1*41ec0267Sriastradh /* $NetBSD: radeon_object.h,v 1.4 2021/12/18 23:45:43 riastradh Exp $ */
2d01ac146Sriastradh
39d20d926Sriastradh /*
49d20d926Sriastradh * Copyright 2008 Advanced Micro Devices, Inc.
59d20d926Sriastradh * Copyright 2008 Red Hat Inc.
69d20d926Sriastradh * Copyright 2009 Jerome Glisse.
79d20d926Sriastradh *
89d20d926Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a
99d20d926Sriastradh * copy of this software and associated documentation files (the "Software"),
109d20d926Sriastradh * to deal in the Software without restriction, including without limitation
119d20d926Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense,
129d20d926Sriastradh * and/or sell copies of the Software, and to permit persons to whom the
139d20d926Sriastradh * Software is furnished to do so, subject to the following conditions:
149d20d926Sriastradh *
159d20d926Sriastradh * The above copyright notice and this permission notice shall be included in
169d20d926Sriastradh * all copies or substantial portions of the Software.
179d20d926Sriastradh *
189d20d926Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
199d20d926Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
209d20d926Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
219d20d926Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
229d20d926Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
239d20d926Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
249d20d926Sriastradh * OTHER DEALINGS IN THE SOFTWARE.
259d20d926Sriastradh *
269d20d926Sriastradh * Authors: Dave Airlie
279d20d926Sriastradh * Alex Deucher
289d20d926Sriastradh * Jerome Glisse
299d20d926Sriastradh */
309d20d926Sriastradh #ifndef __RADEON_OBJECT_H__
319d20d926Sriastradh #define __RADEON_OBJECT_H__
329d20d926Sriastradh
339d20d926Sriastradh #include <drm/radeon_drm.h>
349d20d926Sriastradh #include "radeon.h"
359d20d926Sriastradh
369d20d926Sriastradh /**
379d20d926Sriastradh * radeon_mem_type_to_domain - return domain corresponding to mem_type
389d20d926Sriastradh * @mem_type: ttm memory type
399d20d926Sriastradh *
409d20d926Sriastradh * Returns corresponding domain of the ttm mem_type
419d20d926Sriastradh */
radeon_mem_type_to_domain(u32 mem_type)429d20d926Sriastradh static inline unsigned radeon_mem_type_to_domain(u32 mem_type)
439d20d926Sriastradh {
449d20d926Sriastradh switch (mem_type) {
459d20d926Sriastradh case TTM_PL_VRAM:
469d20d926Sriastradh return RADEON_GEM_DOMAIN_VRAM;
479d20d926Sriastradh case TTM_PL_TT:
489d20d926Sriastradh return RADEON_GEM_DOMAIN_GTT;
499d20d926Sriastradh case TTM_PL_SYSTEM:
509d20d926Sriastradh return RADEON_GEM_DOMAIN_CPU;
519d20d926Sriastradh default:
529d20d926Sriastradh break;
539d20d926Sriastradh }
549d20d926Sriastradh return 0;
559d20d926Sriastradh }
569d20d926Sriastradh
579d20d926Sriastradh /**
589d20d926Sriastradh * radeon_bo_reserve - reserve bo
599d20d926Sriastradh * @bo: bo structure
609d20d926Sriastradh * @no_intr: don't return -ERESTARTSYS on pending signal
619d20d926Sriastradh *
629d20d926Sriastradh * Returns:
639d20d926Sriastradh * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
649d20d926Sriastradh * a signal. Release all buffer reservations and return to user-space.
659d20d926Sriastradh */
radeon_bo_reserve(struct radeon_bo * bo,bool no_intr)669d20d926Sriastradh static inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
679d20d926Sriastradh {
689d20d926Sriastradh int r;
699d20d926Sriastradh
70*41ec0267Sriastradh r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
719d20d926Sriastradh if (unlikely(r != 0)) {
729d20d926Sriastradh if (r != -ERESTARTSYS)
739d20d926Sriastradh dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
749d20d926Sriastradh return r;
759d20d926Sriastradh }
769d20d926Sriastradh return 0;
779d20d926Sriastradh }
789d20d926Sriastradh
radeon_bo_unreserve(struct radeon_bo * bo)799d20d926Sriastradh static inline void radeon_bo_unreserve(struct radeon_bo *bo)
809d20d926Sriastradh {
819d20d926Sriastradh ttm_bo_unreserve(&bo->tbo);
829d20d926Sriastradh }
839d20d926Sriastradh
849d20d926Sriastradh /**
859d20d926Sriastradh * radeon_bo_gpu_offset - return GPU offset of bo
869d20d926Sriastradh * @bo: radeon object for which we query the offset
879d20d926Sriastradh *
889d20d926Sriastradh * Returns current GPU offset of the object.
899d20d926Sriastradh *
909d20d926Sriastradh * Note: object should either be pinned or reserved when calling this
919d20d926Sriastradh * function, it might be useful to add check for this for debugging.
929d20d926Sriastradh */
radeon_bo_gpu_offset(struct radeon_bo * bo)939d20d926Sriastradh static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
949d20d926Sriastradh {
959d20d926Sriastradh return bo->tbo.offset;
969d20d926Sriastradh }
979d20d926Sriastradh
radeon_bo_size(struct radeon_bo * bo)989d20d926Sriastradh static inline unsigned long radeon_bo_size(struct radeon_bo *bo)
999d20d926Sriastradh {
1009d20d926Sriastradh return bo->tbo.num_pages << PAGE_SHIFT;
1019d20d926Sriastradh }
1029d20d926Sriastradh
radeon_bo_ngpu_pages(struct radeon_bo * bo)1039d20d926Sriastradh static inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo)
1049d20d926Sriastradh {
1059d20d926Sriastradh return (bo->tbo.num_pages << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
1069d20d926Sriastradh }
1079d20d926Sriastradh
radeon_bo_gpu_page_alignment(struct radeon_bo * bo)1089d20d926Sriastradh static inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo)
1099d20d926Sriastradh {
1109d20d926Sriastradh return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
1119d20d926Sriastradh }
1129d20d926Sriastradh
1139d20d926Sriastradh /**
1149d20d926Sriastradh * radeon_bo_mmap_offset - return mmap offset of bo
1159d20d926Sriastradh * @bo: radeon object for which we query the offset
1169d20d926Sriastradh *
1179d20d926Sriastradh * Returns mmap offset of the object.
1189d20d926Sriastradh */
radeon_bo_mmap_offset(struct radeon_bo * bo)1199d20d926Sriastradh static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo)
1209d20d926Sriastradh {
121*41ec0267Sriastradh return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
1229d20d926Sriastradh }
1239d20d926Sriastradh
1249d20d926Sriastradh extern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
1259d20d926Sriastradh bool no_wait);
1269d20d926Sriastradh
1279d20d926Sriastradh extern int radeon_bo_create(struct radeon_device *rdev,
1289d20d926Sriastradh unsigned long size, int byte_align,
129d01ac146Sriastradh bool kernel, u32 domain, u32 flags,
1309d20d926Sriastradh struct sg_table *sg,
131*41ec0267Sriastradh struct dma_resv *resv,
1329d20d926Sriastradh struct radeon_bo **bo_ptr);
1339d20d926Sriastradh extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr);
1349d20d926Sriastradh extern void radeon_bo_kunmap(struct radeon_bo *bo);
135d01ac146Sriastradh extern struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo);
1369d20d926Sriastradh extern void radeon_bo_unref(struct radeon_bo **bo);
1379d20d926Sriastradh extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
1389d20d926Sriastradh extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain,
1399d20d926Sriastradh u64 max_offset, u64 *gpu_addr);
1409d20d926Sriastradh extern int radeon_bo_unpin(struct radeon_bo *bo);
1419d20d926Sriastradh extern int radeon_bo_evict_vram(struct radeon_device *rdev);
1429d20d926Sriastradh extern void radeon_bo_force_delete(struct radeon_device *rdev);
1439d20d926Sriastradh extern int radeon_bo_init(struct radeon_device *rdev);
1449d20d926Sriastradh extern void radeon_bo_fini(struct radeon_device *rdev);
1459d20d926Sriastradh extern int radeon_bo_list_validate(struct radeon_device *rdev,
1469d20d926Sriastradh struct ww_acquire_ctx *ticket,
1479d20d926Sriastradh struct list_head *head, int ring);
1489d20d926Sriastradh extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
1499d20d926Sriastradh u32 tiling_flags, u32 pitch);
1509d20d926Sriastradh extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
1519d20d926Sriastradh u32 *tiling_flags, u32 *pitch);
1529d20d926Sriastradh extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
1539d20d926Sriastradh bool force_drop);
1549d20d926Sriastradh extern void radeon_bo_move_notify(struct ttm_buffer_object *bo,
155*41ec0267Sriastradh bool evict,
1569d20d926Sriastradh struct ttm_mem_reg *new_mem);
1579d20d926Sriastradh extern int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
1589d20d926Sriastradh extern int radeon_bo_get_surface_reg(struct radeon_bo *bo);
159d01ac146Sriastradh extern void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
160d01ac146Sriastradh bool shared);
1619d20d926Sriastradh
1629d20d926Sriastradh /*
1639d20d926Sriastradh * sub allocation
1649d20d926Sriastradh */
1659d20d926Sriastradh
radeon_sa_bo_gpu_addr(struct radeon_sa_bo * sa_bo)1669d20d926Sriastradh static inline uint64_t radeon_sa_bo_gpu_addr(struct radeon_sa_bo *sa_bo)
1679d20d926Sriastradh {
1689d20d926Sriastradh return sa_bo->manager->gpu_addr + sa_bo->soffset;
1699d20d926Sriastradh }
1709d20d926Sriastradh
radeon_sa_bo_cpu_addr(struct radeon_sa_bo * sa_bo)1719d20d926Sriastradh static inline void * radeon_sa_bo_cpu_addr(struct radeon_sa_bo *sa_bo)
1729d20d926Sriastradh {
173b81c64e1Sriastradh return (char *)sa_bo->manager->cpu_ptr + sa_bo->soffset;
1749d20d926Sriastradh }
1759d20d926Sriastradh
1769d20d926Sriastradh extern int radeon_sa_bo_manager_init(struct radeon_device *rdev,
1779d20d926Sriastradh struct radeon_sa_manager *sa_manager,
178d01ac146Sriastradh unsigned size, u32 align, u32 domain,
179d01ac146Sriastradh u32 flags);
1809d20d926Sriastradh extern void radeon_sa_bo_manager_fini(struct radeon_device *rdev,
1819d20d926Sriastradh struct radeon_sa_manager *sa_manager);
1829d20d926Sriastradh extern int radeon_sa_bo_manager_start(struct radeon_device *rdev,
1839d20d926Sriastradh struct radeon_sa_manager *sa_manager);
1849d20d926Sriastradh extern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev,
1859d20d926Sriastradh struct radeon_sa_manager *sa_manager);
1869d20d926Sriastradh extern int radeon_sa_bo_new(struct radeon_device *rdev,
1879d20d926Sriastradh struct radeon_sa_manager *sa_manager,
1889d20d926Sriastradh struct radeon_sa_bo **sa_bo,
1899d20d926Sriastradh unsigned size, unsigned align);
1909d20d926Sriastradh extern void radeon_sa_bo_free(struct radeon_device *rdev,
1919d20d926Sriastradh struct radeon_sa_bo **sa_bo,
1929d20d926Sriastradh struct radeon_fence *fence);
1939d20d926Sriastradh #if defined(CONFIG_DEBUG_FS)
1949d20d926Sriastradh extern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager,
1959d20d926Sriastradh struct seq_file *m);
1969d20d926Sriastradh #endif
1979d20d926Sriastradh
1989d20d926Sriastradh
1999d20d926Sriastradh #endif
200