1 /* $NetBSD: uhci.c,v 1.245 2012/03/06 03:35:29 mrg Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart@augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.245 2012/03/06 03:35:29 mrg Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/select.h> 55 #include <sys/extent.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/bus.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/uhcireg.h> 69 #include <dev/usb/uhcivar.h> 70 #include <dev/usb/usbroothub_subr.h> 71 72 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 73 /*#define UHCI_CTL_LOOP */ 74 75 76 77 #ifdef UHCI_DEBUG 78 uhci_softc_t *thesc; 79 #define DPRINTF(x) if (uhcidebug) printf x 80 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 81 int uhcidebug = 0; 82 int uhcinoloop = 0; 83 #else 84 #define DPRINTF(x) 85 #define DPRINTFN(n,x) 86 #endif 87 88 /* 89 * The UHCI controller is little endian, so on big endian machines 90 * the data stored in memory needs to be swapped. 91 */ 92 93 struct uhci_pipe { 94 struct usbd_pipe pipe; 95 int nexttoggle; 96 97 u_char aborting; 98 usbd_xfer_handle abortstart, abortend; 99 100 /* Info needed for different pipe kinds. */ 101 union { 102 /* Control pipe */ 103 struct { 104 uhci_soft_qh_t *sqh; 105 usb_dma_t reqdma; 106 uhci_soft_td_t *setup, *stat; 107 u_int length; 108 } ctl; 109 /* Interrupt pipe */ 110 struct { 111 int npoll; 112 int isread; 113 uhci_soft_qh_t **qhs; 114 } intr; 115 /* Bulk pipe */ 116 struct { 117 uhci_soft_qh_t *sqh; 118 u_int length; 119 int isread; 120 } bulk; 121 /* Iso pipe */ 122 struct iso { 123 uhci_soft_td_t **stds; 124 int next, inuse; 125 } iso; 126 } u; 127 }; 128 129 Static void uhci_globalreset(uhci_softc_t *); 130 Static usbd_status uhci_portreset(uhci_softc_t*, int); 131 Static void uhci_reset(uhci_softc_t *); 132 Static usbd_status uhci_run(uhci_softc_t *, int run); 133 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 134 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 135 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 136 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 137 #if 0 138 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 139 uhci_intr_info_t *); 140 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 141 #endif 142 143 Static void uhci_free_std_chain(uhci_softc_t *, 144 uhci_soft_td_t *, uhci_soft_td_t *); 145 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 146 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 147 uhci_soft_td_t **, uhci_soft_td_t **); 148 Static void uhci_poll_hub(void *); 149 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 150 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 151 Static void uhci_idone(uhci_intr_info_t *); 152 153 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 154 155 Static void uhci_timeout(void *); 156 Static void uhci_timeout_task(void *); 157 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 160 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 163 Static void uhci_add_loop(uhci_softc_t *sc); 164 Static void uhci_rem_loop(uhci_softc_t *sc); 165 166 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 167 Static void uhci_device_isoc_enter(usbd_xfer_handle); 168 169 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 170 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 171 172 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 173 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 174 175 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 176 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 177 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 178 Static void uhci_device_ctrl_close(usbd_pipe_handle); 179 Static void uhci_device_ctrl_done(usbd_xfer_handle); 180 181 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 182 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 183 Static void uhci_device_intr_abort(usbd_xfer_handle); 184 Static void uhci_device_intr_close(usbd_pipe_handle); 185 Static void uhci_device_intr_done(usbd_xfer_handle); 186 187 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 188 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 189 Static void uhci_device_bulk_abort(usbd_xfer_handle); 190 Static void uhci_device_bulk_close(usbd_pipe_handle); 191 Static void uhci_device_bulk_done(usbd_xfer_handle); 192 193 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 194 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 195 Static void uhci_device_isoc_abort(usbd_xfer_handle); 196 Static void uhci_device_isoc_close(usbd_pipe_handle); 197 Static void uhci_device_isoc_done(usbd_xfer_handle); 198 199 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 200 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 201 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 202 Static void uhci_root_ctrl_close(usbd_pipe_handle); 203 Static void uhci_root_ctrl_done(usbd_xfer_handle); 204 205 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 206 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 207 Static void uhci_root_intr_abort(usbd_xfer_handle); 208 Static void uhci_root_intr_close(usbd_pipe_handle); 209 Static void uhci_root_intr_done(usbd_xfer_handle); 210 211 Static usbd_status uhci_open(usbd_pipe_handle); 212 Static void uhci_poll(struct usbd_bus *); 213 Static void uhci_softintr(void *); 214 215 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 216 217 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 218 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 219 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 220 struct uhci_pipe *pipe, int ival); 221 222 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 223 Static void uhci_noop(usbd_pipe_handle pipe); 224 225 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 226 uhci_soft_qh_t *); 227 228 #ifdef UHCI_DEBUG 229 Static void uhci_dump_all(uhci_softc_t *); 230 Static void uhci_dumpregs(uhci_softc_t *); 231 Static void uhci_dump_qhs(uhci_soft_qh_t *); 232 Static void uhci_dump_qh(uhci_soft_qh_t *); 233 Static void uhci_dump_tds(uhci_soft_td_t *); 234 Static void uhci_dump_td(uhci_soft_td_t *); 235 Static void uhci_dump_ii(uhci_intr_info_t *ii); 236 void uhci_dump(void); 237 #endif 238 239 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 240 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 241 #define UWRITE1(sc, r, x) \ 242 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 243 } while (/*CONSTCOND*/0) 244 #define UWRITE2(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 #define UWRITE4(sc, r, x) \ 248 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 249 } while (/*CONSTCOND*/0) 250 static __inline uint8_t 251 UREAD1(uhci_softc_t *sc, bus_size_t r) 252 { 253 254 UBARR(sc); 255 return bus_space_read_1(sc->iot, sc->ioh, r); 256 } 257 258 static __inline uint16_t 259 UREAD2(uhci_softc_t *sc, bus_size_t r) 260 { 261 262 UBARR(sc); 263 return bus_space_read_2(sc->iot, sc->ioh, r); 264 } 265 266 static __inline uint32_t 267 UREAD4(uhci_softc_t *sc, bus_size_t r) 268 { 269 270 UBARR(sc); 271 return bus_space_read_4(sc->iot, sc->ioh, r); 272 } 273 274 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 275 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 276 277 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 278 279 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 280 281 #define UHCI_INTR_ENDPT 1 282 283 const struct usbd_bus_methods uhci_bus_methods = { 284 .open_pipe = uhci_open, 285 .soft_intr = uhci_softintr, 286 .do_poll = uhci_poll, 287 .allocm = uhci_allocm, 288 .freem = uhci_freem, 289 .allocx = uhci_allocx, 290 .freex = uhci_freex, 291 }; 292 293 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 294 .transfer = uhci_root_ctrl_transfer, 295 .start = uhci_root_ctrl_start, 296 .abort = uhci_root_ctrl_abort, 297 .close = uhci_root_ctrl_close, 298 .cleartoggle = uhci_noop, 299 .done = uhci_root_ctrl_done, 300 }; 301 302 const struct usbd_pipe_methods uhci_root_intr_methods = { 303 .transfer = uhci_root_intr_transfer, 304 .start = uhci_root_intr_start, 305 .abort = uhci_root_intr_abort, 306 .close = uhci_root_intr_close, 307 .cleartoggle = uhci_noop, 308 .done = uhci_root_intr_done, 309 }; 310 311 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 312 .transfer = uhci_device_ctrl_transfer, 313 .start = uhci_device_ctrl_start, 314 .abort = uhci_device_ctrl_abort, 315 .close = uhci_device_ctrl_close, 316 .cleartoggle = uhci_noop, 317 .done = uhci_device_ctrl_done, 318 }; 319 320 const struct usbd_pipe_methods uhci_device_intr_methods = { 321 .transfer = uhci_device_intr_transfer, 322 .start = uhci_device_intr_start, 323 .abort = uhci_device_intr_abort, 324 .close = uhci_device_intr_close, 325 .cleartoggle = uhci_device_clear_toggle, 326 .done = uhci_device_intr_done, 327 }; 328 329 const struct usbd_pipe_methods uhci_device_bulk_methods = { 330 .transfer = uhci_device_bulk_transfer, 331 .start = uhci_device_bulk_start, 332 .abort = uhci_device_bulk_abort, 333 .close = uhci_device_bulk_close, 334 .cleartoggle = uhci_device_clear_toggle, 335 .done = uhci_device_bulk_done, 336 }; 337 338 const struct usbd_pipe_methods uhci_device_isoc_methods = { 339 .transfer = uhci_device_isoc_transfer, 340 .start = uhci_device_isoc_start, 341 .abort = uhci_device_isoc_abort, 342 .close = uhci_device_isoc_close, 343 .cleartoggle = uhci_noop, 344 .done = uhci_device_isoc_done, 345 }; 346 347 #define uhci_add_intr_info(sc, ii) \ 348 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 349 #define uhci_del_intr_info(ii) \ 350 do { \ 351 LIST_REMOVE((ii), list); \ 352 (ii)->list.le_prev = NULL; \ 353 } while (0) 354 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 355 356 static inline uhci_soft_qh_t * 357 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 358 { 359 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 360 361 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 362 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 363 usb_syncmem(&pqh->dma, 364 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 365 sizeof(pqh->qh.qh_hlink), 366 BUS_DMASYNC_POSTWRITE); 367 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 368 printf("uhci_find_prev_qh: QH not found\n"); 369 return (NULL); 370 } 371 #endif 372 } 373 return (pqh); 374 } 375 376 void 377 uhci_globalreset(uhci_softc_t *sc) 378 { 379 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 380 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 381 UHCICMD(sc, 0); /* do nothing */ 382 } 383 384 usbd_status 385 uhci_init(uhci_softc_t *sc) 386 { 387 usbd_status err; 388 int i, j; 389 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 390 uhci_soft_td_t *std; 391 392 DPRINTFN(1,("uhci_init: start\n")); 393 394 #ifdef UHCI_DEBUG 395 thesc = sc; 396 397 if (uhcidebug > 2) 398 uhci_dumpregs(sc); 399 #endif 400 401 sc->sc_suspend = PWR_RESUME; 402 403 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 404 uhci_globalreset(sc); /* reset the controller */ 405 uhci_reset(sc); 406 407 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 408 USB_MEM_RESERVE); 409 410 /* Allocate and initialize real frame array. */ 411 err = usb_allocmem(&sc->sc_bus, 412 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 413 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 414 if (err) 415 return (err); 416 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 417 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 418 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 419 420 /* 421 * Allocate a TD, inactive, that hangs from the last QH. 422 * This is to avoid a bug in the PIIX that makes it run berserk 423 * otherwise. 424 */ 425 std = uhci_alloc_std(sc); 426 if (std == NULL) 427 return (USBD_NOMEM); 428 std->link.std = NULL; 429 std->td.td_link = htole32(UHCI_PTR_T); 430 std->td.td_status = htole32(0); /* inactive */ 431 std->td.td_token = htole32(0); 432 std->td.td_buffer = htole32(0); 433 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 434 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 435 436 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 437 lsqh = uhci_alloc_sqh(sc); 438 if (lsqh == NULL) 439 return (USBD_NOMEM); 440 lsqh->hlink = NULL; 441 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 442 lsqh->elink = std; 443 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 444 sc->sc_last_qh = lsqh; 445 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 446 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 447 448 /* Allocate the dummy QH where bulk traffic will be queued. */ 449 bsqh = uhci_alloc_sqh(sc); 450 if (bsqh == NULL) 451 return (USBD_NOMEM); 452 bsqh->hlink = lsqh; 453 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 454 bsqh->elink = NULL; 455 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 456 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 457 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 458 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 459 460 /* Allocate dummy QH where high speed control traffic will be queued. */ 461 chsqh = uhci_alloc_sqh(sc); 462 if (chsqh == NULL) 463 return (USBD_NOMEM); 464 chsqh->hlink = bsqh; 465 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 466 chsqh->elink = NULL; 467 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 468 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 469 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 470 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 471 472 /* Allocate dummy QH where control traffic will be queued. */ 473 clsqh = uhci_alloc_sqh(sc); 474 if (clsqh == NULL) 475 return (USBD_NOMEM); 476 clsqh->hlink = chsqh; 477 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 478 clsqh->elink = NULL; 479 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 480 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 481 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 482 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 483 484 /* 485 * Make all (virtual) frame list pointers point to the interrupt 486 * queue heads and the interrupt queue heads at the control 487 * queue head and point the physical frame list to the virtual. 488 */ 489 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 490 std = uhci_alloc_std(sc); 491 sqh = uhci_alloc_sqh(sc); 492 if (std == NULL || sqh == NULL) 493 return (USBD_NOMEM); 494 std->link.sqh = sqh; 495 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 496 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 497 std->td.td_token = htole32(0); 498 std->td.td_buffer = htole32(0); 499 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 500 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 501 sqh->hlink = clsqh; 502 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 503 sqh->elink = NULL; 504 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 505 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 506 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 507 sc->sc_vframes[i].htd = std; 508 sc->sc_vframes[i].etd = std; 509 sc->sc_vframes[i].hqh = sqh; 510 sc->sc_vframes[i].eqh = sqh; 511 for (j = i; 512 j < UHCI_FRAMELIST_COUNT; 513 j += UHCI_VFRAMELIST_COUNT) 514 sc->sc_pframes[j] = htole32(std->physaddr); 515 } 516 usb_syncmem(&sc->sc_dma, 0, 517 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 518 BUS_DMASYNC_PREWRITE); 519 520 521 LIST_INIT(&sc->sc_intrhead); 522 523 SIMPLEQ_INIT(&sc->sc_free_xfers); 524 525 callout_init(&sc->sc_poll_handle, 0); 526 527 /* Set up the bus struct. */ 528 sc->sc_bus.methods = &uhci_bus_methods; 529 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 530 531 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 532 533 DPRINTFN(1,("uhci_init: enabling\n")); 534 535 err = uhci_run(sc, 1); /* and here we go... */ 536 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 537 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 538 return err; 539 } 540 541 int 542 uhci_activate(device_t self, enum devact act) 543 { 544 struct uhci_softc *sc = device_private(self); 545 546 switch (act) { 547 case DVACT_DEACTIVATE: 548 sc->sc_dying = 1; 549 return 0; 550 default: 551 return EOPNOTSUPP; 552 } 553 } 554 555 void 556 uhci_childdet(device_t self, device_t child) 557 { 558 struct uhci_softc *sc = device_private(self); 559 560 KASSERT(sc->sc_child == child); 561 sc->sc_child = NULL; 562 } 563 564 int 565 uhci_detach(struct uhci_softc *sc, int flags) 566 { 567 usbd_xfer_handle xfer; 568 int rv = 0; 569 570 if (sc->sc_child != NULL) 571 rv = config_detach(sc->sc_child, flags); 572 573 if (rv != 0) 574 return (rv); 575 576 /* Free all xfers associated with this HC. */ 577 for (;;) { 578 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 579 if (xfer == NULL) 580 break; 581 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 582 free(xfer, M_USB); 583 } 584 585 callout_halt(&sc->sc_poll_handle, NULL); 586 callout_destroy(&sc->sc_poll_handle); 587 588 /* XXX free other data structures XXX */ 589 590 return (rv); 591 } 592 593 usbd_status 594 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 595 { 596 struct uhci_softc *sc = bus->hci_private; 597 usbd_status status; 598 u_int32_t n; 599 600 /* 601 * XXX 602 * Since we are allocating a buffer we can assume that we will 603 * need TDs for it. Since we don't want to allocate those from 604 * an interrupt context, we allocate them here and free them again. 605 * This is no guarantee that we'll get the TDs next time... 606 */ 607 n = size / 8; 608 if (n > 16) { 609 u_int32_t i; 610 uhci_soft_td_t **stds; 611 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 612 stds = malloc(sizeof(uhci_soft_td_t *) * n, M_TEMP, 613 M_WAITOK|M_ZERO); 614 for(i=0; i < n; i++) 615 stds[i] = uhci_alloc_std(sc); 616 for(i=0; i < n; i++) 617 if (stds[i] != NULL) 618 uhci_free_std(sc, stds[i]); 619 free(stds, M_TEMP); 620 } 621 622 623 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 624 if (status == USBD_NOMEM) 625 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 626 return status; 627 } 628 629 void 630 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 631 { 632 if (dma->block->flags & USB_DMA_RESERVE) { 633 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 634 dma); 635 return; 636 } 637 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 638 } 639 640 usbd_xfer_handle 641 uhci_allocx(struct usbd_bus *bus) 642 { 643 struct uhci_softc *sc = bus->hci_private; 644 usbd_xfer_handle xfer; 645 646 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 647 if (xfer != NULL) { 648 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 649 #ifdef DIAGNOSTIC 650 if (xfer->busy_free != XFER_FREE) { 651 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 652 xfer->busy_free); 653 } 654 #endif 655 } else { 656 xfer = malloc(sizeof(struct uhci_xfer), M_USB, M_NOWAIT); 657 } 658 if (xfer != NULL) { 659 memset(xfer, 0, sizeof (struct uhci_xfer)); 660 UXFER(xfer)->iinfo.sc = sc; 661 #ifdef DIAGNOSTIC 662 UXFER(xfer)->iinfo.isdone = 1; 663 xfer->busy_free = XFER_BUSY; 664 #endif 665 } 666 return (xfer); 667 } 668 669 void 670 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 671 { 672 struct uhci_softc *sc = bus->hci_private; 673 674 #ifdef DIAGNOSTIC 675 if (xfer->busy_free != XFER_BUSY) { 676 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 677 xfer->busy_free); 678 } 679 xfer->busy_free = XFER_FREE; 680 if (!UXFER(xfer)->iinfo.isdone) { 681 printf("uhci_freex: !isdone\n"); 682 } 683 #endif 684 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 685 } 686 687 /* 688 * Handle suspend/resume. 689 * 690 * We need to switch to polling mode here, because this routine is 691 * called from an interrupt context. This is all right since we 692 * are almost suspended anyway. 693 */ 694 bool 695 uhci_resume(device_t dv, const pmf_qual_t *qual) 696 { 697 uhci_softc_t *sc = device_private(dv); 698 int cmd; 699 int s; 700 701 s = splhardusb(); 702 703 cmd = UREAD2(sc, UHCI_CMD); 704 sc->sc_bus.use_polling++; 705 UWRITE2(sc, UHCI_INTR, 0); 706 uhci_globalreset(sc); 707 uhci_reset(sc); 708 if (cmd & UHCI_CMD_RS) 709 uhci_run(sc, 0); 710 711 /* restore saved state */ 712 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 713 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 714 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 715 716 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 717 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 718 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 719 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 720 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 721 UHCICMD(sc, UHCI_CMD_MAXP); 722 uhci_run(sc, 1); /* and start traffic again */ 723 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 724 sc->sc_bus.use_polling--; 725 if (sc->sc_intr_xfer != NULL) 726 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 727 sc->sc_intr_xfer); 728 #ifdef UHCI_DEBUG 729 if (uhcidebug > 2) 730 uhci_dumpregs(sc); 731 #endif 732 733 sc->sc_suspend = PWR_RESUME; 734 splx(s); 735 736 return true; 737 } 738 739 bool 740 uhci_suspend(device_t dv, const pmf_qual_t *qual) 741 { 742 uhci_softc_t *sc = device_private(dv); 743 int cmd; 744 int s; 745 746 s = splhardusb(); 747 748 cmd = UREAD2(sc, UHCI_CMD); 749 750 #ifdef UHCI_DEBUG 751 if (uhcidebug > 2) 752 uhci_dumpregs(sc); 753 #endif 754 if (sc->sc_intr_xfer != NULL) 755 callout_stop(&sc->sc_poll_handle); 756 sc->sc_suspend = PWR_SUSPEND; 757 sc->sc_bus.use_polling++; 758 759 uhci_run(sc, 0); /* stop the controller */ 760 cmd &= ~UHCI_CMD_RS; 761 762 /* save some state if BIOS doesn't */ 763 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 764 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 765 766 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 767 768 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 769 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 770 sc->sc_bus.use_polling--; 771 772 splx(s); 773 774 return true; 775 } 776 777 #ifdef UHCI_DEBUG 778 Static void 779 uhci_dumpregs(uhci_softc_t *sc) 780 { 781 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 782 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 783 device_xname(sc->sc_dev), 784 UREAD2(sc, UHCI_CMD), 785 UREAD2(sc, UHCI_STS), 786 UREAD2(sc, UHCI_INTR), 787 UREAD2(sc, UHCI_FRNUM), 788 UREAD4(sc, UHCI_FLBASEADDR), 789 UREAD1(sc, UHCI_SOF), 790 UREAD2(sc, UHCI_PORTSC1), 791 UREAD2(sc, UHCI_PORTSC2))); 792 } 793 794 void 795 uhci_dump_td(uhci_soft_td_t *p) 796 { 797 char sbuf[128], sbuf2[128]; 798 799 800 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 801 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 802 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 803 "token=0x%08lx buffer=0x%08lx\n", 804 p, (long)p->physaddr, 805 (long)le32toh(p->td.td_link), 806 (long)le32toh(p->td.td_status), 807 (long)le32toh(p->td.td_token), 808 (long)le32toh(p->td.td_buffer))); 809 810 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 811 (u_int32_t)le32toh(p->td.td_link)); 812 snprintb(sbuf2, sizeof(sbuf2), 813 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 814 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 815 (u_int32_t)le32toh(p->td.td_status)); 816 817 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 818 "D=%d,maxlen=%d\n", sbuf, sbuf2, 819 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 820 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 821 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 822 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 823 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 824 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 825 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 826 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 827 BUS_DMASYNC_PREREAD); 828 } 829 830 void 831 uhci_dump_qh(uhci_soft_qh_t *sqh) 832 { 833 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 834 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 835 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 836 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 837 le32toh(sqh->qh.qh_elink))); 838 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 839 } 840 841 842 #if 1 843 void 844 uhci_dump(void) 845 { 846 uhci_dump_all(thesc); 847 } 848 #endif 849 850 void 851 uhci_dump_all(uhci_softc_t *sc) 852 { 853 uhci_dumpregs(sc); 854 printf("intrs=%d\n", sc->sc_bus.no_intrs); 855 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 856 uhci_dump_qh(sc->sc_lctl_start); 857 } 858 859 860 void 861 uhci_dump_qhs(uhci_soft_qh_t *sqh) 862 { 863 uhci_dump_qh(sqh); 864 865 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 866 * Traverses sideways first, then down. 867 * 868 * QH1 869 * QH2 870 * No QH 871 * TD2.1 872 * TD2.2 873 * TD1.1 874 * etc. 875 * 876 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 877 */ 878 879 880 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 881 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 882 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 883 uhci_dump_qhs(sqh->hlink); 884 else 885 DPRINTF(("No QH\n")); 886 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 887 888 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 889 uhci_dump_tds(sqh->elink); 890 else 891 DPRINTF(("No TD\n")); 892 } 893 894 void 895 uhci_dump_tds(uhci_soft_td_t *std) 896 { 897 uhci_soft_td_t *td; 898 int stop; 899 900 for(td = std; td != NULL; td = td->link.std) { 901 uhci_dump_td(td); 902 903 /* Check whether the link pointer in this TD marks 904 * the link pointer as end of queue. This avoids 905 * printing the free list in case the queue/TD has 906 * already been moved there (seatbelt). 907 */ 908 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 909 sizeof(td->td.td_link), 910 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 911 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 912 le32toh(td->td.td_link) == 0); 913 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 914 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 915 if (stop) 916 break; 917 } 918 } 919 920 Static void 921 uhci_dump_ii(uhci_intr_info_t *ii) 922 { 923 usbd_pipe_handle pipe; 924 usb_endpoint_descriptor_t *ed; 925 usbd_device_handle dev; 926 927 #ifdef DIAGNOSTIC 928 #define DONE ii->isdone 929 #else 930 #define DONE 0 931 #endif 932 if (ii == NULL) { 933 printf("ii NULL\n"); 934 return; 935 } 936 if (ii->xfer == NULL) { 937 printf("ii %p: done=%d xfer=NULL\n", 938 ii, DONE); 939 return; 940 } 941 pipe = ii->xfer->pipe; 942 if (pipe == NULL) { 943 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 944 ii, DONE, ii->xfer); 945 return; 946 } 947 if (pipe->endpoint == NULL) { 948 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 949 ii, DONE, ii->xfer, pipe); 950 return; 951 } 952 if (pipe->device == NULL) { 953 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 954 ii, DONE, ii->xfer, pipe); 955 return; 956 } 957 ed = pipe->endpoint->edesc; 958 dev = pipe->device; 959 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 960 ii, DONE, ii->xfer, dev, 961 UGETW(dev->ddesc.idVendor), 962 UGETW(dev->ddesc.idProduct), 963 dev->address, pipe, 964 ed->bEndpointAddress, ed->bmAttributes); 965 #undef DONE 966 } 967 968 void uhci_dump_iis(struct uhci_softc *sc); 969 void 970 uhci_dump_iis(struct uhci_softc *sc) 971 { 972 uhci_intr_info_t *ii; 973 974 printf("intr_info list:\n"); 975 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 976 uhci_dump_ii(ii); 977 } 978 979 void iidump(void); 980 void iidump(void) { uhci_dump_iis(thesc); } 981 982 #endif 983 984 /* 985 * This routine is executed periodically and simulates interrupts 986 * from the root controller interrupt pipe for port status change. 987 */ 988 void 989 uhci_poll_hub(void *addr) 990 { 991 usbd_xfer_handle xfer = addr; 992 usbd_pipe_handle pipe = xfer->pipe; 993 uhci_softc_t *sc; 994 int s; 995 u_char *p; 996 997 DPRINTFN(20, ("uhci_poll_hub\n")); 998 999 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1000 return; /* device has detached */ 1001 sc = pipe->device->bus->hci_private; 1002 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1003 1004 p = KERNADDR(&xfer->dmabuf, 0); 1005 p[0] = 0; 1006 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1007 p[0] |= 1<<1; 1008 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<2; 1010 if (p[0] == 0) 1011 /* No change, try again in a while */ 1012 return; 1013 1014 xfer->actlen = 1; 1015 xfer->status = USBD_NORMAL_COMPLETION; 1016 s = splusb(); 1017 xfer->device->bus->intr_context++; 1018 usb_transfer_complete(xfer); 1019 xfer->device->bus->intr_context--; 1020 splx(s); 1021 } 1022 1023 void 1024 uhci_root_intr_done(usbd_xfer_handle xfer) 1025 { 1026 } 1027 1028 void 1029 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1030 { 1031 } 1032 1033 /* 1034 * Let the last QH loop back to the high speed control transfer QH. 1035 * This is what intel calls "bandwidth reclamation" and improves 1036 * USB performance a lot for some devices. 1037 * If we are already looping, just count it. 1038 */ 1039 void 1040 uhci_add_loop(uhci_softc_t *sc) { 1041 #ifdef UHCI_DEBUG 1042 if (uhcinoloop) 1043 return; 1044 #endif 1045 if (++sc->sc_loops == 1) { 1046 DPRINTFN(5,("uhci_start_loop: add\n")); 1047 /* Note, we don't loop back the soft pointer. */ 1048 sc->sc_last_qh->qh.qh_hlink = 1049 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1050 usb_syncmem(&sc->sc_last_qh->dma, 1051 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1052 sizeof(sc->sc_last_qh->qh.qh_hlink), 1053 BUS_DMASYNC_PREWRITE); 1054 } 1055 } 1056 1057 void 1058 uhci_rem_loop(uhci_softc_t *sc) { 1059 #ifdef UHCI_DEBUG 1060 if (uhcinoloop) 1061 return; 1062 #endif 1063 if (--sc->sc_loops == 0) { 1064 DPRINTFN(5,("uhci_end_loop: remove\n")); 1065 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1066 usb_syncmem(&sc->sc_last_qh->dma, 1067 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1068 sizeof(sc->sc_last_qh->qh.qh_hlink), 1069 BUS_DMASYNC_PREWRITE); 1070 } 1071 } 1072 1073 /* Add high speed control QH, called at splusb(). */ 1074 void 1075 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1076 { 1077 uhci_soft_qh_t *eqh; 1078 1079 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1080 eqh = sc->sc_hctl_end; 1081 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1082 sizeof(eqh->qh.qh_hlink), 1083 BUS_DMASYNC_POSTWRITE); 1084 sqh->hlink = eqh->hlink; 1085 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1086 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1087 BUS_DMASYNC_PREWRITE); 1088 eqh->hlink = sqh; 1089 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1090 sc->sc_hctl_end = sqh; 1091 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1092 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1093 #ifdef UHCI_CTL_LOOP 1094 uhci_add_loop(sc); 1095 #endif 1096 } 1097 1098 /* Remove high speed control QH, called at splusb(). */ 1099 void 1100 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1101 { 1102 uhci_soft_qh_t *pqh; 1103 1104 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1105 #ifdef UHCI_CTL_LOOP 1106 uhci_rem_loop(sc); 1107 #endif 1108 /* 1109 * The T bit should be set in the elink of the QH so that the HC 1110 * doesn't follow the pointer. This condition may fail if the 1111 * the transferred packet was short so that the QH still points 1112 * at the last used TD. 1113 * In this case we set the T bit and wait a little for the HC 1114 * to stop looking at the TD. 1115 * Note that if the TD chain is large enough, the controller 1116 * may still be looking at the chain at the end of this function. 1117 * uhci_free_std_chain() will make sure the controller stops 1118 * looking at it quickly, but until then we should not change 1119 * sqh->hlink. 1120 */ 1121 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1122 sizeof(sqh->qh.qh_elink), 1123 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1124 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1125 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1126 usb_syncmem(&sqh->dma, 1127 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1128 sizeof(sqh->qh.qh_elink), 1129 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1130 delay(UHCI_QH_REMOVE_DELAY); 1131 } 1132 1133 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1134 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1135 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1136 pqh->hlink = sqh->hlink; 1137 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1138 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1139 sizeof(pqh->qh.qh_hlink), 1140 BUS_DMASYNC_PREWRITE); 1141 delay(UHCI_QH_REMOVE_DELAY); 1142 if (sc->sc_hctl_end == sqh) 1143 sc->sc_hctl_end = pqh; 1144 } 1145 1146 /* Add low speed control QH, called at splusb(). */ 1147 void 1148 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1149 { 1150 uhci_soft_qh_t *eqh; 1151 1152 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1153 eqh = sc->sc_lctl_end; 1154 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1155 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1156 sqh->hlink = eqh->hlink; 1157 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1158 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1159 BUS_DMASYNC_PREWRITE); 1160 eqh->hlink = sqh; 1161 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1162 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1163 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1164 sc->sc_lctl_end = sqh; 1165 } 1166 1167 /* Remove low speed control QH, called at splusb(). */ 1168 void 1169 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1170 { 1171 uhci_soft_qh_t *pqh; 1172 1173 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1174 /* See comment in uhci_remove_hs_ctrl() */ 1175 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1176 sizeof(sqh->qh.qh_elink), 1177 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1178 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1179 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1180 usb_syncmem(&sqh->dma, 1181 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1182 sizeof(sqh->qh.qh_elink), 1183 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1184 delay(UHCI_QH_REMOVE_DELAY); 1185 } 1186 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1187 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1188 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1189 pqh->hlink = sqh->hlink; 1190 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1191 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1192 sizeof(pqh->qh.qh_hlink), 1193 BUS_DMASYNC_PREWRITE); 1194 delay(UHCI_QH_REMOVE_DELAY); 1195 if (sc->sc_lctl_end == sqh) 1196 sc->sc_lctl_end = pqh; 1197 } 1198 1199 /* Add bulk QH, called at splusb(). */ 1200 void 1201 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1202 { 1203 uhci_soft_qh_t *eqh; 1204 1205 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1206 eqh = sc->sc_bulk_end; 1207 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1208 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1209 sqh->hlink = eqh->hlink; 1210 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1211 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1212 BUS_DMASYNC_PREWRITE); 1213 eqh->hlink = sqh; 1214 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1215 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1216 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1217 sc->sc_bulk_end = sqh; 1218 uhci_add_loop(sc); 1219 } 1220 1221 /* Remove bulk QH, called at splusb(). */ 1222 void 1223 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1224 { 1225 uhci_soft_qh_t *pqh; 1226 1227 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1228 uhci_rem_loop(sc); 1229 /* See comment in uhci_remove_hs_ctrl() */ 1230 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1231 sizeof(sqh->qh.qh_elink), 1232 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1233 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1234 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1235 usb_syncmem(&sqh->dma, 1236 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1237 sizeof(sqh->qh.qh_elink), 1238 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1239 delay(UHCI_QH_REMOVE_DELAY); 1240 } 1241 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1242 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1243 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1244 pqh->hlink = sqh->hlink; 1245 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1246 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1247 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1248 delay(UHCI_QH_REMOVE_DELAY); 1249 if (sc->sc_bulk_end == sqh) 1250 sc->sc_bulk_end = pqh; 1251 } 1252 1253 Static int uhci_intr1(uhci_softc_t *); 1254 1255 int 1256 uhci_intr(void *arg) 1257 { 1258 uhci_softc_t *sc = arg; 1259 1260 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1261 return (0); 1262 1263 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1264 #ifdef DIAGNOSTIC 1265 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1266 #endif 1267 return (0); 1268 } 1269 1270 return (uhci_intr1(sc)); 1271 } 1272 1273 int 1274 uhci_intr1(uhci_softc_t *sc) 1275 { 1276 int status; 1277 int ack; 1278 1279 #ifdef UHCI_DEBUG 1280 if (uhcidebug > 15) { 1281 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1282 uhci_dumpregs(sc); 1283 } 1284 #endif 1285 1286 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1287 if (status == 0) /* The interrupt was not for us. */ 1288 return (0); 1289 1290 if (sc->sc_suspend != PWR_RESUME) { 1291 #ifdef DIAGNOSTIC 1292 printf("%s: interrupt while not operating ignored\n", 1293 device_xname(sc->sc_dev)); 1294 #endif 1295 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1296 return (0); 1297 } 1298 1299 ack = 0; 1300 if (status & UHCI_STS_USBINT) 1301 ack |= UHCI_STS_USBINT; 1302 if (status & UHCI_STS_USBEI) 1303 ack |= UHCI_STS_USBEI; 1304 if (status & UHCI_STS_RD) { 1305 ack |= UHCI_STS_RD; 1306 #ifdef UHCI_DEBUG 1307 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1308 #endif 1309 } 1310 if (status & UHCI_STS_HSE) { 1311 ack |= UHCI_STS_HSE; 1312 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1313 } 1314 if (status & UHCI_STS_HCPE) { 1315 ack |= UHCI_STS_HCPE; 1316 printf("%s: host controller process error\n", 1317 device_xname(sc->sc_dev)); 1318 } 1319 1320 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1321 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1322 /* no acknowledge needed */ 1323 if (!sc->sc_dying) { 1324 printf("%s: host controller halted\n", 1325 device_xname(sc->sc_dev)); 1326 #ifdef UHCI_DEBUG 1327 uhci_dump_all(sc); 1328 #endif 1329 } 1330 sc->sc_dying = 1; 1331 } 1332 1333 if (!ack) 1334 return (0); /* nothing to acknowledge */ 1335 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1336 1337 sc->sc_bus.no_intrs++; 1338 usb_schedsoftintr(&sc->sc_bus); 1339 1340 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1341 1342 return (1); 1343 } 1344 1345 void 1346 uhci_softintr(void *v) 1347 { 1348 struct usbd_bus *bus = v; 1349 uhci_softc_t *sc = bus->hci_private; 1350 uhci_intr_info_t *ii, *nextii; 1351 1352 DPRINTFN(10,("%s: uhci_softintr (%d)\n", device_xname(sc->sc_dev), 1353 sc->sc_bus.intr_context)); 1354 1355 sc->sc_bus.intr_context++; 1356 1357 /* 1358 * Interrupts on UHCI really suck. When the host controller 1359 * interrupts because a transfer is completed there is no 1360 * way of knowing which transfer it was. You can scan down 1361 * the TDs and QHs of the previous frame to limit the search, 1362 * but that assumes that the interrupt was not delayed by more 1363 * than 1 ms, which may not always be true (e.g. after debug 1364 * output on a slow console). 1365 * We scan all interrupt descriptors to see if any have 1366 * completed. 1367 */ 1368 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1369 nextii = LIST_NEXT(ii, list); 1370 uhci_check_intr(sc, ii); 1371 } 1372 1373 if (sc->sc_softwake) { 1374 sc->sc_softwake = 0; 1375 wakeup(&sc->sc_softwake); 1376 } 1377 1378 sc->sc_bus.intr_context--; 1379 } 1380 1381 /* Check for an interrupt. */ 1382 void 1383 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1384 { 1385 uhci_soft_td_t *std, *lstd; 1386 u_int32_t status; 1387 1388 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1389 #ifdef DIAGNOSTIC 1390 if (ii == NULL) { 1391 printf("uhci_check_intr: no ii? %p\n", ii); 1392 return; 1393 } 1394 #endif 1395 if (ii->xfer->status == USBD_CANCELLED || 1396 ii->xfer->status == USBD_TIMEOUT) { 1397 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1398 return; 1399 } 1400 1401 if (ii->stdstart == NULL) 1402 return; 1403 lstd = ii->stdend; 1404 #ifdef DIAGNOSTIC 1405 if (lstd == NULL) { 1406 printf("uhci_check_intr: std==0\n"); 1407 return; 1408 } 1409 #endif 1410 /* 1411 * If the last TD is still active we need to check whether there 1412 * is an error somewhere in the middle, or whether there was a 1413 * short packet (SPD and not ACTIVE). 1414 */ 1415 usb_syncmem(&lstd->dma, 1416 lstd->offs + offsetof(uhci_td_t, td_status), 1417 sizeof(lstd->td.td_status), 1418 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1419 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) { 1420 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1421 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1422 usb_syncmem(&std->dma, 1423 std->offs + offsetof(uhci_td_t, td_status), 1424 sizeof(std->td.td_status), 1425 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1426 status = le32toh(std->td.td_status); 1427 usb_syncmem(&std->dma, 1428 std->offs + offsetof(uhci_td_t, td_status), 1429 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1430 /* If there's an active TD the xfer isn't done. */ 1431 if (status & UHCI_TD_ACTIVE) 1432 break; 1433 /* Any kind of error makes the xfer done. */ 1434 if (status & UHCI_TD_STALLED) 1435 goto done; 1436 /* We want short packets, and it is short: it's done */ 1437 usb_syncmem(&std->dma, 1438 std->offs + offsetof(uhci_td_t, td_token), 1439 sizeof(std->td.td_token), 1440 BUS_DMASYNC_POSTWRITE); 1441 if ((status & UHCI_TD_SPD) && 1442 UHCI_TD_GET_ACTLEN(status) < 1443 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1444 goto done; 1445 } 1446 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1447 ii, ii->stdstart)); 1448 usb_syncmem(&lstd->dma, 1449 lstd->offs + offsetof(uhci_td_t, td_status), 1450 sizeof(lstd->td.td_status), 1451 BUS_DMASYNC_PREREAD); 1452 return; 1453 } 1454 done: 1455 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1456 callout_stop(&ii->xfer->timeout_handle); 1457 uhci_idone(ii); 1458 } 1459 1460 /* Called at splusb() */ 1461 void 1462 uhci_idone(uhci_intr_info_t *ii) 1463 { 1464 usbd_xfer_handle xfer = ii->xfer; 1465 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1466 uhci_soft_td_t *std; 1467 u_int32_t status = 0, nstatus; 1468 int actlen; 1469 1470 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1471 #ifdef DIAGNOSTIC 1472 { 1473 int s = splhigh(); 1474 if (ii->isdone) { 1475 splx(s); 1476 #ifdef UHCI_DEBUG 1477 printf("uhci_idone: ii is done!\n "); 1478 uhci_dump_ii(ii); 1479 #else 1480 printf("uhci_idone: ii=%p is done!\n", ii); 1481 #endif 1482 return; 1483 } 1484 ii->isdone = 1; 1485 splx(s); 1486 } 1487 #endif 1488 1489 if (xfer->nframes != 0) { 1490 /* Isoc transfer, do things differently. */ 1491 uhci_soft_td_t **stds = upipe->u.iso.stds; 1492 int i, n, nframes, len; 1493 1494 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1495 1496 nframes = xfer->nframes; 1497 actlen = 0; 1498 n = UXFER(xfer)->curframe; 1499 for (i = 0; i < nframes; i++) { 1500 std = stds[n]; 1501 #ifdef UHCI_DEBUG 1502 if (uhcidebug > 5) { 1503 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1504 uhci_dump_td(std); 1505 } 1506 #endif 1507 if (++n >= UHCI_VFRAMELIST_COUNT) 1508 n = 0; 1509 usb_syncmem(&std->dma, 1510 std->offs + offsetof(uhci_td_t, td_status), 1511 sizeof(std->td.td_status), 1512 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1513 status = le32toh(std->td.td_status); 1514 len = UHCI_TD_GET_ACTLEN(status); 1515 xfer->frlengths[i] = len; 1516 actlen += len; 1517 } 1518 upipe->u.iso.inuse -= nframes; 1519 xfer->actlen = actlen; 1520 xfer->status = USBD_NORMAL_COMPLETION; 1521 goto end; 1522 } 1523 1524 #ifdef UHCI_DEBUG 1525 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1526 ii, xfer, upipe)); 1527 if (uhcidebug > 10) 1528 uhci_dump_tds(ii->stdstart); 1529 #endif 1530 1531 /* The transfer is done, compute actual length and status. */ 1532 actlen = 0; 1533 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1534 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1535 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1536 nstatus = le32toh(std->td.td_status); 1537 if (nstatus & UHCI_TD_ACTIVE) 1538 break; 1539 1540 status = nstatus; 1541 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1542 UHCI_TD_PID_SETUP) 1543 actlen += UHCI_TD_GET_ACTLEN(status); 1544 else { 1545 /* 1546 * UHCI will report CRCTO in addition to a STALL or NAK 1547 * for a SETUP transaction. See section 3.2.2, "TD 1548 * CONTROL AND STATUS". 1549 */ 1550 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1551 status &= ~UHCI_TD_CRCTO; 1552 } 1553 } 1554 /* If there are left over TDs we need to update the toggle. */ 1555 if (std != NULL) 1556 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1557 1558 status &= UHCI_TD_ERROR; 1559 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1560 actlen, status)); 1561 xfer->actlen = actlen; 1562 if (status != 0) { 1563 #ifdef UHCI_DEBUG 1564 char sbuf[128]; 1565 1566 snprintb(sbuf, sizeof(sbuf), 1567 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1568 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1569 1570 DPRINTFN((status == UHCI_TD_STALLED)*10, 1571 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1572 "status 0x%s\n", 1573 xfer->pipe->device->address, 1574 xfer->pipe->endpoint->edesc->bEndpointAddress, 1575 sbuf)); 1576 #endif 1577 1578 if (status == UHCI_TD_STALLED) 1579 xfer->status = USBD_STALLED; 1580 else 1581 xfer->status = USBD_IOERROR; /* more info XXX */ 1582 } else { 1583 xfer->status = USBD_NORMAL_COMPLETION; 1584 } 1585 1586 end: 1587 usb_transfer_complete(xfer); 1588 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1589 } 1590 1591 /* 1592 * Called when a request does not complete. 1593 */ 1594 void 1595 uhci_timeout(void *addr) 1596 { 1597 uhci_intr_info_t *ii = addr; 1598 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1599 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1600 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1601 1602 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1603 1604 if (sc->sc_dying) { 1605 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1606 return; 1607 } 1608 1609 /* Execute the abort in a process context. */ 1610 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer); 1611 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1612 USB_TASKQ_HC); 1613 } 1614 1615 void 1616 uhci_timeout_task(void *addr) 1617 { 1618 usbd_xfer_handle xfer = addr; 1619 int s; 1620 1621 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1622 1623 s = splusb(); 1624 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1625 splx(s); 1626 } 1627 1628 /* 1629 * Wait here until controller claims to have an interrupt. 1630 * Then call uhci_intr and return. Use timeout to avoid waiting 1631 * too long. 1632 * Only used during boot when interrupts are not enabled yet. 1633 */ 1634 void 1635 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1636 { 1637 int timo = xfer->timeout; 1638 uhci_intr_info_t *ii; 1639 1640 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1641 1642 xfer->status = USBD_IN_PROGRESS; 1643 for (; timo >= 0; timo--) { 1644 usb_delay_ms(&sc->sc_bus, 1); 1645 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1646 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1647 uhci_intr1(sc); 1648 if (xfer->status != USBD_IN_PROGRESS) 1649 return; 1650 } 1651 } 1652 1653 /* Timeout */ 1654 DPRINTF(("uhci_waitintr: timeout\n")); 1655 for (ii = LIST_FIRST(&sc->sc_intrhead); 1656 ii != NULL && ii->xfer != xfer; 1657 ii = LIST_NEXT(ii, list)) 1658 ; 1659 #ifdef DIAGNOSTIC 1660 if (ii == NULL) 1661 panic("uhci_waitintr: lost intr_info"); 1662 #endif 1663 uhci_idone(ii); 1664 } 1665 1666 void 1667 uhci_poll(struct usbd_bus *bus) 1668 { 1669 uhci_softc_t *sc = bus->hci_private; 1670 1671 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) 1672 uhci_intr1(sc); 1673 } 1674 1675 void 1676 uhci_reset(uhci_softc_t *sc) 1677 { 1678 int n; 1679 1680 UHCICMD(sc, UHCI_CMD_HCRESET); 1681 /* The reset bit goes low when the controller is done. */ 1682 for (n = 0; n < UHCI_RESET_TIMEOUT && 1683 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1684 usb_delay_ms(&sc->sc_bus, 1); 1685 if (n >= UHCI_RESET_TIMEOUT) 1686 printf("%s: controller did not reset\n", 1687 device_xname(sc->sc_dev)); 1688 } 1689 1690 usbd_status 1691 uhci_run(uhci_softc_t *sc, int run) 1692 { 1693 int s, n, running; 1694 u_int16_t cmd; 1695 1696 run = run != 0; 1697 s = splhardusb(); 1698 DPRINTF(("uhci_run: setting run=%d\n", run)); 1699 cmd = UREAD2(sc, UHCI_CMD); 1700 if (run) 1701 cmd |= UHCI_CMD_RS; 1702 else 1703 cmd &= ~UHCI_CMD_RS; 1704 UHCICMD(sc, cmd); 1705 for(n = 0; n < 10; n++) { 1706 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1707 /* return when we've entered the state we want */ 1708 if (run == running) { 1709 splx(s); 1710 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1711 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1712 return (USBD_NORMAL_COMPLETION); 1713 } 1714 usb_delay_ms(&sc->sc_bus, 1); 1715 } 1716 splx(s); 1717 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1718 run ? "start" : "stop"); 1719 return (USBD_IOERROR); 1720 } 1721 1722 /* 1723 * Memory management routines. 1724 * uhci_alloc_std allocates TDs 1725 * uhci_alloc_sqh allocates QHs 1726 * These two routines do their own free list management, 1727 * partly for speed, partly because allocating DMAable memory 1728 * has page size granularaity so much memory would be wasted if 1729 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1730 */ 1731 1732 uhci_soft_td_t * 1733 uhci_alloc_std(uhci_softc_t *sc) 1734 { 1735 uhci_soft_td_t *std; 1736 usbd_status err; 1737 int i, offs; 1738 usb_dma_t dma; 1739 1740 if (sc->sc_freetds == NULL) { 1741 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1742 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1743 UHCI_TD_ALIGN, &dma); 1744 if (err) 1745 return (0); 1746 for(i = 0; i < UHCI_STD_CHUNK; i++) { 1747 offs = i * UHCI_STD_SIZE; 1748 std = KERNADDR(&dma, offs); 1749 std->physaddr = DMAADDR(&dma, offs); 1750 std->dma = dma; 1751 std->offs = offs; 1752 std->link.std = sc->sc_freetds; 1753 sc->sc_freetds = std; 1754 } 1755 } 1756 std = sc->sc_freetds; 1757 sc->sc_freetds = std->link.std; 1758 memset(&std->td, 0, sizeof(uhci_td_t)); 1759 return std; 1760 } 1761 1762 void 1763 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1764 { 1765 #ifdef DIAGNOSTIC 1766 #define TD_IS_FREE 0x12345678 1767 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1768 printf("uhci_free_std: freeing free TD %p\n", std); 1769 return; 1770 } 1771 std->td.td_token = htole32(TD_IS_FREE); 1772 #endif 1773 std->link.std = sc->sc_freetds; 1774 sc->sc_freetds = std; 1775 } 1776 1777 uhci_soft_qh_t * 1778 uhci_alloc_sqh(uhci_softc_t *sc) 1779 { 1780 uhci_soft_qh_t *sqh; 1781 usbd_status err; 1782 int i, offs; 1783 usb_dma_t dma; 1784 1785 if (sc->sc_freeqhs == NULL) { 1786 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1787 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1788 UHCI_QH_ALIGN, &dma); 1789 if (err) 1790 return (0); 1791 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1792 offs = i * UHCI_SQH_SIZE; 1793 sqh = KERNADDR(&dma, offs); 1794 sqh->physaddr = DMAADDR(&dma, offs); 1795 sqh->dma = dma; 1796 sqh->offs = offs; 1797 sqh->hlink = sc->sc_freeqhs; 1798 sc->sc_freeqhs = sqh; 1799 } 1800 } 1801 sqh = sc->sc_freeqhs; 1802 sc->sc_freeqhs = sqh->hlink; 1803 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1804 return (sqh); 1805 } 1806 1807 void 1808 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1809 { 1810 sqh->hlink = sc->sc_freeqhs; 1811 sc->sc_freeqhs = sqh; 1812 } 1813 1814 void 1815 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1816 uhci_soft_td_t *stdend) 1817 { 1818 uhci_soft_td_t *p; 1819 1820 /* 1821 * to avoid race condition with the controller which may be looking 1822 * at this chain, we need to first invalidate all links, and 1823 * then wait for the controller to move to another queue 1824 */ 1825 for (p = std; p != stdend; p = p->link.std) { 1826 usb_syncmem(&p->dma, 1827 p->offs + offsetof(uhci_td_t, td_link), 1828 sizeof(p->td.td_link), 1829 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1830 if ((p->td.td_link & UHCI_PTR_T) == 0) { 1831 p->td.td_link = UHCI_PTR_T; 1832 usb_syncmem(&p->dma, 1833 p->offs + offsetof(uhci_td_t, td_link), 1834 sizeof(p->td.td_link), 1835 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1836 } 1837 } 1838 delay(UHCI_QH_REMOVE_DELAY); 1839 1840 for (; std != stdend; std = p) { 1841 p = std->link.std; 1842 uhci_free_std(sc, std); 1843 } 1844 } 1845 1846 usbd_status 1847 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1848 int rd, u_int16_t flags, usb_dma_t *dma, 1849 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1850 { 1851 uhci_soft_td_t *p, *lastp; 1852 uhci_physaddr_t lastlink; 1853 int i, ntd, l, tog, maxp; 1854 u_int32_t status; 1855 int addr = upipe->pipe.device->address; 1856 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1857 1858 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1859 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1860 upipe->pipe.device->speed, flags)); 1861 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1862 if (maxp == 0) { 1863 printf("uhci_alloc_std_chain: maxp=0\n"); 1864 return (USBD_INVAL); 1865 } 1866 ntd = (len + maxp - 1) / maxp; 1867 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1868 ntd++; 1869 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1870 if (ntd == 0) { 1871 *sp = *ep = 0; 1872 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1873 return (USBD_NORMAL_COMPLETION); 1874 } 1875 tog = upipe->nexttoggle; 1876 if (ntd % 2 == 0) 1877 tog ^= 1; 1878 upipe->nexttoggle = tog ^ 1; 1879 lastp = NULL; 1880 lastlink = UHCI_PTR_T; 1881 ntd--; 1882 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1883 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1884 status |= UHCI_TD_LS; 1885 if (flags & USBD_SHORT_XFER_OK) 1886 status |= UHCI_TD_SPD; 1887 usb_syncmem(dma, 0, len, 1888 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1889 for (i = ntd; i >= 0; i--) { 1890 p = uhci_alloc_std(sc); 1891 if (p == NULL) { 1892 KASSERT(lastp != NULL); 1893 uhci_free_std_chain(sc, lastp, NULL); 1894 return (USBD_NOMEM); 1895 } 1896 p->link.std = lastp; 1897 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1898 lastp = p; 1899 lastlink = p->physaddr; 1900 p->td.td_status = htole32(status); 1901 if (i == ntd) { 1902 /* last TD */ 1903 l = len % maxp; 1904 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1905 l = maxp; 1906 *ep = p; 1907 } else 1908 l = maxp; 1909 p->td.td_token = 1910 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1911 UHCI_TD_OUT(l, endpt, addr, tog)); 1912 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1913 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1914 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1915 tog ^= 1; 1916 } 1917 *sp = lastp; 1918 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1919 upipe->nexttoggle)); 1920 return (USBD_NORMAL_COMPLETION); 1921 } 1922 1923 void 1924 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1925 { 1926 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1927 upipe->nexttoggle = 0; 1928 } 1929 1930 void 1931 uhci_noop(usbd_pipe_handle pipe) 1932 { 1933 } 1934 1935 usbd_status 1936 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1937 { 1938 usbd_status err; 1939 1940 /* Insert last in queue. */ 1941 err = usb_insert_transfer(xfer); 1942 if (err) 1943 return (err); 1944 1945 /* 1946 * Pipe isn't running (otherwise err would be USBD_INPROG), 1947 * so start it first. 1948 */ 1949 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1950 } 1951 1952 usbd_status 1953 uhci_device_bulk_start(usbd_xfer_handle xfer) 1954 { 1955 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1956 usbd_device_handle dev = upipe->pipe.device; 1957 uhci_softc_t *sc = dev->bus->hci_private; 1958 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 1959 uhci_soft_td_t *data, *dataend; 1960 uhci_soft_qh_t *sqh; 1961 usbd_status err; 1962 int len, isread, endpt; 1963 int s; 1964 1965 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 1966 xfer, xfer->length, xfer->flags, ii)); 1967 1968 if (sc->sc_dying) 1969 return (USBD_IOERROR); 1970 1971 #ifdef DIAGNOSTIC 1972 if (xfer->rqflags & URQ_REQUEST) 1973 panic("uhci_device_bulk_transfer: a request"); 1974 #endif 1975 1976 len = xfer->length; 1977 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1978 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 1979 sqh = upipe->u.bulk.sqh; 1980 1981 upipe->u.bulk.isread = isread; 1982 upipe->u.bulk.length = len; 1983 1984 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 1985 &xfer->dmabuf, &data, &dataend); 1986 if (err) 1987 return (err); 1988 dataend->td.td_status |= htole32(UHCI_TD_IOC); 1989 usb_syncmem(&dataend->dma, 1990 dataend->offs + offsetof(uhci_td_t, td_status), 1991 sizeof(dataend->td.td_status), 1992 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1993 1994 1995 #ifdef UHCI_DEBUG 1996 if (uhcidebug > 8) { 1997 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 1998 uhci_dump_tds(data); 1999 } 2000 #endif 2001 2002 /* Set up interrupt info. */ 2003 ii->xfer = xfer; 2004 ii->stdstart = data; 2005 ii->stdend = dataend; 2006 #ifdef DIAGNOSTIC 2007 if (!ii->isdone) { 2008 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2009 } 2010 ii->isdone = 0; 2011 #endif 2012 2013 sqh->elink = data; 2014 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2015 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2016 2017 s = splusb(); 2018 uhci_add_bulk(sc, sqh); 2019 uhci_add_intr_info(sc, ii); 2020 2021 if (xfer->timeout && !sc->sc_bus.use_polling) { 2022 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2023 uhci_timeout, ii); 2024 } 2025 xfer->status = USBD_IN_PROGRESS; 2026 splx(s); 2027 2028 #ifdef UHCI_DEBUG 2029 if (uhcidebug > 10) { 2030 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2031 uhci_dump_tds(data); 2032 } 2033 #endif 2034 2035 if (sc->sc_bus.use_polling) 2036 uhci_waitintr(sc, xfer); 2037 2038 return (USBD_IN_PROGRESS); 2039 } 2040 2041 /* Abort a device bulk request. */ 2042 void 2043 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2044 { 2045 DPRINTF(("uhci_device_bulk_abort:\n")); 2046 uhci_abort_xfer(xfer, USBD_CANCELLED); 2047 } 2048 2049 /* 2050 * Abort a device request. 2051 * If this routine is called at splusb() it guarantees that the request 2052 * will be removed from the hardware scheduling and that the callback 2053 * for it will be called with USBD_CANCELLED status. 2054 * It's impossible to guarantee that the requested transfer will not 2055 * have happened since the hardware runs concurrently. 2056 * If the transaction has already happened we rely on the ordinary 2057 * interrupt processing to process it. 2058 */ 2059 void 2060 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2061 { 2062 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2063 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2064 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2065 uhci_soft_td_t *std; 2066 int s; 2067 int wake; 2068 2069 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2070 2071 if (sc->sc_dying) { 2072 /* If we're dying, just do the software part. */ 2073 s = splusb(); 2074 xfer->status = status; /* make software ignore it */ 2075 callout_stop(&xfer->timeout_handle); 2076 usb_transfer_complete(xfer); 2077 splx(s); 2078 return; 2079 } 2080 2081 if (xfer->device->bus->intr_context || !curproc) 2082 panic("uhci_abort_xfer: not in process context"); 2083 2084 /* 2085 * If an abort is already in progress then just wait for it to 2086 * complete and return. 2087 */ 2088 if (xfer->hcflags & UXFER_ABORTING) { 2089 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2090 #ifdef DIAGNOSTIC 2091 if (status == USBD_TIMEOUT) 2092 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2093 #endif 2094 /* Override the status which might be USBD_TIMEOUT. */ 2095 xfer->status = status; 2096 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2097 xfer->hcflags |= UXFER_ABORTWAIT; 2098 while (xfer->hcflags & UXFER_ABORTING) 2099 tsleep(&xfer->hcflags, PZERO, "uhciaw", 0); 2100 return; 2101 } 2102 xfer->hcflags |= UXFER_ABORTING; 2103 2104 /* 2105 * Step 1: Make interrupt routine and hardware ignore xfer. 2106 */ 2107 s = splusb(); 2108 xfer->status = status; /* make software ignore it */ 2109 callout_stop(&xfer->timeout_handle); 2110 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2111 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2112 usb_syncmem(&std->dma, 2113 std->offs + offsetof(uhci_td_t, td_status), 2114 sizeof(std->td.td_status), 2115 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2116 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2117 usb_syncmem(&std->dma, 2118 std->offs + offsetof(uhci_td_t, td_status), 2119 sizeof(std->td.td_status), 2120 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2121 } 2122 splx(s); 2123 2124 /* 2125 * Step 2: Wait until we know hardware has finished any possible 2126 * use of the xfer. Also make sure the soft interrupt routine 2127 * has run. 2128 */ 2129 usb_delay_ms(upipe->pipe.device->bus, 2); /* Hardware finishes in 1ms */ 2130 s = splusb(); 2131 sc->sc_softwake = 1; 2132 usb_schedsoftintr(&sc->sc_bus); 2133 DPRINTFN(1,("uhci_abort_xfer: tsleep\n")); 2134 tsleep(&sc->sc_softwake, PZERO, "uhciab", 0); 2135 splx(s); 2136 2137 /* 2138 * Step 3: Execute callback. 2139 */ 2140 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2141 s = splusb(); 2142 #ifdef DIAGNOSTIC 2143 ii->isdone = 1; 2144 #endif 2145 wake = xfer->hcflags & UXFER_ABORTWAIT; 2146 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2147 usb_transfer_complete(xfer); 2148 if (wake) 2149 wakeup(&xfer->hcflags); 2150 splx(s); 2151 } 2152 2153 /* Close a device bulk pipe. */ 2154 void 2155 uhci_device_bulk_close(usbd_pipe_handle pipe) 2156 { 2157 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2158 usbd_device_handle dev = upipe->pipe.device; 2159 uhci_softc_t *sc = dev->bus->hci_private; 2160 2161 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2162 2163 pipe->endpoint->datatoggle = upipe->nexttoggle; 2164 } 2165 2166 usbd_status 2167 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2168 { 2169 usbd_status err; 2170 2171 /* Insert last in queue. */ 2172 err = usb_insert_transfer(xfer); 2173 if (err) 2174 return (err); 2175 2176 /* 2177 * Pipe isn't running (otherwise err would be USBD_INPROG), 2178 * so start it first. 2179 */ 2180 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2181 } 2182 2183 usbd_status 2184 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2185 { 2186 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2187 usbd_status err; 2188 2189 if (sc->sc_dying) 2190 return (USBD_IOERROR); 2191 2192 #ifdef DIAGNOSTIC 2193 if (!(xfer->rqflags & URQ_REQUEST)) 2194 panic("uhci_device_ctrl_transfer: not a request"); 2195 #endif 2196 2197 err = uhci_device_request(xfer); 2198 if (err) 2199 return (err); 2200 2201 if (sc->sc_bus.use_polling) 2202 uhci_waitintr(sc, xfer); 2203 return (USBD_IN_PROGRESS); 2204 } 2205 2206 usbd_status 2207 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2208 { 2209 usbd_status err; 2210 2211 /* Insert last in queue. */ 2212 err = usb_insert_transfer(xfer); 2213 if (err) 2214 return (err); 2215 2216 /* 2217 * Pipe isn't running (otherwise err would be USBD_INPROG), 2218 * so start it first. 2219 */ 2220 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2221 } 2222 2223 usbd_status 2224 uhci_device_intr_start(usbd_xfer_handle xfer) 2225 { 2226 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2227 usbd_device_handle dev = upipe->pipe.device; 2228 uhci_softc_t *sc = dev->bus->hci_private; 2229 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2230 uhci_soft_td_t *data, *dataend; 2231 uhci_soft_qh_t *sqh; 2232 usbd_status err; 2233 int isread, endpt; 2234 int i, s; 2235 2236 if (sc->sc_dying) 2237 return (USBD_IOERROR); 2238 2239 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2240 xfer, xfer->length, xfer->flags)); 2241 2242 #ifdef DIAGNOSTIC 2243 if (xfer->rqflags & URQ_REQUEST) 2244 panic("uhci_device_intr_transfer: a request"); 2245 #endif 2246 2247 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2248 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2249 2250 upipe->u.intr.isread = isread; 2251 2252 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2253 xfer->flags, &xfer->dmabuf, &data, 2254 &dataend); 2255 if (err) 2256 return (err); 2257 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2258 usb_syncmem(&dataend->dma, 2259 dataend->offs + offsetof(uhci_td_t, td_status), 2260 sizeof(dataend->td.td_status), 2261 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2262 2263 #ifdef UHCI_DEBUG 2264 if (uhcidebug > 10) { 2265 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2266 uhci_dump_tds(data); 2267 uhci_dump_qh(upipe->u.intr.qhs[0]); 2268 } 2269 #endif 2270 2271 s = splusb(); 2272 /* Set up interrupt info. */ 2273 ii->xfer = xfer; 2274 ii->stdstart = data; 2275 ii->stdend = dataend; 2276 #ifdef DIAGNOSTIC 2277 if (!ii->isdone) { 2278 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2279 } 2280 ii->isdone = 0; 2281 #endif 2282 2283 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2284 upipe->u.intr.qhs[0])); 2285 for (i = 0; i < upipe->u.intr.npoll; i++) { 2286 sqh = upipe->u.intr.qhs[i]; 2287 sqh->elink = data; 2288 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2289 usb_syncmem(&sqh->dma, 2290 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2291 sizeof(sqh->qh.qh_elink), 2292 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2293 } 2294 uhci_add_intr_info(sc, ii); 2295 xfer->status = USBD_IN_PROGRESS; 2296 splx(s); 2297 2298 #ifdef UHCI_DEBUG 2299 if (uhcidebug > 10) { 2300 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2301 uhci_dump_tds(data); 2302 uhci_dump_qh(upipe->u.intr.qhs[0]); 2303 } 2304 #endif 2305 2306 return (USBD_IN_PROGRESS); 2307 } 2308 2309 /* Abort a device control request. */ 2310 void 2311 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2312 { 2313 DPRINTF(("uhci_device_ctrl_abort:\n")); 2314 uhci_abort_xfer(xfer, USBD_CANCELLED); 2315 } 2316 2317 /* Close a device control pipe. */ 2318 void 2319 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2320 { 2321 } 2322 2323 /* Abort a device interrupt request. */ 2324 void 2325 uhci_device_intr_abort(usbd_xfer_handle xfer) 2326 { 2327 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2328 if (xfer->pipe->intrxfer == xfer) { 2329 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2330 xfer->pipe->intrxfer = NULL; 2331 } 2332 uhci_abort_xfer(xfer, USBD_CANCELLED); 2333 } 2334 2335 /* Close a device interrupt pipe. */ 2336 void 2337 uhci_device_intr_close(usbd_pipe_handle pipe) 2338 { 2339 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2340 uhci_softc_t *sc = pipe->device->bus->hci_private; 2341 int i, npoll; 2342 int s; 2343 2344 /* Unlink descriptors from controller data structures. */ 2345 npoll = upipe->u.intr.npoll; 2346 s = splusb(); 2347 for (i = 0; i < npoll; i++) 2348 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2349 splx(s); 2350 2351 /* 2352 * We now have to wait for any activity on the physical 2353 * descriptors to stop. 2354 */ 2355 usb_delay_ms(&sc->sc_bus, 2); 2356 2357 for(i = 0; i < npoll; i++) 2358 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2359 free(upipe->u.intr.qhs, M_USBHC); 2360 2361 /* XXX free other resources */ 2362 } 2363 2364 usbd_status 2365 uhci_device_request(usbd_xfer_handle xfer) 2366 { 2367 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2368 usb_device_request_t *req = &xfer->request; 2369 usbd_device_handle dev = upipe->pipe.device; 2370 uhci_softc_t *sc = dev->bus->hci_private; 2371 int addr = dev->address; 2372 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2373 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2374 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2375 uhci_soft_qh_t *sqh; 2376 int len; 2377 u_int32_t ls; 2378 usbd_status err; 2379 int isread; 2380 int s; 2381 2382 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2383 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2384 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2385 UGETW(req->wIndex), UGETW(req->wLength), 2386 addr, endpt)); 2387 2388 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2389 isread = req->bmRequestType & UT_READ; 2390 len = UGETW(req->wLength); 2391 2392 setup = upipe->u.ctl.setup; 2393 stat = upipe->u.ctl.stat; 2394 sqh = upipe->u.ctl.sqh; 2395 2396 /* Set up data transaction */ 2397 if (len != 0) { 2398 upipe->nexttoggle = 1; 2399 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2400 &xfer->dmabuf, &data, &dataend); 2401 if (err) 2402 return (err); 2403 next = data; 2404 dataend->link.std = stat; 2405 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2406 usb_syncmem(&dataend->dma, 2407 dataend->offs + offsetof(uhci_td_t, td_link), 2408 sizeof(dataend->td.td_link), 2409 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2410 } else { 2411 next = stat; 2412 } 2413 upipe->u.ctl.length = len; 2414 2415 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2416 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2417 2418 setup->link.std = next; 2419 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2420 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2421 UHCI_TD_ACTIVE); 2422 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2423 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2424 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2425 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2426 2427 stat->link.std = NULL; 2428 stat->td.td_link = htole32(UHCI_PTR_T); 2429 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2430 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2431 stat->td.td_token = 2432 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2433 UHCI_TD_IN (0, endpt, addr, 1)); 2434 stat->td.td_buffer = htole32(0); 2435 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2436 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2437 2438 #ifdef UHCI_DEBUG 2439 if (uhcidebug > 10) { 2440 DPRINTF(("uhci_device_request: before transfer\n")); 2441 uhci_dump_tds(setup); 2442 } 2443 #endif 2444 2445 /* Set up interrupt info. */ 2446 ii->xfer = xfer; 2447 ii->stdstart = setup; 2448 ii->stdend = stat; 2449 #ifdef DIAGNOSTIC 2450 if (!ii->isdone) { 2451 printf("uhci_device_request: not done, ii=%p\n", ii); 2452 } 2453 ii->isdone = 0; 2454 #endif 2455 2456 sqh->elink = setup; 2457 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2458 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2459 2460 s = splusb(); 2461 if (dev->speed == USB_SPEED_LOW) 2462 uhci_add_ls_ctrl(sc, sqh); 2463 else 2464 uhci_add_hs_ctrl(sc, sqh); 2465 uhci_add_intr_info(sc, ii); 2466 #ifdef UHCI_DEBUG 2467 if (uhcidebug > 12) { 2468 uhci_soft_td_t *std; 2469 uhci_soft_qh_t *xqh; 2470 uhci_soft_qh_t *sxqh; 2471 int maxqh = 0; 2472 uhci_physaddr_t link; 2473 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2474 for (std = sc->sc_vframes[0].htd, link = 0; 2475 (link & UHCI_PTR_QH) == 0; 2476 std = std->link.std) { 2477 link = le32toh(std->td.td_link); 2478 uhci_dump_td(std); 2479 } 2480 sxqh = (uhci_soft_qh_t *)std; 2481 uhci_dump_qh(sxqh); 2482 for (xqh = sxqh; 2483 xqh != NULL; 2484 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2485 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2486 uhci_dump_qh(xqh); 2487 } 2488 DPRINTF(("Enqueued QH:\n")); 2489 uhci_dump_qh(sqh); 2490 uhci_dump_tds(sqh->elink); 2491 } 2492 #endif 2493 if (xfer->timeout && !sc->sc_bus.use_polling) { 2494 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2495 uhci_timeout, ii); 2496 } 2497 xfer->status = USBD_IN_PROGRESS; 2498 splx(s); 2499 2500 return (USBD_NORMAL_COMPLETION); 2501 } 2502 2503 usbd_status 2504 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2505 { 2506 usbd_status err; 2507 2508 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2509 2510 /* Put it on our queue, */ 2511 err = usb_insert_transfer(xfer); 2512 2513 /* bail out on error, */ 2514 if (err && err != USBD_IN_PROGRESS) 2515 return (err); 2516 2517 /* XXX should check inuse here */ 2518 2519 /* insert into schedule, */ 2520 uhci_device_isoc_enter(xfer); 2521 2522 /* and start if the pipe wasn't running */ 2523 if (!err) 2524 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2525 2526 return (err); 2527 } 2528 2529 void 2530 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2531 { 2532 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2533 usbd_device_handle dev = upipe->pipe.device; 2534 uhci_softc_t *sc = dev->bus->hci_private; 2535 struct iso *iso = &upipe->u.iso; 2536 uhci_soft_td_t *std; 2537 u_int32_t buf, len, status, offs; 2538 int s, i, next, nframes; 2539 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2540 2541 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2542 "nframes=%d\n", 2543 iso->inuse, iso->next, xfer, xfer->nframes)); 2544 2545 if (sc->sc_dying) 2546 return; 2547 2548 if (xfer->status == USBD_IN_PROGRESS) { 2549 /* This request has already been entered into the frame list */ 2550 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2551 /* XXX */ 2552 } 2553 2554 #ifdef DIAGNOSTIC 2555 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2556 printf("uhci_device_isoc_enter: overflow!\n"); 2557 #endif 2558 2559 next = iso->next; 2560 if (next == -1) { 2561 /* Not in use yet, schedule it a few frames ahead. */ 2562 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2563 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2564 } 2565 2566 xfer->status = USBD_IN_PROGRESS; 2567 UXFER(xfer)->curframe = next; 2568 2569 buf = DMAADDR(&xfer->dmabuf, 0); 2570 offs = 0; 2571 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2572 UHCI_TD_ACTIVE | 2573 UHCI_TD_IOS); 2574 nframes = xfer->nframes; 2575 s = splusb(); 2576 for (i = 0; i < nframes; i++) { 2577 std = iso->stds[next]; 2578 if (++next >= UHCI_VFRAMELIST_COUNT) 2579 next = 0; 2580 len = xfer->frlengths[i]; 2581 std->td.td_buffer = htole32(buf); 2582 usb_syncmem(&xfer->dmabuf, offs, len, 2583 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2584 if (i == nframes - 1) 2585 status |= UHCI_TD_IOC; 2586 std->td.td_status = htole32(status); 2587 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2588 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2589 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2590 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2591 #ifdef UHCI_DEBUG 2592 if (uhcidebug > 5) { 2593 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2594 uhci_dump_td(std); 2595 } 2596 #endif 2597 buf += len; 2598 offs += len; 2599 } 2600 iso->next = next; 2601 iso->inuse += xfer->nframes; 2602 2603 splx(s); 2604 } 2605 2606 usbd_status 2607 uhci_device_isoc_start(usbd_xfer_handle xfer) 2608 { 2609 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2610 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2611 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2612 uhci_soft_td_t *end; 2613 int s, i; 2614 2615 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2616 2617 if (sc->sc_dying) 2618 return (USBD_IOERROR); 2619 2620 #ifdef DIAGNOSTIC 2621 if (xfer->status != USBD_IN_PROGRESS) 2622 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2623 #endif 2624 2625 /* Find the last TD */ 2626 i = UXFER(xfer)->curframe + xfer->nframes; 2627 if (i >= UHCI_VFRAMELIST_COUNT) 2628 i -= UHCI_VFRAMELIST_COUNT; 2629 end = upipe->u.iso.stds[i]; 2630 2631 #ifdef DIAGNOSTIC 2632 if (end == NULL) { 2633 printf("uhci_device_isoc_start: end == NULL\n"); 2634 return (USBD_INVAL); 2635 } 2636 #endif 2637 2638 s = splusb(); 2639 2640 /* Set up interrupt info. */ 2641 ii->xfer = xfer; 2642 ii->stdstart = end; 2643 ii->stdend = end; 2644 #ifdef DIAGNOSTIC 2645 if (!ii->isdone) 2646 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2647 ii->isdone = 0; 2648 #endif 2649 uhci_add_intr_info(sc, ii); 2650 2651 splx(s); 2652 2653 return (USBD_IN_PROGRESS); 2654 } 2655 2656 void 2657 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2658 { 2659 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2660 uhci_soft_td_t **stds = upipe->u.iso.stds; 2661 uhci_soft_td_t *std; 2662 int i, n, s, nframes, maxlen, len; 2663 2664 s = splusb(); 2665 2666 /* Transfer is already done. */ 2667 if (xfer->status != USBD_NOT_STARTED && 2668 xfer->status != USBD_IN_PROGRESS) { 2669 splx(s); 2670 return; 2671 } 2672 2673 /* Give xfer the requested abort code. */ 2674 xfer->status = USBD_CANCELLED; 2675 2676 /* make hardware ignore it, */ 2677 nframes = xfer->nframes; 2678 n = UXFER(xfer)->curframe; 2679 maxlen = 0; 2680 for (i = 0; i < nframes; i++) { 2681 std = stds[n]; 2682 usb_syncmem(&std->dma, 2683 std->offs + offsetof(uhci_td_t, td_status), 2684 sizeof(std->td.td_status), 2685 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2686 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2687 usb_syncmem(&std->dma, 2688 std->offs + offsetof(uhci_td_t, td_status), 2689 sizeof(std->td.td_status), 2690 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2691 usb_syncmem(&std->dma, 2692 std->offs + offsetof(uhci_td_t, td_token), 2693 sizeof(std->td.td_token), 2694 BUS_DMASYNC_POSTWRITE); 2695 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2696 if (len > maxlen) 2697 maxlen = len; 2698 if (++n >= UHCI_VFRAMELIST_COUNT) 2699 n = 0; 2700 } 2701 2702 /* and wait until we are sure the hardware has finished. */ 2703 delay(maxlen); 2704 2705 #ifdef DIAGNOSTIC 2706 UXFER(xfer)->iinfo.isdone = 1; 2707 #endif 2708 /* Run callback and remove from interrupt list. */ 2709 usb_transfer_complete(xfer); 2710 2711 splx(s); 2712 } 2713 2714 void 2715 uhci_device_isoc_close(usbd_pipe_handle pipe) 2716 { 2717 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2718 usbd_device_handle dev = upipe->pipe.device; 2719 uhci_softc_t *sc = dev->bus->hci_private; 2720 uhci_soft_td_t *std, *vstd; 2721 struct iso *iso; 2722 int i, s; 2723 2724 /* 2725 * Make sure all TDs are marked as inactive. 2726 * Wait for completion. 2727 * Unschedule. 2728 * Deallocate. 2729 */ 2730 iso = &upipe->u.iso; 2731 2732 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2733 std = iso->stds[i]; 2734 usb_syncmem(&std->dma, 2735 std->offs + offsetof(uhci_td_t, td_status), 2736 sizeof(std->td.td_status), 2737 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2738 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2739 usb_syncmem(&std->dma, 2740 std->offs + offsetof(uhci_td_t, td_status), 2741 sizeof(std->td.td_status), 2742 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2743 } 2744 usb_delay_ms(&sc->sc_bus, 2); /* wait for completion */ 2745 2746 s = splusb(); 2747 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2748 std = iso->stds[i]; 2749 for (vstd = sc->sc_vframes[i].htd; 2750 vstd != NULL && vstd->link.std != std; 2751 vstd = vstd->link.std) 2752 ; 2753 if (vstd == NULL) { 2754 /*panic*/ 2755 printf("uhci_device_isoc_close: %p not found\n", std); 2756 splx(s); 2757 return; 2758 } 2759 vstd->link = std->link; 2760 usb_syncmem(&std->dma, 2761 std->offs + offsetof(uhci_td_t, td_link), 2762 sizeof(std->td.td_link), 2763 BUS_DMASYNC_POSTWRITE); 2764 vstd->td.td_link = std->td.td_link; 2765 usb_syncmem(&vstd->dma, 2766 vstd->offs + offsetof(uhci_td_t, td_link), 2767 sizeof(vstd->td.td_link), 2768 BUS_DMASYNC_PREWRITE); 2769 uhci_free_std(sc, std); 2770 } 2771 splx(s); 2772 2773 free(iso->stds, M_USBHC); 2774 } 2775 2776 usbd_status 2777 uhci_setup_isoc(usbd_pipe_handle pipe) 2778 { 2779 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2780 usbd_device_handle dev = upipe->pipe.device; 2781 uhci_softc_t *sc = dev->bus->hci_private; 2782 int addr = upipe->pipe.device->address; 2783 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2784 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2785 uhci_soft_td_t *std, *vstd; 2786 u_int32_t token; 2787 struct iso *iso; 2788 int i, s; 2789 2790 iso = &upipe->u.iso; 2791 iso->stds = malloc(UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *), 2792 M_USBHC, M_WAITOK); 2793 2794 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2795 UHCI_TD_OUT(0, endpt, addr, 0); 2796 2797 /* Allocate the TDs and mark as inactive; */ 2798 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2799 std = uhci_alloc_std(sc); 2800 if (std == 0) 2801 goto bad; 2802 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2803 std->td.td_token = htole32(token); 2804 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2805 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2806 iso->stds[i] = std; 2807 } 2808 2809 /* Insert TDs into schedule. */ 2810 s = splusb(); 2811 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2812 std = iso->stds[i]; 2813 vstd = sc->sc_vframes[i].htd; 2814 usb_syncmem(&vstd->dma, 2815 vstd->offs + offsetof(uhci_td_t, td_link), 2816 sizeof(vstd->td.td_link), 2817 BUS_DMASYNC_POSTWRITE); 2818 std->link = vstd->link; 2819 std->td.td_link = vstd->td.td_link; 2820 usb_syncmem(&std->dma, 2821 std->offs + offsetof(uhci_td_t, td_link), 2822 sizeof(std->td.td_link), 2823 BUS_DMASYNC_PREWRITE); 2824 vstd->link.std = std; 2825 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2826 usb_syncmem(&vstd->dma, 2827 vstd->offs + offsetof(uhci_td_t, td_link), 2828 sizeof(vstd->td.td_link), 2829 BUS_DMASYNC_PREWRITE); 2830 } 2831 splx(s); 2832 2833 iso->next = -1; 2834 iso->inuse = 0; 2835 2836 return (USBD_NORMAL_COMPLETION); 2837 2838 bad: 2839 while (--i >= 0) 2840 uhci_free_std(sc, iso->stds[i]); 2841 free(iso->stds, M_USBHC); 2842 return (USBD_NOMEM); 2843 } 2844 2845 void 2846 uhci_device_isoc_done(usbd_xfer_handle xfer) 2847 { 2848 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2849 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2850 int i, offs; 2851 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2852 2853 2854 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2855 xfer->actlen, xfer->busy_free)); 2856 2857 if (ii->xfer != xfer) 2858 /* Not on interrupt list, ignore it. */ 2859 return; 2860 2861 if (!uhci_active_intr_info(ii)) 2862 return; 2863 2864 #ifdef DIAGNOSTIC 2865 if (ii->stdend == NULL) { 2866 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2867 #ifdef UHCI_DEBUG 2868 uhci_dump_ii(ii); 2869 #endif 2870 return; 2871 } 2872 #endif 2873 2874 /* Turn off the interrupt since it is active even if the TD is not. */ 2875 usb_syncmem(&ii->stdend->dma, 2876 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2877 sizeof(ii->stdend->td.td_status), 2878 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2879 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2880 usb_syncmem(&ii->stdend->dma, 2881 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2882 sizeof(ii->stdend->td.td_status), 2883 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2884 2885 uhci_del_intr_info(ii); /* remove from active list */ 2886 2887 offs = 0; 2888 for (i = 0; i < xfer->nframes; i++) { 2889 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2890 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2891 offs += xfer->frlengths[i]; 2892 } 2893 } 2894 2895 void 2896 uhci_device_intr_done(usbd_xfer_handle xfer) 2897 { 2898 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2899 uhci_softc_t *sc = ii->sc; 2900 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2901 uhci_soft_qh_t *sqh; 2902 int i, npoll, isread; 2903 2904 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 2905 2906 npoll = upipe->u.intr.npoll; 2907 for(i = 0; i < npoll; i++) { 2908 sqh = upipe->u.intr.qhs[i]; 2909 sqh->elink = NULL; 2910 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2911 usb_syncmem(&sqh->dma, 2912 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2913 sizeof(sqh->qh.qh_elink), 2914 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2915 } 2916 uhci_free_std_chain(sc, ii->stdstart, NULL); 2917 2918 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2919 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2920 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2921 2922 /* XXX Wasteful. */ 2923 if (xfer->pipe->repeat) { 2924 uhci_soft_td_t *data, *dataend; 2925 2926 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 2927 2928 /* This alloc cannot fail since we freed the chain above. */ 2929 uhci_alloc_std_chain(upipe, sc, xfer->length, 2930 upipe->u.intr.isread, xfer->flags, 2931 &xfer->dmabuf, &data, &dataend); 2932 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2933 usb_syncmem(&dataend->dma, 2934 dataend->offs + offsetof(uhci_td_t, td_status), 2935 sizeof(dataend->td.td_status), 2936 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2937 2938 #ifdef UHCI_DEBUG 2939 if (uhcidebug > 10) { 2940 DPRINTF(("uhci_device_intr_done: data(1)\n")); 2941 uhci_dump_tds(data); 2942 uhci_dump_qh(upipe->u.intr.qhs[0]); 2943 } 2944 #endif 2945 2946 ii->stdstart = data; 2947 ii->stdend = dataend; 2948 #ifdef DIAGNOSTIC 2949 if (!ii->isdone) { 2950 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 2951 } 2952 ii->isdone = 0; 2953 #endif 2954 for (i = 0; i < npoll; i++) { 2955 sqh = upipe->u.intr.qhs[i]; 2956 sqh->elink = data; 2957 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2958 usb_syncmem(&sqh->dma, 2959 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2960 sizeof(sqh->qh.qh_elink), 2961 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2962 } 2963 xfer->status = USBD_IN_PROGRESS; 2964 /* The ii is already on the examined list, just leave it. */ 2965 } else { 2966 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 2967 if (uhci_active_intr_info(ii)) 2968 uhci_del_intr_info(ii); 2969 } 2970 } 2971 2972 /* Deallocate request data structures */ 2973 void 2974 uhci_device_ctrl_done(usbd_xfer_handle xfer) 2975 { 2976 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2977 uhci_softc_t *sc = ii->sc; 2978 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2979 int len = UGETW(xfer->request.wLength); 2980 int isread = (xfer->request.bmRequestType & UT_READ); 2981 2982 #ifdef DIAGNOSTIC 2983 if (!(xfer->rqflags & URQ_REQUEST)) 2984 panic("uhci_device_ctrl_done: not a request"); 2985 #endif 2986 2987 if (!uhci_active_intr_info(ii)) 2988 return; 2989 2990 uhci_del_intr_info(ii); /* remove from active list */ 2991 2992 if (upipe->pipe.device->speed == USB_SPEED_LOW) 2993 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 2994 else 2995 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 2996 2997 if (upipe->u.ctl.length != 0) 2998 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 2999 3000 if (len) { 3001 usb_syncmem(&xfer->dmabuf, 0, len, 3002 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3003 } 3004 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3005 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3006 3007 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3008 } 3009 3010 /* Deallocate request data structures */ 3011 void 3012 uhci_device_bulk_done(usbd_xfer_handle xfer) 3013 { 3014 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3015 uhci_softc_t *sc = ii->sc; 3016 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3017 3018 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3019 xfer, ii, sc, upipe)); 3020 3021 if (!uhci_active_intr_info(ii)) 3022 return; 3023 3024 uhci_del_intr_info(ii); /* remove from active list */ 3025 3026 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3027 3028 uhci_free_std_chain(sc, ii->stdstart, NULL); 3029 3030 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3031 } 3032 3033 /* Add interrupt QH, called with vflock. */ 3034 void 3035 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3036 { 3037 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3038 uhci_soft_qh_t *eqh; 3039 3040 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3041 3042 eqh = vf->eqh; 3043 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3044 sizeof(eqh->qh.qh_hlink), 3045 BUS_DMASYNC_POSTWRITE); 3046 sqh->hlink = eqh->hlink; 3047 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3048 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3049 sizeof(sqh->qh.qh_hlink), 3050 BUS_DMASYNC_PREWRITE); 3051 eqh->hlink = sqh; 3052 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3053 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3054 sizeof(eqh->qh.qh_hlink), 3055 BUS_DMASYNC_PREWRITE); 3056 vf->eqh = sqh; 3057 vf->bandwidth++; 3058 } 3059 3060 /* Remove interrupt QH. */ 3061 void 3062 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3063 { 3064 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3065 uhci_soft_qh_t *pqh; 3066 3067 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3068 3069 /* See comment in uhci_remove_ctrl() */ 3070 3071 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3072 sizeof(sqh->qh.qh_elink), 3073 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3074 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3075 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3076 usb_syncmem(&sqh->dma, 3077 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3078 sizeof(sqh->qh.qh_elink), 3079 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3080 delay(UHCI_QH_REMOVE_DELAY); 3081 } 3082 3083 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3084 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3085 sizeof(sqh->qh.qh_hlink), 3086 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3087 pqh->hlink = sqh->hlink; 3088 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3089 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3090 sizeof(pqh->qh.qh_hlink), 3091 BUS_DMASYNC_PREWRITE); 3092 delay(UHCI_QH_REMOVE_DELAY); 3093 if (vf->eqh == sqh) 3094 vf->eqh = pqh; 3095 vf->bandwidth--; 3096 } 3097 3098 usbd_status 3099 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3100 { 3101 uhci_soft_qh_t *sqh; 3102 int i, npoll, s; 3103 u_int bestbw, bw, bestoffs, offs; 3104 3105 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3106 if (ival == 0) { 3107 printf("uhci_device_setintr: 0 interval\n"); 3108 return (USBD_INVAL); 3109 } 3110 3111 if (ival > UHCI_VFRAMELIST_COUNT) 3112 ival = UHCI_VFRAMELIST_COUNT; 3113 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3114 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3115 3116 upipe->u.intr.npoll = npoll; 3117 upipe->u.intr.qhs = 3118 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USBHC, M_WAITOK); 3119 3120 /* 3121 * Figure out which offset in the schedule that has most 3122 * bandwidth left over. 3123 */ 3124 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3125 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3126 for (bw = i = 0; i < npoll; i++) 3127 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3128 if (bw < bestbw) { 3129 bestbw = bw; 3130 bestoffs = offs; 3131 } 3132 } 3133 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3134 3135 for(i = 0; i < npoll; i++) { 3136 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3137 sqh->elink = NULL; 3138 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3139 usb_syncmem(&sqh->dma, 3140 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3141 sizeof(sqh->qh.qh_elink), 3142 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3143 sqh->pos = MOD(i * ival + bestoffs); 3144 } 3145 #undef MOD 3146 3147 s = splusb(); 3148 /* Enter QHs into the controller data structures. */ 3149 for(i = 0; i < npoll; i++) 3150 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3151 splx(s); 3152 3153 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3154 return (USBD_NORMAL_COMPLETION); 3155 } 3156 3157 /* Open a new pipe. */ 3158 usbd_status 3159 uhci_open(usbd_pipe_handle pipe) 3160 { 3161 uhci_softc_t *sc = pipe->device->bus->hci_private; 3162 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3163 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3164 usbd_status err; 3165 int ival; 3166 3167 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3168 pipe, pipe->device->address, 3169 ed->bEndpointAddress, sc->sc_addr)); 3170 3171 upipe->aborting = 0; 3172 /* toggle state needed for bulk endpoints */ 3173 upipe->nexttoggle = pipe->endpoint->datatoggle; 3174 3175 if (pipe->device->address == sc->sc_addr) { 3176 switch (ed->bEndpointAddress) { 3177 case USB_CONTROL_ENDPOINT: 3178 pipe->methods = &uhci_root_ctrl_methods; 3179 break; 3180 case UE_DIR_IN | UHCI_INTR_ENDPT: 3181 pipe->methods = &uhci_root_intr_methods; 3182 break; 3183 default: 3184 return (USBD_INVAL); 3185 } 3186 } else { 3187 switch (ed->bmAttributes & UE_XFERTYPE) { 3188 case UE_CONTROL: 3189 pipe->methods = &uhci_device_ctrl_methods; 3190 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3191 if (upipe->u.ctl.sqh == NULL) 3192 goto bad; 3193 upipe->u.ctl.setup = uhci_alloc_std(sc); 3194 if (upipe->u.ctl.setup == NULL) { 3195 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3196 goto bad; 3197 } 3198 upipe->u.ctl.stat = uhci_alloc_std(sc); 3199 if (upipe->u.ctl.stat == NULL) { 3200 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3201 uhci_free_std(sc, upipe->u.ctl.setup); 3202 goto bad; 3203 } 3204 err = usb_allocmem(&sc->sc_bus, 3205 sizeof(usb_device_request_t), 3206 0, &upipe->u.ctl.reqdma); 3207 if (err) { 3208 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3209 uhci_free_std(sc, upipe->u.ctl.setup); 3210 uhci_free_std(sc, upipe->u.ctl.stat); 3211 goto bad; 3212 } 3213 break; 3214 case UE_INTERRUPT: 3215 pipe->methods = &uhci_device_intr_methods; 3216 ival = pipe->interval; 3217 if (ival == USBD_DEFAULT_INTERVAL) 3218 ival = ed->bInterval; 3219 return (uhci_device_setintr(sc, upipe, ival)); 3220 case UE_ISOCHRONOUS: 3221 pipe->methods = &uhci_device_isoc_methods; 3222 return (uhci_setup_isoc(pipe)); 3223 case UE_BULK: 3224 pipe->methods = &uhci_device_bulk_methods; 3225 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3226 if (upipe->u.bulk.sqh == NULL) 3227 goto bad; 3228 break; 3229 } 3230 } 3231 return (USBD_NORMAL_COMPLETION); 3232 3233 bad: 3234 return (USBD_NOMEM); 3235 } 3236 3237 /* 3238 * Data structures and routines to emulate the root hub. 3239 */ 3240 usb_device_descriptor_t uhci_devd = { 3241 USB_DEVICE_DESCRIPTOR_SIZE, 3242 UDESC_DEVICE, /* type */ 3243 {0x00, 0x01}, /* USB version */ 3244 UDCLASS_HUB, /* class */ 3245 UDSUBCLASS_HUB, /* subclass */ 3246 UDPROTO_FSHUB, /* protocol */ 3247 64, /* max packet */ 3248 {0},{0},{0x00,0x01}, /* device id */ 3249 1,2,0, /* string indicies */ 3250 1 /* # of configurations */ 3251 }; 3252 3253 const usb_config_descriptor_t uhci_confd = { 3254 USB_CONFIG_DESCRIPTOR_SIZE, 3255 UDESC_CONFIG, 3256 {USB_CONFIG_DESCRIPTOR_SIZE + 3257 USB_INTERFACE_DESCRIPTOR_SIZE + 3258 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3259 1, 3260 1, 3261 0, 3262 UC_ATTR_MBO | UC_SELF_POWERED, 3263 0 /* max power */ 3264 }; 3265 3266 const usb_interface_descriptor_t uhci_ifcd = { 3267 USB_INTERFACE_DESCRIPTOR_SIZE, 3268 UDESC_INTERFACE, 3269 0, 3270 0, 3271 1, 3272 UICLASS_HUB, 3273 UISUBCLASS_HUB, 3274 UIPROTO_FSHUB, 3275 0 3276 }; 3277 3278 const usb_endpoint_descriptor_t uhci_endpd = { 3279 USB_ENDPOINT_DESCRIPTOR_SIZE, 3280 UDESC_ENDPOINT, 3281 UE_DIR_IN | UHCI_INTR_ENDPT, 3282 UE_INTERRUPT, 3283 {8}, 3284 255 3285 }; 3286 3287 const usb_hub_descriptor_t uhci_hubd_piix = { 3288 USB_HUB_DESCRIPTOR_SIZE, 3289 UDESC_HUB, 3290 2, 3291 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3292 50, /* power on to power good */ 3293 0, 3294 { 0x00 }, /* both ports are removable */ 3295 { 0 }, 3296 }; 3297 3298 /* 3299 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3300 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3301 * should not be used by the USB subsystem. As we cannot issue a 3302 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3303 * will be enabled as part of the reset. 3304 * 3305 * On the VT83C572, the port cannot be successfully enabled until the 3306 * outstanding "port enable change" and "connection status change" 3307 * events have been reset. 3308 */ 3309 Static usbd_status 3310 uhci_portreset(uhci_softc_t *sc, int index) 3311 { 3312 int lim, port, x; 3313 3314 if (index == 1) 3315 port = UHCI_PORTSC1; 3316 else if (index == 2) 3317 port = UHCI_PORTSC2; 3318 else 3319 return (USBD_IOERROR); 3320 3321 x = URWMASK(UREAD2(sc, port)); 3322 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3323 3324 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3325 3326 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3327 index, UREAD2(sc, port))); 3328 3329 x = URWMASK(UREAD2(sc, port)); 3330 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3331 3332 delay(100); 3333 3334 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3335 index, UREAD2(sc, port))); 3336 3337 x = URWMASK(UREAD2(sc, port)); 3338 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3339 3340 for (lim = 10; --lim > 0;) { 3341 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3342 3343 x = UREAD2(sc, port); 3344 3345 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3346 index, lim, x)); 3347 3348 if (!(x & UHCI_PORTSC_CCS)) { 3349 /* 3350 * No device is connected (or was disconnected 3351 * during reset). Consider the port reset. 3352 * The delay must be long enough to ensure on 3353 * the initial iteration that the device 3354 * connection will have been registered. 50ms 3355 * appears to be sufficient, but 20ms is not. 3356 */ 3357 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3358 index, lim)); 3359 break; 3360 } 3361 3362 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3363 /* 3364 * Port enabled changed and/or connection 3365 * status changed were set. Reset either or 3366 * both raised flags (by writing a 1 to that 3367 * bit), and wait again for state to settle. 3368 */ 3369 UWRITE2(sc, port, URWMASK(x) | 3370 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3371 continue; 3372 } 3373 3374 if (x & UHCI_PORTSC_PE) 3375 /* Port is enabled */ 3376 break; 3377 3378 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3379 } 3380 3381 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3382 index, UREAD2(sc, port))); 3383 3384 if (lim <= 0) { 3385 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3386 return (USBD_TIMEOUT); 3387 } 3388 3389 sc->sc_isreset = 1; 3390 return (USBD_NORMAL_COMPLETION); 3391 } 3392 3393 /* 3394 * Simulate a hardware hub by handling all the necessary requests. 3395 */ 3396 usbd_status 3397 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3398 { 3399 usbd_status err; 3400 3401 /* Insert last in queue. */ 3402 err = usb_insert_transfer(xfer); 3403 if (err) 3404 return (err); 3405 3406 /* 3407 * Pipe isn't running (otherwise err would be USBD_INPROG), 3408 * so start it first. 3409 */ 3410 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3411 } 3412 3413 usbd_status 3414 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3415 { 3416 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3417 usb_device_request_t *req; 3418 void *buf = NULL; 3419 int port, x; 3420 int s, len, value, index, status, change, l, totlen = 0; 3421 usb_port_status_t ps; 3422 usbd_status err; 3423 3424 if (sc->sc_dying) 3425 return (USBD_IOERROR); 3426 3427 #ifdef DIAGNOSTIC 3428 if (!(xfer->rqflags & URQ_REQUEST)) 3429 panic("uhci_root_ctrl_transfer: not a request"); 3430 #endif 3431 req = &xfer->request; 3432 3433 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3434 req->bmRequestType, req->bRequest)); 3435 3436 len = UGETW(req->wLength); 3437 value = UGETW(req->wValue); 3438 index = UGETW(req->wIndex); 3439 3440 if (len != 0) 3441 buf = KERNADDR(&xfer->dmabuf, 0); 3442 3443 #define C(x,y) ((x) | ((y) << 8)) 3444 switch(C(req->bRequest, req->bmRequestType)) { 3445 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3446 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3447 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3448 /* 3449 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3450 * for the integrated root hub. 3451 */ 3452 break; 3453 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3454 if (len > 0) { 3455 *(u_int8_t *)buf = sc->sc_conf; 3456 totlen = 1; 3457 } 3458 break; 3459 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3460 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3461 if (len == 0) 3462 break; 3463 switch(value >> 8) { 3464 case UDESC_DEVICE: 3465 if ((value & 0xff) != 0) { 3466 err = USBD_IOERROR; 3467 goto ret; 3468 } 3469 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3470 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3471 memcpy(buf, &uhci_devd, l); 3472 break; 3473 case UDESC_CONFIG: 3474 if ((value & 0xff) != 0) { 3475 err = USBD_IOERROR; 3476 goto ret; 3477 } 3478 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3479 memcpy(buf, &uhci_confd, l); 3480 buf = (char *)buf + l; 3481 len -= l; 3482 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3483 totlen += l; 3484 memcpy(buf, &uhci_ifcd, l); 3485 buf = (char *)buf + l; 3486 len -= l; 3487 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3488 totlen += l; 3489 memcpy(buf, &uhci_endpd, l); 3490 break; 3491 case UDESC_STRING: 3492 #define sd ((usb_string_descriptor_t *)buf) 3493 switch (value & 0xff) { 3494 case 0: /* Language table */ 3495 totlen = usb_makelangtbl(sd, len); 3496 break; 3497 case 1: /* Vendor */ 3498 totlen = usb_makestrdesc(sd, len, 3499 sc->sc_vendor); 3500 break; 3501 case 2: /* Product */ 3502 totlen = usb_makestrdesc(sd, len, 3503 "UHCI root hub"); 3504 break; 3505 } 3506 #undef sd 3507 break; 3508 default: 3509 err = USBD_IOERROR; 3510 goto ret; 3511 } 3512 break; 3513 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3514 if (len > 0) { 3515 *(u_int8_t *)buf = 0; 3516 totlen = 1; 3517 } 3518 break; 3519 case C(UR_GET_STATUS, UT_READ_DEVICE): 3520 if (len > 1) { 3521 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3522 totlen = 2; 3523 } 3524 break; 3525 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3526 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3527 if (len > 1) { 3528 USETW(((usb_status_t *)buf)->wStatus, 0); 3529 totlen = 2; 3530 } 3531 break; 3532 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3533 if (value >= USB_MAX_DEVICES) { 3534 err = USBD_IOERROR; 3535 goto ret; 3536 } 3537 sc->sc_addr = value; 3538 break; 3539 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3540 if (value != 0 && value != 1) { 3541 err = USBD_IOERROR; 3542 goto ret; 3543 } 3544 sc->sc_conf = value; 3545 break; 3546 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3547 break; 3548 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3549 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3550 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3551 err = USBD_IOERROR; 3552 goto ret; 3553 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3554 break; 3555 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3556 break; 3557 /* Hub requests */ 3558 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3559 break; 3560 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3561 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3562 "port=%d feature=%d\n", 3563 index, value)); 3564 if (index == 1) 3565 port = UHCI_PORTSC1; 3566 else if (index == 2) 3567 port = UHCI_PORTSC2; 3568 else { 3569 err = USBD_IOERROR; 3570 goto ret; 3571 } 3572 switch(value) { 3573 case UHF_PORT_ENABLE: 3574 x = URWMASK(UREAD2(sc, port)); 3575 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3576 break; 3577 case UHF_PORT_SUSPEND: 3578 x = URWMASK(UREAD2(sc, port)); 3579 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3580 break; 3581 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3582 /* see USB2 spec ch. 7.1.7.7 */ 3583 usb_delay_ms(&sc->sc_bus, 20); 3584 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3585 /* 10ms resume delay must be provided by caller */ 3586 break; 3587 case UHF_PORT_RESET: 3588 x = URWMASK(UREAD2(sc, port)); 3589 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3590 break; 3591 case UHF_C_PORT_CONNECTION: 3592 x = URWMASK(UREAD2(sc, port)); 3593 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3594 break; 3595 case UHF_C_PORT_ENABLE: 3596 x = URWMASK(UREAD2(sc, port)); 3597 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3598 break; 3599 case UHF_C_PORT_OVER_CURRENT: 3600 x = URWMASK(UREAD2(sc, port)); 3601 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3602 break; 3603 case UHF_C_PORT_RESET: 3604 sc->sc_isreset = 0; 3605 err = USBD_NORMAL_COMPLETION; 3606 goto ret; 3607 case UHF_PORT_CONNECTION: 3608 case UHF_PORT_OVER_CURRENT: 3609 case UHF_PORT_POWER: 3610 case UHF_PORT_LOW_SPEED: 3611 case UHF_C_PORT_SUSPEND: 3612 default: 3613 err = USBD_IOERROR; 3614 goto ret; 3615 } 3616 break; 3617 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3618 if (index == 1) 3619 port = UHCI_PORTSC1; 3620 else if (index == 2) 3621 port = UHCI_PORTSC2; 3622 else { 3623 err = USBD_IOERROR; 3624 goto ret; 3625 } 3626 if (len > 0) { 3627 *(u_int8_t *)buf = 3628 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3629 UHCI_PORTSC_LS_SHIFT; 3630 totlen = 1; 3631 } 3632 break; 3633 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3634 if (len == 0) 3635 break; 3636 if ((value & 0xff) != 0) { 3637 err = USBD_IOERROR; 3638 goto ret; 3639 } 3640 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3641 totlen = l; 3642 memcpy(buf, &uhci_hubd_piix, l); 3643 break; 3644 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3645 if (len != 4) { 3646 err = USBD_IOERROR; 3647 goto ret; 3648 } 3649 memset(buf, 0, len); 3650 totlen = len; 3651 break; 3652 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3653 if (index == 1) 3654 port = UHCI_PORTSC1; 3655 else if (index == 2) 3656 port = UHCI_PORTSC2; 3657 else { 3658 err = USBD_IOERROR; 3659 goto ret; 3660 } 3661 if (len != 4) { 3662 err = USBD_IOERROR; 3663 goto ret; 3664 } 3665 x = UREAD2(sc, port); 3666 status = change = 0; 3667 if (x & UHCI_PORTSC_CCS) 3668 status |= UPS_CURRENT_CONNECT_STATUS; 3669 if (x & UHCI_PORTSC_CSC) 3670 change |= UPS_C_CONNECT_STATUS; 3671 if (x & UHCI_PORTSC_PE) 3672 status |= UPS_PORT_ENABLED; 3673 if (x & UHCI_PORTSC_POEDC) 3674 change |= UPS_C_PORT_ENABLED; 3675 if (x & UHCI_PORTSC_OCI) 3676 status |= UPS_OVERCURRENT_INDICATOR; 3677 if (x & UHCI_PORTSC_OCIC) 3678 change |= UPS_C_OVERCURRENT_INDICATOR; 3679 if (x & UHCI_PORTSC_SUSP) 3680 status |= UPS_SUSPEND; 3681 if (x & UHCI_PORTSC_LSDA) 3682 status |= UPS_LOW_SPEED; 3683 status |= UPS_PORT_POWER; 3684 if (sc->sc_isreset) 3685 change |= UPS_C_PORT_RESET; 3686 USETW(ps.wPortStatus, status); 3687 USETW(ps.wPortChange, change); 3688 l = min(len, sizeof ps); 3689 memcpy(buf, &ps, l); 3690 totlen = l; 3691 break; 3692 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3693 err = USBD_IOERROR; 3694 goto ret; 3695 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3696 break; 3697 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3698 if (index == 1) 3699 port = UHCI_PORTSC1; 3700 else if (index == 2) 3701 port = UHCI_PORTSC2; 3702 else { 3703 err = USBD_IOERROR; 3704 goto ret; 3705 } 3706 switch(value) { 3707 case UHF_PORT_ENABLE: 3708 x = URWMASK(UREAD2(sc, port)); 3709 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3710 break; 3711 case UHF_PORT_SUSPEND: 3712 x = URWMASK(UREAD2(sc, port)); 3713 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3714 break; 3715 case UHF_PORT_RESET: 3716 err = uhci_portreset(sc, index); 3717 goto ret; 3718 case UHF_PORT_POWER: 3719 /* Pretend we turned on power */ 3720 err = USBD_NORMAL_COMPLETION; 3721 goto ret; 3722 case UHF_C_PORT_CONNECTION: 3723 case UHF_C_PORT_ENABLE: 3724 case UHF_C_PORT_OVER_CURRENT: 3725 case UHF_PORT_CONNECTION: 3726 case UHF_PORT_OVER_CURRENT: 3727 case UHF_PORT_LOW_SPEED: 3728 case UHF_C_PORT_SUSPEND: 3729 case UHF_C_PORT_RESET: 3730 default: 3731 err = USBD_IOERROR; 3732 goto ret; 3733 } 3734 break; 3735 default: 3736 err = USBD_IOERROR; 3737 goto ret; 3738 } 3739 xfer->actlen = totlen; 3740 err = USBD_NORMAL_COMPLETION; 3741 ret: 3742 xfer->status = err; 3743 s = splusb(); 3744 usb_transfer_complete(xfer); 3745 splx(s); 3746 return (USBD_IN_PROGRESS); 3747 } 3748 3749 /* Abort a root control request. */ 3750 void 3751 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3752 { 3753 /* Nothing to do, all transfers are synchronous. */ 3754 } 3755 3756 /* Close the root pipe. */ 3757 void 3758 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3759 { 3760 DPRINTF(("uhci_root_ctrl_close\n")); 3761 } 3762 3763 /* Abort a root interrupt request. */ 3764 void 3765 uhci_root_intr_abort(usbd_xfer_handle xfer) 3766 { 3767 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3768 3769 callout_stop(&sc->sc_poll_handle); 3770 sc->sc_intr_xfer = NULL; 3771 3772 if (xfer->pipe->intrxfer == xfer) { 3773 DPRINTF(("uhci_root_intr_abort: remove\n")); 3774 xfer->pipe->intrxfer = 0; 3775 } 3776 xfer->status = USBD_CANCELLED; 3777 #ifdef DIAGNOSTIC 3778 UXFER(xfer)->iinfo.isdone = 1; 3779 #endif 3780 usb_transfer_complete(xfer); 3781 } 3782 3783 usbd_status 3784 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3785 { 3786 usbd_status err; 3787 3788 /* Insert last in queue. */ 3789 err = usb_insert_transfer(xfer); 3790 if (err) 3791 return (err); 3792 3793 /* 3794 * Pipe isn't running (otherwise err would be USBD_INPROG), 3795 * start first 3796 */ 3797 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3798 } 3799 3800 /* Start a transfer on the root interrupt pipe */ 3801 usbd_status 3802 uhci_root_intr_start(usbd_xfer_handle xfer) 3803 { 3804 usbd_pipe_handle pipe = xfer->pipe; 3805 uhci_softc_t *sc = pipe->device->bus->hci_private; 3806 unsigned int ival; 3807 3808 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3809 xfer, xfer->length, xfer->flags)); 3810 3811 if (sc->sc_dying) 3812 return (USBD_IOERROR); 3813 3814 /* XXX temporary variable needed to avoid gcc3 warning */ 3815 ival = xfer->pipe->endpoint->edesc->bInterval; 3816 sc->sc_ival = mstohz(ival); 3817 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3818 sc->sc_intr_xfer = xfer; 3819 return (USBD_IN_PROGRESS); 3820 } 3821 3822 /* Close the root interrupt pipe. */ 3823 void 3824 uhci_root_intr_close(usbd_pipe_handle pipe) 3825 { 3826 uhci_softc_t *sc = pipe->device->bus->hci_private; 3827 3828 callout_stop(&sc->sc_poll_handle); 3829 sc->sc_intr_xfer = NULL; 3830 DPRINTF(("uhci_root_intr_close\n")); 3831 } 3832