1 /* $NetBSD: be.c,v 1.59 2008/05/04 17:14:41 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.59 2008/05/04 17:14:41 xtraeme Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 #include "bpfilter.h" 65 #include "rnd.h" 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/callout.h> 70 #include <sys/kernel.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 #if NRND > 0 79 #include <sys/rnd.h> 80 #endif 81 82 #include <net/if.h> 83 #include <net/if_dl.h> 84 #include <net/if_types.h> 85 #include <net/netisr.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #ifdef INET 90 #include <netinet/in.h> 91 #include <netinet/if_inarp.h> 92 #include <netinet/in_systm.h> 93 #include <netinet/in_var.h> 94 #include <netinet/ip.h> 95 #endif 96 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 #include <machine/autoconf.h> 106 107 #include <dev/sbus/sbusvar.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/sbus/qecreg.h> 113 #include <dev/sbus/qecvar.h> 114 #include <dev/sbus/bereg.h> 115 116 struct be_softc { 117 struct device sc_dev; 118 struct sbusdev sc_sd; /* sbus device */ 119 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 120 bus_dma_tag_t sc_dmatag; 121 bus_dmamap_t sc_dmamap; 122 struct ethercom sc_ethercom; 123 /*struct ifmedia sc_ifmedia; -* interface media */ 124 struct mii_data sc_mii; /* MII media control */ 125 #define sc_media sc_mii.mii_media/* shorthand */ 126 int sc_phys[2]; /* MII instance -> phy */ 127 128 struct callout sc_tick_ch; 129 130 /* 131 * Some `mii_softc' items we need to emulate MII operation 132 * for our internal transceiver. 133 */ 134 int sc_mii_inst; /* instance of internal phy */ 135 int sc_mii_active; /* currently active medium */ 136 int sc_mii_ticks; /* tick counter */ 137 int sc_mii_flags; /* phy status flags */ 138 #define MIIF_HAVELINK 0x04000000 139 int sc_intphy_curspeed; /* Established link speed */ 140 141 struct qec_softc *sc_qec; /* QEC parent */ 142 143 bus_space_handle_t sc_qr; /* QEC registers */ 144 bus_space_handle_t sc_br; /* BE registers */ 145 bus_space_handle_t sc_cr; /* channel registers */ 146 bus_space_handle_t sc_tr; /* transceiver registers */ 147 148 u_int sc_rev; 149 150 int sc_channel; /* channel number */ 151 int sc_burst; 152 153 struct qec_ring sc_rb; /* Packet Ring Buffer */ 154 155 /* MAC address */ 156 u_int8_t sc_enaddr[6]; 157 #ifdef BEDEBUG 158 int sc_debug; 159 #endif 160 }; 161 162 int bematch(struct device *, struct cfdata *, void *); 163 void beattach(struct device *, struct device *, void *); 164 165 void beinit(struct be_softc *); 166 void bestart(struct ifnet *); 167 void bestop(struct be_softc *); 168 void bewatchdog(struct ifnet *); 169 int beioctl(struct ifnet *, u_long, void *); 170 void bereset(struct be_softc *); 171 172 int beintr(void *); 173 int berint(struct be_softc *); 174 int betint(struct be_softc *); 175 int beqint(struct be_softc *, u_int32_t); 176 int beeint(struct be_softc *, u_int32_t); 177 178 static void be_read(struct be_softc *, int, int); 179 static int be_put(struct be_softc *, int, struct mbuf *); 180 static struct mbuf *be_get(struct be_softc *, int, int); 181 182 void be_pal_gate(struct be_softc *, int); 183 184 /* ifmedia callbacks */ 185 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 186 int be_ifmedia_upd(struct ifnet *); 187 188 void be_mcreset(struct be_softc *); 189 190 /* MII methods & callbacks */ 191 static int be_mii_readreg(struct device *, int, int); 192 static void be_mii_writereg(struct device *, int, int, int); 193 static void be_mii_statchg(struct device *); 194 195 /* MII helpers */ 196 static void be_mii_sync(struct be_softc *); 197 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 198 static int be_mii_reset(struct be_softc *, int); 199 static int be_tcvr_read_bit(struct be_softc *, int); 200 static void be_tcvr_write_bit(struct be_softc *, int, int); 201 202 void be_tick(void *); 203 void be_intphy_auto(struct be_softc *); 204 void be_intphy_status(struct be_softc *); 205 int be_intphy_service(struct be_softc *, struct mii_data *, int); 206 207 208 CFATTACH_DECL(be, sizeof(struct be_softc), 209 bematch, beattach, NULL, NULL); 210 211 int 212 bematch(parent, cf, aux) 213 struct device *parent; 214 struct cfdata *cf; 215 void *aux; 216 { 217 struct sbus_attach_args *sa = aux; 218 219 return (strcmp(cf->cf_name, sa->sa_name) == 0); 220 } 221 222 void 223 beattach(parent, self, aux) 224 struct device *parent, *self; 225 void *aux; 226 { 227 struct sbus_attach_args *sa = aux; 228 struct qec_softc *qec = (struct qec_softc *)parent; 229 struct be_softc *sc = (struct be_softc *)self; 230 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 231 struct mii_data *mii = &sc->sc_mii; 232 struct mii_softc *child; 233 int node = sa->sa_node; 234 bus_dma_tag_t dmatag = sa->sa_dmatag; 235 bus_dma_segment_t seg; 236 bus_size_t size; 237 int instance; 238 int rseg, error; 239 u_int32_t v; 240 241 if (sa->sa_nreg < 3) { 242 printf("%s: only %d register sets\n", 243 device_xname(self), sa->sa_nreg); 244 return; 245 } 246 247 if (bus_space_map(sa->sa_bustag, 248 (bus_addr_t)BUS_ADDR( 249 sa->sa_reg[0].oa_space, 250 sa->sa_reg[0].oa_base), 251 (bus_size_t)sa->sa_reg[0].oa_size, 252 0, &sc->sc_cr) != 0) { 253 printf("beattach: cannot map registers\n"); 254 return; 255 } 256 257 if (bus_space_map(sa->sa_bustag, 258 (bus_addr_t)BUS_ADDR( 259 sa->sa_reg[1].oa_space, 260 sa->sa_reg[1].oa_base), 261 (bus_size_t)sa->sa_reg[1].oa_size, 262 0, &sc->sc_br) != 0) { 263 printf("beattach: cannot map registers\n"); 264 return; 265 } 266 267 if (bus_space_map(sa->sa_bustag, 268 (bus_addr_t)BUS_ADDR( 269 sa->sa_reg[2].oa_space, 270 sa->sa_reg[2].oa_base), 271 (bus_size_t)sa->sa_reg[2].oa_size, 272 0, &sc->sc_tr) != 0) { 273 printf("beattach: cannot map registers\n"); 274 return; 275 } 276 277 sc->sc_bustag = sa->sa_bustag; 278 sc->sc_qec = qec; 279 sc->sc_qr = qec->sc_regs; 280 281 sc->sc_rev = prom_getpropint(node, "board-version", -1); 282 printf(" rev %x", sc->sc_rev); 283 284 bestop(sc); 285 286 sc->sc_channel = prom_getpropint(node, "channel#", -1); 287 if (sc->sc_channel == -1) 288 sc->sc_channel = 0; 289 290 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 291 if (sc->sc_burst == -1) 292 sc->sc_burst = qec->sc_burst; 293 294 /* Clamp at parent's burst sizes */ 295 sc->sc_burst &= qec->sc_burst; 296 297 /* Establish interrupt handler */ 298 if (sa->sa_nintr) 299 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 300 beintr, sc); 301 302 prom_getether(node, sc->sc_enaddr); 303 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 304 305 /* 306 * Allocate descriptor ring and buffers. 307 */ 308 309 /* for now, allocate as many bufs as there are ring descriptors */ 310 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 311 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 312 313 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 314 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 315 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 316 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 317 318 /* Get a DMA handle */ 319 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 320 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 321 aprint_error_dev(self, "DMA map create error %d\n", error); 322 return; 323 } 324 325 /* Allocate DMA buffer */ 326 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 327 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 328 aprint_error_dev(self, "DMA buffer alloc error %d\n", 329 error); 330 return; 331 } 332 333 /* Map DMA memory in CPU addressable space */ 334 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 335 &sc->sc_rb.rb_membase, 336 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 337 aprint_error_dev(self, "DMA buffer map error %d\n", 338 error); 339 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 340 return; 341 } 342 343 /* Load the buffer */ 344 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 345 sc->sc_rb.rb_membase, size, NULL, 346 BUS_DMA_NOWAIT)) != 0) { 347 aprint_error_dev(self, "DMA buffer map load error %d\n", 348 error); 349 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 350 bus_dmamem_free(dmatag, &seg, rseg); 351 return; 352 } 353 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 354 355 /* 356 * Initialize our media structures and MII info. 357 */ 358 mii->mii_ifp = ifp; 359 mii->mii_readreg = be_mii_readreg; 360 mii->mii_writereg = be_mii_writereg; 361 mii->mii_statchg = be_mii_statchg; 362 363 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 364 365 callout_init(&sc->sc_tick_ch, 0); 366 367 /* 368 * Initialize transceiver and determine which PHY connection to use. 369 */ 370 be_mii_sync(sc); 371 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 372 373 instance = 0; 374 375 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 376 377 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 378 MII_OFFSET_ANY, 0); 379 380 child = LIST_FIRST(&mii->mii_phys); 381 if (child == NULL) { 382 /* No PHY attached */ 383 ifmedia_add(&sc->sc_media, 384 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 385 0, NULL); 386 ifmedia_set(&sc->sc_media, 387 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 388 } else { 389 /* 390 * Note: we support just one PHY on the external 391 * MII connector. 392 */ 393 #ifdef DIAGNOSTIC 394 if (LIST_NEXT(child, mii_list) != NULL) { 395 aprint_error_dev(&sc->sc_dev, "spurious MII device %s attached\n", 396 device_xname(child->mii_dev)); 397 } 398 #endif 399 if (child->mii_phy != BE_PHY_EXTERNAL || 400 child->mii_inst > 0) { 401 aprint_error_dev(&sc->sc_dev, "cannot accommodate MII device %s" 402 " at phy %d, instance %d\n", 403 device_xname(child->mii_dev), 404 child->mii_phy, child->mii_inst); 405 } else { 406 sc->sc_phys[instance] = child->mii_phy; 407 } 408 409 /* 410 * XXX - we can really do the following ONLY if the 411 * phy indeed has the auto negotiation capability!! 412 */ 413 ifmedia_set(&sc->sc_media, 414 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 415 416 /* Mark our current media setting */ 417 be_pal_gate(sc, BE_PHY_EXTERNAL); 418 instance++; 419 } 420 421 } 422 423 if ((v & MGMT_PAL_INT_MDIO) != 0) { 424 /* 425 * The be internal phy looks vaguely like MII hardware, 426 * but not enough to be able to use the MII device 427 * layer. Hence, we have to take care of media selection 428 * ourselves. 429 */ 430 431 sc->sc_mii_inst = instance; 432 sc->sc_phys[instance] = BE_PHY_INTERNAL; 433 434 /* Use `ifm_data' to store BMCR bits */ 435 ifmedia_add(&sc->sc_media, 436 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 437 0, NULL); 438 ifmedia_add(&sc->sc_media, 439 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 440 BMCR_S100, NULL); 441 ifmedia_add(&sc->sc_media, 442 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 443 0, NULL); 444 445 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 446 device_xname(self)); 447 448 be_mii_reset(sc, BE_PHY_INTERNAL); 449 /* Only set default medium here if there's no external PHY */ 450 if (instance == 0) { 451 be_pal_gate(sc, BE_PHY_INTERNAL); 452 ifmedia_set(&sc->sc_media, 453 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 454 } else 455 be_mii_writereg((void *)sc, 456 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 457 } 458 459 memcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 460 ifp->if_softc = sc; 461 ifp->if_start = bestart; 462 ifp->if_ioctl = beioctl; 463 ifp->if_watchdog = bewatchdog; 464 ifp->if_flags = 465 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 466 IFQ_SET_READY(&ifp->if_snd); 467 468 /* claim 802.1q capability */ 469 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 470 471 /* Attach the interface. */ 472 if_attach(ifp); 473 ether_ifattach(ifp, sc->sc_enaddr); 474 } 475 476 477 /* 478 * Routine to copy from mbuf chain to transmit buffer in 479 * network buffer memory. 480 */ 481 static inline int 482 be_put(sc, idx, m) 483 struct be_softc *sc; 484 int idx; 485 struct mbuf *m; 486 { 487 struct mbuf *n; 488 int len, tlen = 0, boff = 0; 489 void *bp; 490 491 bp = (char *)sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 492 493 for (; m; m = n) { 494 len = m->m_len; 495 if (len == 0) { 496 MFREE(m, n); 497 continue; 498 } 499 memcpy((char *)bp + boff, mtod(m, void *), len); 500 boff += len; 501 tlen += len; 502 MFREE(m, n); 503 } 504 return (tlen); 505 } 506 507 /* 508 * Pull data off an interface. 509 * Len is the length of data, with local net header stripped. 510 * We copy the data into mbufs. When full cluster sized units are present, 511 * we copy into clusters. 512 */ 513 static inline struct mbuf * 514 be_get(sc, idx, totlen) 515 struct be_softc *sc; 516 int idx, totlen; 517 { 518 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 519 struct mbuf *m; 520 struct mbuf *top, **mp; 521 int len, pad, boff = 0; 522 void *bp; 523 524 bp = (char *)sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 525 526 MGETHDR(m, M_DONTWAIT, MT_DATA); 527 if (m == NULL) 528 return (NULL); 529 m->m_pkthdr.rcvif = ifp; 530 m->m_pkthdr.len = totlen; 531 532 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 533 m->m_data += pad; 534 len = MHLEN - pad; 535 top = NULL; 536 mp = ⊤ 537 538 while (totlen > 0) { 539 if (top) { 540 MGET(m, M_DONTWAIT, MT_DATA); 541 if (m == NULL) { 542 m_freem(top); 543 return (NULL); 544 } 545 len = MLEN; 546 } 547 if (top && totlen >= MINCLSIZE) { 548 MCLGET(m, M_DONTWAIT); 549 if (m->m_flags & M_EXT) 550 len = MCLBYTES; 551 } 552 m->m_len = len = min(totlen, len); 553 memcpy(mtod(m, void *), (char *)bp + boff, len); 554 boff += len; 555 totlen -= len; 556 *mp = m; 557 mp = &m->m_next; 558 } 559 560 return (top); 561 } 562 563 /* 564 * Pass a packet to the higher levels. 565 */ 566 static inline void 567 be_read(sc, idx, len) 568 struct be_softc *sc; 569 int idx, len; 570 { 571 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 572 struct mbuf *m; 573 574 if (len <= sizeof(struct ether_header) || 575 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 576 #ifdef BEDEBUG 577 if (sc->sc_debug) 578 printf("%s: invalid packet size %d; dropping\n", 579 ifp->if_xname, len); 580 #endif 581 ifp->if_ierrors++; 582 return; 583 } 584 585 /* 586 * Pull packet off interface. 587 */ 588 m = be_get(sc, idx, len); 589 if (m == NULL) { 590 ifp->if_ierrors++; 591 return; 592 } 593 ifp->if_ipackets++; 594 595 #if NBPFILTER > 0 596 /* 597 * Check if there's a BPF listener on this interface. 598 * If so, hand off the raw packet to BPF. 599 */ 600 if (ifp->if_bpf) 601 bpf_mtap(ifp->if_bpf, m); 602 #endif 603 /* Pass the packet up. */ 604 (*ifp->if_input)(ifp, m); 605 } 606 607 /* 608 * Start output on interface. 609 * We make two assumptions here: 610 * 1) that the current priority is set to splnet _before_ this code 611 * is called *and* is returned to the appropriate priority after 612 * return 613 * 2) that the IFF_OACTIVE flag is checked before this code is called 614 * (i.e. that the output part of the interface is idle) 615 */ 616 void 617 bestart(ifp) 618 struct ifnet *ifp; 619 { 620 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 621 struct qec_xd *txd = sc->sc_rb.rb_txd; 622 struct mbuf *m; 623 unsigned int bix, len; 624 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 625 626 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 627 return; 628 629 bix = sc->sc_rb.rb_tdhead; 630 631 for (;;) { 632 IFQ_DEQUEUE(&ifp->if_snd, m); 633 if (m == 0) 634 break; 635 636 #if NBPFILTER > 0 637 /* 638 * If BPF is listening on this interface, let it see the 639 * packet before we commit it to the wire. 640 */ 641 if (ifp->if_bpf) 642 bpf_mtap(ifp->if_bpf, m); 643 #endif 644 645 /* 646 * Copy the mbuf chain into the transmit buffer. 647 */ 648 len = be_put(sc, bix, m); 649 650 /* 651 * Initialize transmit registers and start transmission 652 */ 653 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 654 (len & QEC_XD_LENGTH); 655 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 656 BE_CR_CTRL_TWAKEUP); 657 658 if (++bix == QEC_XD_RING_MAXSIZE) 659 bix = 0; 660 661 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 662 ifp->if_flags |= IFF_OACTIVE; 663 break; 664 } 665 } 666 667 sc->sc_rb.rb_tdhead = bix; 668 } 669 670 void 671 bestop(sc) 672 struct be_softc *sc; 673 { 674 int n; 675 bus_space_tag_t t = sc->sc_bustag; 676 bus_space_handle_t br = sc->sc_br; 677 678 callout_stop(&sc->sc_tick_ch); 679 680 /* Down the MII. */ 681 mii_down(&sc->sc_mii); 682 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 683 684 /* Stop the transmitter */ 685 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 686 for (n = 32; n > 0; n--) { 687 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 688 break; 689 DELAY(20); 690 } 691 692 /* Stop the receiver */ 693 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 694 for (n = 32; n > 0; n--) { 695 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 696 break; 697 DELAY(20); 698 } 699 } 700 701 /* 702 * Reset interface. 703 */ 704 void 705 bereset(sc) 706 struct be_softc *sc; 707 { 708 int s; 709 710 s = splnet(); 711 bestop(sc); 712 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 713 beinit(sc); 714 splx(s); 715 } 716 717 void 718 bewatchdog(ifp) 719 struct ifnet *ifp; 720 { 721 struct be_softc *sc = ifp->if_softc; 722 723 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 724 ++sc->sc_ethercom.ec_if.if_oerrors; 725 726 bereset(sc); 727 } 728 729 int 730 beintr(v) 731 void *v; 732 { 733 struct be_softc *sc = (struct be_softc *)v; 734 bus_space_tag_t t = sc->sc_bustag; 735 u_int32_t whyq, whyb, whyc; 736 int r = 0; 737 738 /* Read QEC status, channel status and BE status */ 739 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 740 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 741 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 742 743 if (whyq & QEC_STAT_BM) 744 r |= beeint(sc, whyb); 745 746 if (whyq & QEC_STAT_ER) 747 r |= beqint(sc, whyc); 748 749 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 750 r |= betint(sc); 751 752 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 753 r |= berint(sc); 754 755 return (r); 756 } 757 758 /* 759 * QEC Interrupt. 760 */ 761 int 762 beqint(sc, why) 763 struct be_softc *sc; 764 u_int32_t why; 765 { 766 int r = 0, rst = 0; 767 768 if (why & BE_CR_STAT_TXIRQ) 769 r |= 1; 770 if (why & BE_CR_STAT_RXIRQ) 771 r |= 1; 772 773 if (why & BE_CR_STAT_BERROR) { 774 r |= 1; 775 rst = 1; 776 aprint_error_dev(&sc->sc_dev, "bigmac error\n"); 777 } 778 779 if (why & BE_CR_STAT_TXDERR) { 780 r |= 1; 781 rst = 1; 782 aprint_error_dev(&sc->sc_dev, "bogus tx descriptor\n"); 783 } 784 785 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 786 r |= 1; 787 rst = 1; 788 aprint_error_dev(&sc->sc_dev, "tx DMA error ( "); 789 if (why & BE_CR_STAT_TXLERR) 790 printf("Late "); 791 if (why & BE_CR_STAT_TXPERR) 792 printf("Parity "); 793 if (why & BE_CR_STAT_TXSERR) 794 printf("Generic "); 795 printf(")\n"); 796 } 797 798 if (why & BE_CR_STAT_RXDROP) { 799 r |= 1; 800 rst = 1; 801 aprint_error_dev(&sc->sc_dev, "out of rx descriptors\n"); 802 } 803 804 if (why & BE_CR_STAT_RXSMALL) { 805 r |= 1; 806 rst = 1; 807 aprint_error_dev(&sc->sc_dev, "rx descriptor too small\n"); 808 } 809 810 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 811 r |= 1; 812 rst = 1; 813 aprint_error_dev(&sc->sc_dev, "rx DMA error ( "); 814 if (why & BE_CR_STAT_RXLERR) 815 printf("Late "); 816 if (why & BE_CR_STAT_RXPERR) 817 printf("Parity "); 818 if (why & BE_CR_STAT_RXSERR) 819 printf("Generic "); 820 printf(")\n"); 821 } 822 823 if (!r) { 824 rst = 1; 825 aprint_error_dev(&sc->sc_dev, "unexpected error interrupt %08x\n", 826 why); 827 } 828 829 if (rst) { 830 printf("%s: resetting\n", device_xname(&sc->sc_dev)); 831 bereset(sc); 832 } 833 834 return (r); 835 } 836 837 /* 838 * Error interrupt. 839 */ 840 int 841 beeint(sc, why) 842 struct be_softc *sc; 843 u_int32_t why; 844 { 845 int r = 0, rst = 0; 846 847 if (why & BE_BR_STAT_RFIFOVF) { 848 r |= 1; 849 rst = 1; 850 aprint_error_dev(&sc->sc_dev, "receive fifo overrun\n"); 851 } 852 if (why & BE_BR_STAT_TFIFO_UND) { 853 r |= 1; 854 rst = 1; 855 aprint_error_dev(&sc->sc_dev, "transmit fifo underrun\n"); 856 } 857 if (why & BE_BR_STAT_MAXPKTERR) { 858 r |= 1; 859 rst = 1; 860 aprint_error_dev(&sc->sc_dev, "max packet size error\n"); 861 } 862 863 if (!r) { 864 rst = 1; 865 aprint_error_dev(&sc->sc_dev, "unexpected error interrupt %08x\n", 866 why); 867 } 868 869 if (rst) { 870 printf("%s: resetting\n", device_xname(&sc->sc_dev)); 871 bereset(sc); 872 } 873 874 return (r); 875 } 876 877 /* 878 * Transmit interrupt. 879 */ 880 int 881 betint(sc) 882 struct be_softc *sc; 883 { 884 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 885 bus_space_tag_t t = sc->sc_bustag; 886 bus_space_handle_t br = sc->sc_br; 887 unsigned int bix, txflags; 888 889 /* 890 * Unload collision counters 891 */ 892 ifp->if_collisions += 893 bus_space_read_4(t, br, BE_BRI_NCCNT) + 894 bus_space_read_4(t, br, BE_BRI_FCCNT) + 895 bus_space_read_4(t, br, BE_BRI_EXCNT) + 896 bus_space_read_4(t, br, BE_BRI_LTCNT); 897 898 /* 899 * the clear the hardware counters 900 */ 901 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 902 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 903 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 904 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 905 906 bix = sc->sc_rb.rb_tdtail; 907 908 for (;;) { 909 if (sc->sc_rb.rb_td_nbusy <= 0) 910 break; 911 912 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 913 914 if (txflags & QEC_XD_OWN) 915 break; 916 917 ifp->if_flags &= ~IFF_OACTIVE; 918 ifp->if_opackets++; 919 920 if (++bix == QEC_XD_RING_MAXSIZE) 921 bix = 0; 922 923 --sc->sc_rb.rb_td_nbusy; 924 } 925 926 sc->sc_rb.rb_tdtail = bix; 927 928 bestart(ifp); 929 930 if (sc->sc_rb.rb_td_nbusy == 0) 931 ifp->if_timer = 0; 932 933 return (1); 934 } 935 936 /* 937 * Receive interrupt. 938 */ 939 int 940 berint(sc) 941 struct be_softc *sc; 942 { 943 struct qec_xd *xd = sc->sc_rb.rb_rxd; 944 unsigned int bix, len; 945 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 946 947 bix = sc->sc_rb.rb_rdtail; 948 949 /* 950 * Process all buffers with valid data. 951 */ 952 for (;;) { 953 len = xd[bix].xd_flags; 954 if (len & QEC_XD_OWN) 955 break; 956 957 len &= QEC_XD_LENGTH; 958 be_read(sc, bix, len); 959 960 /* ... */ 961 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 962 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 963 964 if (++bix == QEC_XD_RING_MAXSIZE) 965 bix = 0; 966 } 967 968 sc->sc_rb.rb_rdtail = bix; 969 970 return (1); 971 } 972 973 int 974 beioctl(ifp, cmd, data) 975 struct ifnet *ifp; 976 u_long cmd; 977 void *data; 978 { 979 struct be_softc *sc = ifp->if_softc; 980 struct ifaddr *ifa = (struct ifaddr *)data; 981 struct ifreq *ifr = (struct ifreq *)data; 982 int s, error = 0; 983 984 s = splnet(); 985 986 switch (cmd) { 987 case SIOCSIFADDR: 988 ifp->if_flags |= IFF_UP; 989 switch (ifa->ifa_addr->sa_family) { 990 #ifdef INET 991 case AF_INET: 992 beinit(sc); 993 arp_ifinit(ifp, ifa); 994 break; 995 #endif /* INET */ 996 default: 997 beinit(sc); 998 break; 999 } 1000 break; 1001 1002 case SIOCSIFFLAGS: 1003 if ((ifp->if_flags & IFF_UP) == 0 && 1004 (ifp->if_flags & IFF_RUNNING) != 0) { 1005 /* 1006 * If interface is marked down and it is running, then 1007 * stop it. 1008 */ 1009 bestop(sc); 1010 ifp->if_flags &= ~IFF_RUNNING; 1011 } else if ((ifp->if_flags & IFF_UP) != 0 && 1012 (ifp->if_flags & IFF_RUNNING) == 0) { 1013 /* 1014 * If interface is marked up and it is stopped, then 1015 * start it. 1016 */ 1017 beinit(sc); 1018 } else { 1019 /* 1020 * Reset the interface to pick up changes in any other 1021 * flags that affect hardware registers. 1022 */ 1023 bestop(sc); 1024 beinit(sc); 1025 } 1026 #ifdef BEDEBUG 1027 if (ifp->if_flags & IFF_DEBUG) 1028 sc->sc_debug = 1; 1029 else 1030 sc->sc_debug = 0; 1031 #endif 1032 break; 1033 1034 case SIOCADDMULTI: 1035 case SIOCDELMULTI: 1036 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1037 /* 1038 * Multicast list has changed; set the hardware filter 1039 * accordingly. 1040 */ 1041 if (ifp->if_flags & IFF_RUNNING) 1042 be_mcreset(sc); 1043 error = 0; 1044 } 1045 break; 1046 case SIOCGIFMEDIA: 1047 case SIOCSIFMEDIA: 1048 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1049 break; 1050 default: 1051 error = EINVAL; 1052 break; 1053 } 1054 splx(s); 1055 return (error); 1056 } 1057 1058 1059 void 1060 beinit(sc) 1061 struct be_softc *sc; 1062 { 1063 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1064 bus_space_tag_t t = sc->sc_bustag; 1065 bus_space_handle_t br = sc->sc_br; 1066 bus_space_handle_t cr = sc->sc_cr; 1067 struct qec_softc *qec = sc->sc_qec; 1068 u_int32_t v; 1069 u_int32_t qecaddr; 1070 u_int8_t *ea; 1071 int rc, s; 1072 1073 s = splnet(); 1074 1075 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1076 1077 bestop(sc); 1078 1079 ea = sc->sc_enaddr; 1080 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1081 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1082 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1083 1084 /* Clear hash table */ 1085 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1086 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1087 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1088 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1089 1090 /* Re-initialize RX configuration */ 1091 v = BE_BR_RXCFG_FIFO; 1092 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1093 1094 be_mcreset(sc); 1095 1096 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1097 1098 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1099 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1100 1101 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1102 1103 /* 1104 * Turn off counter expiration interrupts as well as 1105 * 'gotframe' and 'sentframe' 1106 */ 1107 bus_space_write_4(t, br, BE_BRI_IMASK, 1108 BE_BR_IMASK_GOTFRAME | 1109 BE_BR_IMASK_RCNTEXP | 1110 BE_BR_IMASK_ACNTEXP | 1111 BE_BR_IMASK_CCNTEXP | 1112 BE_BR_IMASK_LCNTEXP | 1113 BE_BR_IMASK_CVCNTEXP | 1114 BE_BR_IMASK_SENTFRAME | 1115 BE_BR_IMASK_NCNTEXP | 1116 BE_BR_IMASK_ECNTEXP | 1117 BE_BR_IMASK_LCCNTEXP | 1118 BE_BR_IMASK_FCNTEXP | 1119 BE_BR_IMASK_DTIMEXP); 1120 1121 /* Channel registers: */ 1122 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1123 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1124 1125 qecaddr = sc->sc_channel * qec->sc_msize; 1126 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1127 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1128 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1129 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1130 1131 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1132 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1133 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1134 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1135 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1136 1137 /* Set max packet length */ 1138 v = ETHER_MAX_LEN; 1139 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1140 v += ETHER_VLAN_ENCAP_LEN; 1141 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1142 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1143 1144 /* Enable transmitter */ 1145 bus_space_write_4(t, br, BE_BRI_TXCFG, 1146 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1147 1148 /* Enable receiver */ 1149 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1150 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1151 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1152 1153 if ((rc = be_ifmedia_upd(ifp)) != 0) 1154 goto out; 1155 1156 ifp->if_flags |= IFF_RUNNING; 1157 ifp->if_flags &= ~IFF_OACTIVE; 1158 1159 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1160 out: 1161 splx(s); 1162 } 1163 1164 void 1165 be_mcreset(sc) 1166 struct be_softc *sc; 1167 { 1168 struct ethercom *ec = &sc->sc_ethercom; 1169 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1170 bus_space_tag_t t = sc->sc_bustag; 1171 bus_space_handle_t br = sc->sc_br; 1172 u_int32_t crc; 1173 u_int16_t hash[4]; 1174 u_int8_t octet; 1175 u_int32_t v; 1176 int i, j; 1177 struct ether_multi *enm; 1178 struct ether_multistep step; 1179 1180 if (ifp->if_flags & IFF_PROMISC) { 1181 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1182 v |= BE_BR_RXCFG_PMISC; 1183 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1184 return; 1185 } 1186 1187 if (ifp->if_flags & IFF_ALLMULTI) { 1188 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1189 goto chipit; 1190 } 1191 1192 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1193 1194 ETHER_FIRST_MULTI(step, ec, enm); 1195 while (enm != NULL) { 1196 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1197 /* 1198 * We must listen to a range of multicast 1199 * addresses. For now, just accept all 1200 * multicasts, rather than trying to set only 1201 * those filter bits needed to match the range. 1202 * (At this time, the only use of address 1203 * ranges is for IP multicast routing, for 1204 * which the range is big enough to require 1205 * all bits set.) 1206 */ 1207 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1208 ifp->if_flags |= IFF_ALLMULTI; 1209 goto chipit; 1210 } 1211 1212 crc = 0xffffffff; 1213 1214 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1215 octet = enm->enm_addrlo[i]; 1216 1217 for (j = 0; j < 8; j++) { 1218 if ((crc & 1) ^ (octet & 1)) { 1219 crc >>= 1; 1220 crc ^= MC_POLY_LE; 1221 } 1222 else 1223 crc >>= 1; 1224 octet >>= 1; 1225 } 1226 } 1227 1228 crc >>= 26; 1229 hash[crc >> 4] |= 1 << (crc & 0xf); 1230 ETHER_NEXT_MULTI(step, enm); 1231 } 1232 1233 ifp->if_flags &= ~IFF_ALLMULTI; 1234 1235 chipit: 1236 /* Enable the hash filter */ 1237 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1238 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1239 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1240 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1241 1242 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1243 v &= ~BE_BR_RXCFG_PMISC; 1244 v |= BE_BR_RXCFG_HENABLE; 1245 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1246 } 1247 1248 /* 1249 * Set the tcvr to an idle state 1250 */ 1251 void 1252 be_mii_sync(sc) 1253 struct be_softc *sc; 1254 { 1255 bus_space_tag_t t = sc->sc_bustag; 1256 bus_space_handle_t tr = sc->sc_tr; 1257 int n = 32; 1258 1259 while (n--) { 1260 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1261 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1262 MGMT_PAL_OENAB); 1263 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1264 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1265 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1266 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1267 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1268 } 1269 } 1270 1271 void 1272 be_pal_gate(sc, phy) 1273 struct be_softc *sc; 1274 int phy; 1275 { 1276 bus_space_tag_t t = sc->sc_bustag; 1277 bus_space_handle_t tr = sc->sc_tr; 1278 u_int32_t v; 1279 1280 be_mii_sync(sc); 1281 1282 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1283 if (phy == BE_PHY_INTERNAL) 1284 v &= ~TCVR_PAL_SERIAL; 1285 1286 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1287 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1288 } 1289 1290 static int 1291 be_tcvr_read_bit(sc, phy) 1292 struct be_softc *sc; 1293 int phy; 1294 { 1295 bus_space_tag_t t = sc->sc_bustag; 1296 bus_space_handle_t tr = sc->sc_tr; 1297 int ret; 1298 1299 if (phy == BE_PHY_INTERNAL) { 1300 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1301 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1302 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1303 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1304 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1305 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1306 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1307 } else { 1308 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1309 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1310 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1311 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1312 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1313 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1314 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1315 } 1316 1317 return (ret); 1318 } 1319 1320 static void 1321 be_tcvr_write_bit(sc, phy, bit) 1322 struct be_softc *sc; 1323 int phy; 1324 int bit; 1325 { 1326 bus_space_tag_t t = sc->sc_bustag; 1327 bus_space_handle_t tr = sc->sc_tr; 1328 u_int32_t v; 1329 1330 if (phy == BE_PHY_INTERNAL) { 1331 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1332 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1333 } else { 1334 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1335 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1336 } 1337 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1338 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1339 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1340 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1341 } 1342 1343 static void 1344 be_mii_sendbits(sc, phy, data, nbits) 1345 struct be_softc *sc; 1346 int phy; 1347 u_int32_t data; 1348 int nbits; 1349 { 1350 int i; 1351 1352 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1353 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1354 } 1355 } 1356 1357 static int 1358 be_mii_readreg(self, phy, reg) 1359 struct device *self; 1360 int phy, reg; 1361 { 1362 struct be_softc *sc = (struct be_softc *)self; 1363 int val = 0, i; 1364 1365 /* 1366 * Read the PHY register by manually driving the MII control lines. 1367 */ 1368 be_mii_sync(sc); 1369 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1370 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1371 be_mii_sendbits(sc, phy, phy, 5); 1372 be_mii_sendbits(sc, phy, reg, 5); 1373 1374 (void) be_tcvr_read_bit(sc, phy); 1375 (void) be_tcvr_read_bit(sc, phy); 1376 1377 for (i = 15; i >= 0; i--) 1378 val |= (be_tcvr_read_bit(sc, phy) << i); 1379 1380 (void) be_tcvr_read_bit(sc, phy); 1381 (void) be_tcvr_read_bit(sc, phy); 1382 (void) be_tcvr_read_bit(sc, phy); 1383 1384 return (val); 1385 } 1386 1387 void 1388 be_mii_writereg(self, phy, reg, val) 1389 struct device *self; 1390 int phy, reg, val; 1391 { 1392 struct be_softc *sc = (struct be_softc *)self; 1393 int i; 1394 1395 /* 1396 * Write the PHY register by manually driving the MII control lines. 1397 */ 1398 be_mii_sync(sc); 1399 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1400 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1401 be_mii_sendbits(sc, phy, phy, 5); 1402 be_mii_sendbits(sc, phy, reg, 5); 1403 1404 be_tcvr_write_bit(sc, phy, 1); 1405 be_tcvr_write_bit(sc, phy, 0); 1406 1407 for (i = 15; i >= 0; i--) 1408 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1409 } 1410 1411 int 1412 be_mii_reset(sc, phy) 1413 struct be_softc *sc; 1414 int phy; 1415 { 1416 int n; 1417 1418 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1419 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1420 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1421 1422 for (n = 16; n >= 0; n--) { 1423 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1424 if ((bmcr & BMCR_RESET) == 0) 1425 break; 1426 DELAY(20); 1427 } 1428 if (n == 0) { 1429 aprint_error_dev(&sc->sc_dev, "bmcr reset failed\n"); 1430 return (EIO); 1431 } 1432 1433 return (0); 1434 } 1435 1436 void 1437 be_tick(arg) 1438 void *arg; 1439 { 1440 struct be_softc *sc = arg; 1441 int s = splnet(); 1442 1443 mii_tick(&sc->sc_mii); 1444 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1445 1446 splx(s); 1447 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1448 } 1449 1450 void 1451 be_mii_statchg(self) 1452 struct device *self; 1453 { 1454 struct be_softc *sc = (struct be_softc *)self; 1455 bus_space_tag_t t = sc->sc_bustag; 1456 bus_space_handle_t br = sc->sc_br; 1457 u_int instance; 1458 u_int32_t v; 1459 1460 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1461 #ifdef DIAGNOSTIC 1462 if (instance > 1) 1463 panic("be_mii_statchg: instance %d out of range", instance); 1464 #endif 1465 1466 /* Update duplex mode in TX configuration */ 1467 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1468 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1469 v |= BE_BR_TXCFG_FULLDPLX; 1470 else 1471 v &= ~BE_BR_TXCFG_FULLDPLX; 1472 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1473 1474 /* Change to appropriate gate in transceiver PAL */ 1475 be_pal_gate(sc, sc->sc_phys[instance]); 1476 } 1477 1478 /* 1479 * Get current media settings. 1480 */ 1481 void 1482 be_ifmedia_sts(ifp, ifmr) 1483 struct ifnet *ifp; 1484 struct ifmediareq *ifmr; 1485 { 1486 struct be_softc *sc = ifp->if_softc; 1487 1488 mii_pollstat(&sc->sc_mii); 1489 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1490 1491 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1492 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1493 return; 1494 } 1495 1496 /* 1497 * Set media options. 1498 */ 1499 int 1500 be_ifmedia_upd(ifp) 1501 struct ifnet *ifp; 1502 { 1503 struct be_softc *sc = ifp->if_softc; 1504 int error; 1505 1506 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1507 error = 0; 1508 else if (error != 0) 1509 return error; 1510 1511 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1512 } 1513 1514 /* 1515 * Service routine for our pseudo-MII internal transceiver. 1516 */ 1517 int 1518 be_intphy_service(sc, mii, cmd) 1519 struct be_softc *sc; 1520 struct mii_data *mii; 1521 int cmd; 1522 { 1523 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1524 int bmcr, bmsr; 1525 int error; 1526 1527 switch (cmd) { 1528 case MII_POLLSTAT: 1529 /* 1530 * If we're not polling our PHY instance, just return. 1531 */ 1532 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1533 return (0); 1534 1535 break; 1536 1537 case MII_MEDIACHG: 1538 1539 /* 1540 * If the media indicates a different PHY instance, 1541 * isolate ourselves. 1542 */ 1543 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1544 bmcr = be_mii_readreg((void *)sc, 1545 BE_PHY_INTERNAL, MII_BMCR); 1546 be_mii_writereg((void *)sc, 1547 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1548 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1549 sc->sc_intphy_curspeed = 0; 1550 return (0); 1551 } 1552 1553 1554 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1555 return (error); 1556 1557 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1558 1559 /* 1560 * Select the new mode and take out of isolation 1561 */ 1562 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1563 bmcr |= BMCR_S100; 1564 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1565 bmcr &= ~BMCR_S100; 1566 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1567 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1568 bmcr &= ~BMCR_S100; 1569 bmcr |= sc->sc_intphy_curspeed; 1570 } else { 1571 /* Keep isolated until link is up */ 1572 bmcr |= BMCR_ISO; 1573 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1574 } 1575 } 1576 1577 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1578 bmcr |= BMCR_FDX; 1579 else 1580 bmcr &= ~BMCR_FDX; 1581 1582 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1583 break; 1584 1585 case MII_TICK: 1586 /* 1587 * If we're not currently selected, just return. 1588 */ 1589 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1590 return (0); 1591 1592 /* Only used for automatic media selection */ 1593 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1594 return (0); 1595 1596 /* Is the interface even up? */ 1597 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1598 return (0); 1599 1600 /* 1601 * Check link status; if we don't have a link, try another 1602 * speed. We can't detect duplex mode, so half-duplex is 1603 * what we have to settle for. 1604 */ 1605 1606 /* Read twice in case the register is latched */ 1607 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1608 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1609 1610 if ((bmsr & BMSR_LINK) != 0) { 1611 /* We have a carrier */ 1612 bmcr = be_mii_readreg((void *)sc, 1613 BE_PHY_INTERNAL, MII_BMCR); 1614 1615 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1616 bmcr = be_mii_readreg((void *)sc, 1617 BE_PHY_INTERNAL, MII_BMCR); 1618 1619 sc->sc_mii_flags |= MIIF_HAVELINK; 1620 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1621 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1622 1623 bmcr &= ~BMCR_ISO; 1624 be_mii_writereg((void *)sc, 1625 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1626 1627 printf("%s: link up at %s Mbps\n", 1628 device_xname(&sc->sc_dev), 1629 (bmcr & BMCR_S100) ? "100" : "10"); 1630 } 1631 return (0); 1632 } 1633 1634 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1635 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1636 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1637 sc->sc_intphy_curspeed = 0; 1638 printf("%s: link down\n", device_xname(&sc->sc_dev)); 1639 } 1640 1641 /* Only retry autonegotiation every 5 seconds. */ 1642 if (++sc->sc_mii_ticks < 5) 1643 return(0); 1644 1645 sc->sc_mii_ticks = 0; 1646 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1647 /* Just flip the fast speed bit */ 1648 bmcr ^= BMCR_S100; 1649 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1650 1651 break; 1652 1653 case MII_DOWN: 1654 /* Isolate this phy */ 1655 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1656 be_mii_writereg((void *)sc, 1657 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1658 return (0); 1659 } 1660 1661 /* Update the media status. */ 1662 be_intphy_status(sc); 1663 1664 /* Callback if something changed. */ 1665 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1666 (*mii->mii_statchg)((struct device *)sc); 1667 sc->sc_mii_active = mii->mii_media_active; 1668 } 1669 return (0); 1670 } 1671 1672 /* 1673 * Determine status of internal transceiver 1674 */ 1675 void 1676 be_intphy_status(sc) 1677 struct be_softc *sc; 1678 { 1679 struct mii_data *mii = &sc->sc_mii; 1680 int media_active, media_status; 1681 int bmcr, bmsr; 1682 1683 media_status = IFM_AVALID; 1684 media_active = 0; 1685 1686 /* 1687 * Internal transceiver; do the work here. 1688 */ 1689 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1690 1691 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1692 case (BMCR_S100 | BMCR_FDX): 1693 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1694 break; 1695 case BMCR_S100: 1696 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1697 break; 1698 case BMCR_FDX: 1699 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1700 break; 1701 case 0: 1702 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1703 break; 1704 } 1705 1706 /* Read twice in case the register is latched */ 1707 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1708 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1709 if (bmsr & BMSR_LINK) 1710 media_status |= IFM_ACTIVE; 1711 1712 mii->mii_media_status = media_status; 1713 mii->mii_media_active = media_active; 1714 } 1715