xref: /netbsd-src/sys/dev/qbus/dhureg.h (revision f2523f5b9fb56d6f24081755eb29a853502106fe)
1*f2523f5bSragge /*	$NetBSD: dhureg.h,v 1.5 2003/04/06 15:45:12 ragge Exp $	*/
2545a67b8Sragge /*
3545a67b8Sragge  * Copyright (c) 1996  Ken C. Wellsch.  All rights reserved.
4545a67b8Sragge  *
5545a67b8Sragge  * Redistribution and use in source and binary forms, with or without
6545a67b8Sragge  * modification, are permitted provided that the following conditions
7545a67b8Sragge  * are met:
8545a67b8Sragge  * 1. Redistributions of source code must retain the above copyright
9545a67b8Sragge  *    notice, this list of conditions and the following disclaimer.
10545a67b8Sragge  * 2. Redistributions in binary form must reproduce the above copyright
11545a67b8Sragge  *    notice, this list of conditions and the following disclaimer in the
12545a67b8Sragge  *    documentation and/or other materials provided with the distribution.
13545a67b8Sragge  * 3. All advertising materials mentioning features or use of this software
14545a67b8Sragge  *    must display the following acknowledgement:
15545a67b8Sragge  *	This product includes software developed by the University of
16545a67b8Sragge  *	California, Berkeley and its contributors.
17545a67b8Sragge  * 4. Neither the name of the University nor the names of its contributors
18545a67b8Sragge  *    may be used to endorse or promote products derived from this software
19545a67b8Sragge  *    without specific prior written permission.
20545a67b8Sragge  *
21545a67b8Sragge  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22545a67b8Sragge  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23545a67b8Sragge  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24545a67b8Sragge  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25545a67b8Sragge  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26545a67b8Sragge  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27545a67b8Sragge  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28545a67b8Sragge  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29545a67b8Sragge  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30545a67b8Sragge  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31545a67b8Sragge  * SUCH DAMAGE.
32545a67b8Sragge  */
33545a67b8Sragge 
34542c5517Sragge #ifdef notdef
35545a67b8Sragge union w_b
36545a67b8Sragge {
37545a67b8Sragge 	u_short word;
38545a67b8Sragge 	struct {
39545a67b8Sragge 		u_char byte_lo;
40545a67b8Sragge 		u_char byte_hi;
41545a67b8Sragge 	} bytes;
42545a67b8Sragge };
43545a67b8Sragge 
44545a67b8Sragge struct DHUregs
45545a67b8Sragge {
46545a67b8Sragge 	volatile union w_b u_csr;	/* Control/Status Register (R/W) */
47545a67b8Sragge 	volatile u_short dhu_rbuf;	/* Receive Buffer (R only) */
48545a67b8Sragge #define dhu_txchar	 dhu_rbuf	/* Transmit Character (W only) */
49545a67b8Sragge 	volatile u_short dhu_lpr;	/* Line Parameter Register (R/W) */
50545a67b8Sragge 	volatile u_short dhu_stat;	/* Line Status (R only) */
51545a67b8Sragge 	volatile u_short dhu_lnctrl;	/* Line Control (R/W) */
52545a67b8Sragge 	volatile u_short dhu_tbufad1;	/* Transmit Buffer Address 1 (R/W) */
53545a67b8Sragge 	volatile u_short dhu_tbufad2;	/* Transmit Buffer Address 2 (R/W) */
54545a67b8Sragge 	volatile u_short dhu_tbufcnt;	/* Transmit Buffer Count (R/W) */
55545a67b8Sragge };
56545a67b8Sragge 
57545a67b8Sragge #define dhu_csr		u_csr.word
58545a67b8Sragge #define dhu_csr_lo	u_csr.bytes.byte_lo
59545a67b8Sragge #define dhu_csr_hi	u_csr.bytes.byte_hi
60545a67b8Sragge 
61545a67b8Sragge typedef struct DHUregs dhuregs;
62542c5517Sragge #endif
63542c5517Sragge 
64542c5517Sragge #define	DHU_UBA_CSR	0
65542c5517Sragge #define	DHU_UBA_CSR_HI	1
66542c5517Sragge #define	DHU_UBA_RBUF	2
67542c5517Sragge #define	DHU_UBA_TXCHAR	2
68*f2523f5bSragge #define	DHU_UBA_RXTIME	DHU_UBA_TXCHAR	/* on a real dhu only */
69542c5517Sragge #define	DHU_UBA_LPR	4
70542c5517Sragge #define	DHU_UBA_STAT	6
71*f2523f5bSragge #define	DHU_UBA_FIFO	DHU_UBA_STAT	/* on a real dhu only */
72542c5517Sragge #define	DHU_UBA_LNCTRL	8
73542c5517Sragge #define	DHU_UBA_TBUFAD1	10
74542c5517Sragge #define	DHU_UBA_TBUFAD2	12
75542c5517Sragge #define	DHU_UBA_TBUFCNT	14
76545a67b8Sragge 
77545a67b8Sragge /* CSR bits */
78545a67b8Sragge 
79545a67b8Sragge #define DHU_CSR_TX_ACTION	0100000
80545a67b8Sragge #define DHU_CSR_TXIE		0040000
81545a67b8Sragge #define DHU_CSR_DIAG_FAIL	0020000
82545a67b8Sragge #define DHU_CSR_TX_DMA_ERROR	0010000
83545a67b8Sragge #define DHU_CSR_TX_LINE_MASK	0007400
84545a67b8Sragge #define DHU_CSR_RX_DATA_AVAIL	0000200
85545a67b8Sragge #define DHU_CSR_RXIE		0000100
86545a67b8Sragge #define DHU_CSR_MASTER_RESET	0000040
87545a67b8Sragge #define DHU_CSR_UNUSED		0000020
88545a67b8Sragge #define DHU_CSR_CHANNEL_MASK	0000017
89545a67b8Sragge 
90545a67b8Sragge /* RBUF bits */
91545a67b8Sragge 
92545a67b8Sragge #define DHU_RBUF_DATA_VALID	0100000
93545a67b8Sragge #define DHU_RBUF_OVERRUN_ERR	0040000
94545a67b8Sragge #define DHU_RBUF_FRAMING_ERR	0020000
95545a67b8Sragge #define DHU_RBUF_PARITY_ERR	0010000
96545a67b8Sragge #define DHU_RBUF_RX_LINE_MASK	0007400
97545a67b8Sragge 
98545a67b8Sragge #define DHU_DIAG_CODE		0070001
99545a67b8Sragge #define DHU_MODEM_CODE		0070000
100545a67b8Sragge 
101545a67b8Sragge /* TXCHAR bits */
102545a67b8Sragge 
103545a67b8Sragge #define DHU_TXCHAR_DATA_VALID	0100000
104545a67b8Sragge 
105545a67b8Sragge /* LPR bits */
106545a67b8Sragge 
107545a67b8Sragge #define DHU_LPR_B50		0x0
108545a67b8Sragge #define DHU_LPR_B75		0x1
109545a67b8Sragge #define DHU_LPR_B110		0x2
110545a67b8Sragge #define DHU_LPR_B134		0x3
111545a67b8Sragge #define DHU_LPR_B150		0x4
112545a67b8Sragge #define DHU_LPR_B300		0x5
113545a67b8Sragge #define DHU_LPR_B600		0x6
114545a67b8Sragge #define DHU_LPR_B1200		0x7
115545a67b8Sragge #define DHU_LPR_B1800		0x8
116545a67b8Sragge #define DHU_LPR_B2000		0x9
117545a67b8Sragge #define DHU_LPR_B2400		0xA
118545a67b8Sragge #define DHU_LPR_B4800		0xB
119545a67b8Sragge #define DHU_LPR_B7200		0xC
120545a67b8Sragge #define DHU_LPR_B9600		0xD
121545a67b8Sragge #define DHU_LPR_B19200		0xE
122545a67b8Sragge #define DHU_LPR_B38400		0xF
123545a67b8Sragge 
124545a67b8Sragge #define DHU_LPR_5_BIT_CHAR	0000000
125545a67b8Sragge #define DHU_LPR_6_BIT_CHAR	0000010
126545a67b8Sragge #define DHU_LPR_7_BIT_CHAR	0000020
127545a67b8Sragge #define DHU_LPR_8_BIT_CHAR	0000030
128545a67b8Sragge #define DHU_LPR_PARENB		0000040
129545a67b8Sragge #define DHU_LPR_EPAR		0000100
130545a67b8Sragge #define DHU_LPR_2_STOP		0000200
131545a67b8Sragge 
132545a67b8Sragge /* STAT bits */
133545a67b8Sragge 
134545a67b8Sragge #define DHU_STAT_DSR		0100000
135545a67b8Sragge #define DHU_STAT_RI		0020000
136545a67b8Sragge #define DHU_STAT_DCD		0010000
137545a67b8Sragge #define DHU_STAT_CTS		0004000
138*f2523f5bSragge #define	DHU_STAT_MDL		0001000
139545a67b8Sragge #define DHU_STAT_DHU		0000400
140545a67b8Sragge 
141545a67b8Sragge /* LNCTRL bits */
142545a67b8Sragge 
143545a67b8Sragge #define DHU_LNCTRL_DMA_ABORT	0000001
144545a67b8Sragge #define DHU_LNCTRL_IAUTO	0000002
145545a67b8Sragge #define DHU_LNCTRL_RX_ENABLE	0000004
146545a67b8Sragge #define DHU_LNCTRL_BREAK	0000010
147545a67b8Sragge #define DHU_LNCTRL_OAUTO	0000020
148545a67b8Sragge #define DHU_LNCTRL_FORCE_XOFF	0000040
149545a67b8Sragge #define DHU_LNCTRL_LINK_TYPE	0000400
150545a67b8Sragge #define DHU_LNCTRL_DTR		0001000
151545a67b8Sragge #define DHU_LNCTRL_RTS		0010000
152545a67b8Sragge 
153545a67b8Sragge /* TBUFAD2 bits */
154545a67b8Sragge 
155545a67b8Sragge #define DHU_TBUFAD2_DMA_START	0000200
156545a67b8Sragge #define DHU_TBUFAD2_TX_ENABLE	0100000
157