1 /* $NetBSD: pciide.c,v 1.33 1999/02/22 10:12:00 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI IDE controller driver. 35 * 36 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 37 * sys/dev/pci/ppb.c, revision 1.16). 38 * 39 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 40 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 41 * 5/16/94" from the PCI SIG. 42 * 43 */ 44 45 #define WDCDEBUG 46 47 #define DEBUG_DMA 0x01 48 #define DEBUG_XFERS 0x02 49 #define DEBUG_FUNCS 0x08 50 #define DEBUG_PROBE 0x10 51 #ifdef WDCDEBUG 52 int wdcdebug_pciide_mask = 0; 53 #define WDCDEBUG_PRINT(args, level) \ 54 if (wdcdebug_pciide_mask & (level)) printf args 55 #else 56 #define WDCDEBUG_PRINT(args, level) 57 #endif 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 63 #include <vm/vm.h> 64 #include <vm/vm_param.h> 65 #include <vm/vm_kern.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pciidereg.h> 71 #include <dev/pci/pciidevar.h> 72 #include <dev/pci/pciide_piix_reg.h> 73 #include <dev/pci/pciide_apollo_reg.h> 74 #include <dev/pci/pciide_cmd_reg.h> 75 #include <dev/pci/pciide_cy693_reg.h> 76 #include <dev/pci/pciide_sis_reg.h> 77 #include <dev/pci/pciide_acer_reg.h> 78 #include <dev/ata/atavar.h> 79 #include <dev/ic/wdcreg.h> 80 #include <dev/ic/wdcvar.h> 81 82 /* inlines for reading/writing 8-bit PCI registers */ 83 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 84 int)); 85 static __inline u_int8_t 86 pciide_pci_read(pc, pa, reg) 87 pci_chipset_tag_t pc; 88 pcitag_t pa; 89 int reg; 90 { 91 return ( 92 pci_conf_read(pc, pa, (reg & ~0x03)) >> ((reg & 0x03) * 8) & 0xff); 93 } 94 95 96 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 97 int, u_int8_t)); 98 static __inline void 99 pciide_pci_write(pc, pa, reg, val) 100 pci_chipset_tag_t pc; 101 pcitag_t pa; 102 int reg; 103 u_int8_t val; 104 { 105 pcireg_t pcival; 106 107 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 108 pcival &= ~(0xff << ((reg & 0x03) * 8)); 109 pcival |= (val << ((reg & 0x03) * 8)); 110 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 111 } 112 113 struct pciide_softc { 114 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 115 pci_chipset_tag_t sc_pc; /* PCI registers info */ 116 pcitag_t sc_tag; 117 void *sc_pci_ih; /* PCI interrupt handle */ 118 int sc_dma_ok; /* bus-master DMA info */ 119 bus_space_tag_t sc_dma_iot; 120 bus_space_handle_t sc_dma_ioh; 121 bus_dma_tag_t sc_dmat; 122 /* Chip description */ 123 const struct pciide_product_desc *sc_pp; 124 /* common definitions */ 125 struct channel_softc *wdc_chanarray[PCIIDE_NUM_CHANNELS]; 126 /* internal bookkeeping */ 127 struct pciide_channel { /* per-channel data */ 128 struct channel_softc wdc_channel; /* generic part */ 129 char *name; 130 int hw_ok; /* hardware mapped & OK? */ 131 int compat; /* is it compat? */ 132 void *ih; /* compat or pci handle */ 133 /* DMA tables and DMA map for xfer, for each drive */ 134 struct pciide_dma_maps { 135 bus_dmamap_t dmamap_table; 136 struct idedma_table *dma_table; 137 bus_dmamap_t dmamap_xfer; 138 } dma_maps[2]; 139 } pciide_channels[PCIIDE_NUM_CHANNELS]; 140 }; 141 142 void default_setup_cap __P((struct pciide_softc*)); 143 void default_setup_chip __P((struct pciide_softc*)); 144 void default_channel_map __P((struct pci_attach_args *, 145 struct pciide_channel *)); 146 147 void piix_setup_cap __P((struct pciide_softc*)); 148 void piix_setup_chip __P((struct pciide_softc*)); 149 void piix_setup_channel __P((struct channel_softc*)); 150 void piix3_4_setup_chip __P((struct pciide_softc*)); 151 void piix3_4_setup_channel __P((struct channel_softc*)); 152 void piix_channel_map __P((struct pci_attach_args *, struct pciide_channel *)); 153 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 154 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 155 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 156 157 void apollo_setup_cap __P((struct pciide_softc*)); 158 void apollo_setup_chip __P((struct pciide_softc*)); 159 void apollo_setup_channel __P((struct channel_softc*)); 160 void apollo_channel_map __P((struct pci_attach_args *, 161 struct pciide_channel *)); 162 163 void cmd0643_6_setup_cap __P((struct pciide_softc*)); 164 void cmd0643_6_setup_chip __P((struct pciide_softc*)); 165 void cmd0643_6_setup_channel __P((struct channel_softc*)); 166 void cmd_channel_map __P((struct pci_attach_args *, struct pciide_channel *)); 167 168 void cy693_setup_cap __P((struct pciide_softc*)); 169 void cy693_setup_chip __P((struct pciide_softc*)); 170 void cy693_setup_channel __P((struct channel_softc*)); 171 void cy693_channel_map __P((struct pci_attach_args *, struct pciide_channel *)); 172 173 void sis_setup_cap __P((struct pciide_softc*)); 174 void sis_setup_chip __P((struct pciide_softc*)); 175 void sis_setup_channel __P((struct channel_softc*)); 176 void sis_channel_map __P((struct pci_attach_args *, struct pciide_channel *)); 177 178 void acer_setup_cap __P((struct pciide_softc*)); 179 void acer_setup_chip __P((struct pciide_softc*)); 180 void acer_setup_channel __P((struct channel_softc*)); 181 void acer_channel_map __P((struct pci_attach_args *, struct pciide_channel *)); 182 183 void pciide_channel_dma_setup __P((struct pciide_channel *)); 184 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 185 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 186 void pciide_dma_start __P((void*, int, int, int)); 187 int pciide_dma_finish __P((void*, int, int, int)); 188 void pciide_print_modes __P((struct pciide_channel *)); 189 190 struct pciide_product_desc { 191 u_int32_t ide_product; 192 int ide_flags; 193 int ide_num_channels; 194 const char *ide_name; 195 /* init controller's capabilities for drives probe */ 196 void (*setup_cap) __P((struct pciide_softc*)); 197 /* init controller after drives probe */ 198 void (*setup_chip) __P((struct pciide_softc*)); 199 /* map channel if possible/necessary */ 200 void (*channel_map) __P((struct pci_attach_args *, 201 struct pciide_channel *)); 202 }; 203 204 /* Flags for ide_flags */ 205 #define CMD_PCI064x_IOEN 0x01 /* CMD-style PCI_COMMAND_IO_ENABLE */ 206 #define ONE_QUEUE 0x02 /* device need serialised access */ 207 208 /* Default product description for devices not known from this controller */ 209 const struct pciide_product_desc default_product_desc = { 210 0, 211 0, 212 PCIIDE_NUM_CHANNELS, 213 "Generic PCI IDE controller", 214 default_setup_cap, 215 default_setup_chip, 216 default_channel_map 217 }; 218 219 220 const struct pciide_product_desc pciide_intel_products[] = { 221 { PCI_PRODUCT_INTEL_82092AA, 222 0, 223 PCIIDE_NUM_CHANNELS, 224 "Intel 82092AA IDE controller", 225 default_setup_cap, 226 default_setup_chip, 227 default_channel_map 228 }, 229 { PCI_PRODUCT_INTEL_82371FB_IDE, 230 0, 231 PCIIDE_NUM_CHANNELS, 232 "Intel 82371FB IDE controller (PIIX)", 233 piix_setup_cap, 234 piix_setup_chip, 235 piix_channel_map 236 }, 237 { PCI_PRODUCT_INTEL_82371SB_IDE, 238 0, 239 PCIIDE_NUM_CHANNELS, 240 "Intel 82371SB IDE Interface (PIIX3)", 241 piix_setup_cap, 242 piix3_4_setup_chip, 243 piix_channel_map 244 }, 245 { PCI_PRODUCT_INTEL_82371AB_IDE, 246 0, 247 PCIIDE_NUM_CHANNELS, 248 "Intel 82371AB IDE controller (PIIX4)", 249 piix_setup_cap, 250 piix3_4_setup_chip, 251 piix_channel_map 252 }, 253 { 0, 254 0, 255 0, 256 NULL, 257 } 258 }; 259 const struct pciide_product_desc pciide_cmd_products[] = { 260 { PCI_PRODUCT_CMDTECH_640, 261 ONE_QUEUE | CMD_PCI064x_IOEN, 262 PCIIDE_NUM_CHANNELS, 263 "CMD Technology PCI0640", 264 default_setup_cap, 265 default_setup_chip, 266 cmd_channel_map 267 }, 268 { PCI_PRODUCT_CMDTECH_643, 269 ONE_QUEUE | CMD_PCI064x_IOEN, 270 PCIIDE_NUM_CHANNELS, 271 "CMD Technology PCI0643", 272 cmd0643_6_setup_cap, 273 cmd0643_6_setup_chip, 274 cmd_channel_map 275 }, 276 { PCI_PRODUCT_CMDTECH_646, 277 ONE_QUEUE | CMD_PCI064x_IOEN, 278 PCIIDE_NUM_CHANNELS, 279 "CMD Technology PCI0646", 280 cmd0643_6_setup_cap, 281 cmd0643_6_setup_chip, 282 cmd_channel_map 283 }, 284 { 0, 285 0, 286 0, 287 NULL, 288 } 289 }; 290 291 const struct pciide_product_desc pciide_via_products[] = { 292 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 293 0, 294 PCIIDE_NUM_CHANNELS, 295 "VIA Technologies VT82C586 (Apollo VP) IDE Controller", 296 apollo_setup_cap, 297 apollo_setup_chip, 298 apollo_channel_map 299 }, 300 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 301 0, 302 PCIIDE_NUM_CHANNELS, 303 "VIA Technologies VT82C586A IDE Controller", 304 apollo_setup_cap, 305 apollo_setup_chip, 306 apollo_channel_map 307 }, 308 { 0, 309 0, 310 0, 311 NULL, 312 } 313 }; 314 315 const struct pciide_product_desc pciide_cypress_products[] = { 316 { PCI_PRODUCT_CONTAQ_82C693, 317 0, 318 1, 319 "Contaq Microsystems CY82C693 IDE Controller", 320 cy693_setup_cap, 321 cy693_setup_chip, 322 cy693_channel_map 323 }, 324 { 0, 325 0, 326 0, 327 NULL, 328 } 329 }; 330 331 const struct pciide_product_desc pciide_sis_products[] = { 332 { PCI_PRODUCT_SIS_5597_IDE, 333 0, 334 PCIIDE_NUM_CHANNELS, 335 "Silicon Integrated System 5597/5598 IDE controller", 336 sis_setup_cap, 337 sis_setup_chip, 338 sis_channel_map 339 }, 340 { 0, 341 0, 342 0, 343 NULL, 344 } 345 }; 346 347 const struct pciide_product_desc pciide_acer_products[] = { 348 { PCI_PRODUCT_ALI_M5229, 349 0, 350 PCIIDE_NUM_CHANNELS, 351 "Acer Labs M5229 UDMA IDE Controller", 352 acer_setup_cap, 353 acer_setup_chip, 354 acer_channel_map 355 }, 356 { 0, 357 0, 358 0, 359 NULL, 360 } 361 }; 362 363 struct pciide_vendor_desc { 364 u_int32_t ide_vendor; 365 const struct pciide_product_desc *ide_products; 366 }; 367 368 const struct pciide_vendor_desc pciide_vendors[] = { 369 { PCI_VENDOR_INTEL, pciide_intel_products }, 370 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 371 { PCI_VENDOR_VIATECH, pciide_via_products }, 372 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 373 { PCI_VENDOR_SIS, pciide_sis_products }, 374 { PCI_VENDOR_ALI, pciide_acer_products }, 375 { 0, NULL } 376 }; 377 378 379 #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary") 380 381 /* options passed via the 'flags' config keyword */ 382 #define PCIIDE_OPTIONS_DMA 0x01 383 384 int pciide_match __P((struct device *, struct cfdata *, void *)); 385 void pciide_attach __P((struct device *, struct device *, void *)); 386 387 struct cfattach pciide_ca = { 388 sizeof(struct pciide_softc), pciide_match, pciide_attach 389 }; 390 391 int pciide_mapregs_compat __P(( struct pci_attach_args *, 392 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 393 int pciide_mapregs_native __P((struct pci_attach_args *, 394 struct pciide_channel *, bus_size_t *, bus_size_t *)); 395 void pciide_mapchan __P((struct pci_attach_args *, 396 struct pciide_channel *, int, bus_size_t *, bus_size_t *)); 397 int pciiide_chan_candisable __P((struct pciide_channel *)); 398 void pciide_map_compat_intr __P(( struct pci_attach_args *, 399 struct pciide_channel *, int, int)); 400 int pciide_print __P((void *, const char *pnp)); 401 int pciide_compat_intr __P((void *)); 402 int pciide_pci_intr __P((void *)); 403 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 404 405 const struct pciide_product_desc* 406 pciide_lookup_product(id) 407 u_int32_t id; 408 { 409 const struct pciide_product_desc *pp; 410 const struct pciide_vendor_desc *vp; 411 412 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 413 if (PCI_VENDOR(id) == vp->ide_vendor) 414 break; 415 416 if ((pp = vp->ide_products) == NULL) 417 return NULL; 418 419 for (; pp->ide_name != NULL; pp++) 420 if (PCI_PRODUCT(id) == pp->ide_product) 421 break; 422 423 if (pp->ide_name == NULL) 424 return NULL; 425 return pp; 426 } 427 428 int 429 pciide_match(parent, match, aux) 430 struct device *parent; 431 struct cfdata *match; 432 void *aux; 433 { 434 struct pci_attach_args *pa = aux; 435 436 /* 437 * Check the ID register to see that it's a PCI IDE controller. 438 * If it is, we assume that we can deal with it; it _should_ 439 * work in a standardized way... 440 */ 441 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 442 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 443 return (1); 444 } 445 446 return (0); 447 } 448 449 void 450 pciide_attach(parent, self, aux) 451 struct device *parent, *self; 452 void *aux; 453 { 454 struct pci_attach_args *pa = aux; 455 pci_chipset_tag_t pc = pa->pa_pc; 456 pcitag_t tag = pa->pa_tag; 457 struct pciide_softc *sc = (struct pciide_softc *)self; 458 struct pciide_channel *cp; 459 pcireg_t class, interface, csr; 460 char devinfo[256]; 461 int i; 462 463 sc->sc_pp = pciide_lookup_product(pa->pa_id); 464 if (sc->sc_pp == NULL) { 465 sc->sc_pp = &default_product_desc; 466 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 467 printf(": %s (rev. 0x%02x)\n", devinfo, 468 PCI_REVISION(pa->pa_class)); 469 } else { 470 printf(": %s\n", sc->sc_pp->ide_name); 471 } 472 473 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 474 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 475 /* 476 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 477 * and base adresses registers can be disabled at 478 * hardware level. In this case, the device is wired 479 * in compat mode and its first channel is always enabled, 480 * but we can't rely on PCI_COMMAND_IO_ENABLE. 481 * In fact, it seems that the first channel of the CMD PCI0640 482 * can't be disabled. 483 */ 484 #ifndef PCIIDE_CMD064x_DISABLE 485 if ((sc->sc_pp->ide_flags & CMD_PCI064x_IOEN) == 0) { 486 #else 487 if (1) { 488 #endif 489 printf("%s: device disabled (at %s)\n", 490 sc->sc_wdcdev.sc_dev.dv_xname, 491 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 492 "device" : "bridge"); 493 return; 494 } 495 } 496 497 sc->sc_pc = pa->pa_pc; 498 sc->sc_tag = pa->pa_tag; 499 500 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 501 interface = PCI_INTERFACE(class); 502 503 /* 504 * Map DMA registers, if DMA is supported. 505 * 506 * Note that sc_dma_ok is the right variable to test to see if 507 * DMA can be done. If the interface doesn't support DMA, 508 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 509 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 510 * non-zero if the interface supports DMA and the registers 511 * could be mapped. 512 * 513 * XXX Note that despite the fact that the Bus Master IDE specs 514 * XXX say that "The bus master IDE functoin uses 16 bytes of IO 515 * XXX space," some controllers (at least the United 516 * XXX Microelectronics UM8886BF) place it in memory space. 517 * XXX eventually, we should probably read the register and check 518 * XXX which type it is. Either that or 'quirk' certain devices. 519 */ 520 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 521 printf("%s: bus-master DMA support present", 522 sc->sc_wdcdev.sc_dev.dv_xname); 523 if (sc->sc_pp == &default_product_desc && 524 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 525 PCIIDE_OPTIONS_DMA) == 0) { 526 printf(", but unused (no driver support)"); 527 sc->sc_dma_ok = 0; 528 } else { 529 sc->sc_dma_ok = (pci_mapreg_map(pa, 530 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 531 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 532 sc->sc_dmat = pa->pa_dmat; 533 if (sc->sc_dma_ok == 0) { 534 printf(", but unused (couldn't map registers)"); 535 } else { 536 if (sc->sc_pp == &default_product_desc) 537 printf(", used without full driver " 538 "support"); 539 sc->sc_wdcdev.dma_arg = sc; 540 sc->sc_wdcdev.dma_init = pciide_dma_init; 541 sc->sc_wdcdev.dma_start = pciide_dma_start; 542 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 543 } 544 } 545 } else { 546 printf("%s: pciide0: hardware does not support DMA", 547 sc->sc_wdcdev.sc_dev.dv_xname); 548 } 549 printf("\n"); 550 sc->sc_pp->setup_cap(sc); 551 sc->sc_wdcdev.channels = sc->wdc_chanarray; 552 sc->sc_wdcdev.nchannels = sc->sc_pp->ide_num_channels;; 553 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 554 555 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 556 cp = &sc->pciide_channels[i]; 557 sc->wdc_chanarray[i] = &cp->wdc_channel; 558 559 cp->name = PCIIDE_CHANNEL_NAME(i); 560 561 cp->wdc_channel.channel = i; 562 cp->wdc_channel.wdc = &sc->sc_wdcdev; 563 if (i > 0 && (sc->sc_pp->ide_flags & ONE_QUEUE)) { 564 cp->wdc_channel.ch_queue = 565 sc->pciide_channels[0].wdc_channel.ch_queue; 566 } else { 567 cp->wdc_channel.ch_queue = 568 malloc(sizeof(struct channel_queue), M_DEVBUF, 569 M_NOWAIT); 570 } 571 if (cp->wdc_channel.ch_queue == NULL) { 572 printf("%s %s channel: " 573 "can't allocate memory for command queue", 574 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 575 continue; 576 } 577 printf("%s: %s channel %s to %s mode\n", 578 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 579 (interface & PCIIDE_INTERFACE_SETTABLE(i)) ? 580 "configured" : "wired", 581 (interface & PCIIDE_INTERFACE_PCI(i)) ? "native-PCI" : 582 "compatibility"); 583 584 /* 585 * sc->sc_pp->channel_map() will also call wdcattach. 586 * Eventually the channel will be disabled if there's no 587 * drive present. sc->hw_ok will be updated accordingly. 588 */ 589 sc->sc_pp->channel_map(pa, cp); 590 591 } 592 /* Now that all drives are know, setup DMA, etc ...*/ 593 sc->sc_pp->setup_chip(sc); 594 if (sc->sc_dma_ok) { 595 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 596 csr |= PCI_COMMAND_MASTER_ENABLE; 597 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 598 } 599 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 600 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 601 } 602 603 int 604 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 605 struct pci_attach_args *pa; 606 struct pciide_channel *cp; 607 int compatchan; 608 bus_size_t *cmdsizep, *ctlsizep; 609 { 610 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 611 struct channel_softc *wdc_cp = &cp->wdc_channel; 612 int rv = 1; 613 614 cp->compat = 1; 615 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 616 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 617 618 wdc_cp->cmd_iot = pa->pa_iot; 619 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 620 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 621 printf("%s: couldn't map %s channel cmd regs\n", 622 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 623 rv = 0; 624 } 625 626 wdc_cp->ctl_iot = pa->pa_iot; 627 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 628 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 629 printf("%s: couldn't map %s channel ctl regs\n", 630 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 631 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 632 PCIIDE_COMPAT_CMD_SIZE); 633 rv = 0; 634 } 635 636 return (rv); 637 } 638 639 int 640 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep) 641 struct pci_attach_args * pa; 642 struct pciide_channel *cp; 643 bus_size_t *cmdsizep, *ctlsizep; 644 { 645 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 646 struct channel_softc *wdc_cp = &cp->wdc_channel; 647 const char *intrstr; 648 pci_intr_handle_t intrhandle; 649 650 cp->compat = 0; 651 652 if (sc->sc_pci_ih == NULL) { 653 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 654 pa->pa_intrline, &intrhandle) != 0) { 655 printf("%s: couldn't map native-PCI interrupt\n", 656 sc->sc_wdcdev.sc_dev.dv_xname); 657 return 0; 658 } 659 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 660 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 661 intrhandle, IPL_BIO, pciide_pci_intr, sc); 662 if (sc->sc_pci_ih != NULL) { 663 printf("%s: using %s for native-PCI interrupt\n", 664 sc->sc_wdcdev.sc_dev.dv_xname, 665 intrstr ? intrstr : "unknown interrupt"); 666 } else { 667 printf("%s: couldn't establish native-PCI interrupt", 668 sc->sc_wdcdev.sc_dev.dv_xname); 669 if (intrstr != NULL) 670 printf(" at %s", intrstr); 671 printf("\n"); 672 return 0; 673 } 674 } 675 cp->ih = sc->sc_pci_ih; 676 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 677 PCI_MAPREG_TYPE_IO, 0, 678 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 679 printf("%s: couldn't map %s channel cmd regs\n", 680 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 681 return 0; 682 } 683 684 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 685 PCI_MAPREG_TYPE_IO, 0, 686 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 687 printf("%s: couldn't map %s channel ctl regs\n", 688 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 689 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 690 return 0; 691 } 692 return (1); 693 } 694 695 int 696 pciide_compat_intr(arg) 697 void *arg; 698 { 699 struct pciide_channel *cp = arg; 700 701 #ifdef DIAGNOSTIC 702 /* should only be called for a compat channel */ 703 if (cp->compat == 0) 704 panic("pciide compat intr called for non-compat chan %p\n", cp); 705 #endif 706 return (wdcintr(&cp->wdc_channel)); 707 } 708 709 int 710 pciide_pci_intr(arg) 711 void *arg; 712 { 713 struct pciide_softc *sc = arg; 714 struct pciide_channel *cp; 715 struct channel_softc *wdc_cp; 716 int i, rv, crv; 717 718 rv = 0; 719 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 720 cp = &sc->pciide_channels[i]; 721 wdc_cp = &cp->wdc_channel; 722 723 /* If a compat channel skip. */ 724 if (cp->compat) 725 continue; 726 /* if this channel not waiting for intr, skip */ 727 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 728 continue; 729 730 crv = wdcintr(wdc_cp); 731 if (crv == 0) 732 ; /* leave rv alone */ 733 else if (crv == 1) 734 rv = 1; /* claim the intr */ 735 else if (rv == 0) /* crv should be -1 in this case */ 736 rv = crv; /* if we've done no better, take it */ 737 } 738 return (rv); 739 } 740 741 void 742 pciide_channel_dma_setup(cp) 743 struct pciide_channel *cp; 744 { 745 int drive; 746 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 747 struct ata_drive_datas *drvp; 748 749 for (drive = 0; drive < 2; drive++) { 750 drvp = &cp->wdc_channel.ch_drive[drive]; 751 /* If no drive, skip */ 752 if ((drvp->drive_flags & DRIVE) == 0) 753 continue; 754 /* setup DMA if needed */ 755 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 756 (drvp->drive_flags & DRIVE_UDMA) == 0) || 757 sc->sc_dma_ok == 0) { 758 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 759 continue; 760 } 761 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 762 != 0) { 763 /* Abort DMA setup */ 764 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 765 continue; 766 } 767 } 768 } 769 770 int 771 pciide_dma_table_setup(sc, channel, drive) 772 struct pciide_softc *sc; 773 int channel, drive; 774 { 775 bus_dma_segment_t seg; 776 int error, rseg; 777 const bus_size_t dma_table_size = 778 sizeof(struct idedma_table) * NIDEDMA_TABLES; 779 struct pciide_dma_maps *dma_maps = 780 &sc->pciide_channels[channel].dma_maps[drive]; 781 782 /* If table was already allocated, just return */ 783 if (dma_maps->dma_table) 784 return 0; 785 786 /* Allocate memory for the DMA tables and map it */ 787 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 788 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 789 BUS_DMA_NOWAIT)) != 0) { 790 printf("%s:%d: unable to allocate table DMA for " 791 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 792 channel, drive, error); 793 return error; 794 } 795 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 796 dma_table_size, 797 (caddr_t *)&dma_maps->dma_table, 798 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 799 printf("%s:%d: unable to map table DMA for" 800 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 801 channel, drive, error); 802 return error; 803 } 804 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 805 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 806 seg.ds_addr), DEBUG_PROBE); 807 808 /* Create and load table DMA map for this disk */ 809 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 810 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 811 &dma_maps->dmamap_table)) != 0) { 812 printf("%s:%d: unable to create table DMA map for " 813 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 814 channel, drive, error); 815 return error; 816 } 817 if ((error = bus_dmamap_load(sc->sc_dmat, 818 dma_maps->dmamap_table, 819 dma_maps->dma_table, 820 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 821 printf("%s:%d: unable to load table DMA map for " 822 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 823 channel, drive, error); 824 return error; 825 } 826 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 827 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 828 /* Create a xfer DMA map for this drive */ 829 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 830 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 831 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 832 &dma_maps->dmamap_xfer)) != 0) { 833 printf("%s:%d: unable to create xfer DMA map for " 834 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 835 channel, drive, error); 836 return error; 837 } 838 return 0; 839 } 840 841 int 842 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 843 void *v; 844 int channel, drive; 845 void *databuf; 846 size_t datalen; 847 int flags; 848 { 849 struct pciide_softc *sc = v; 850 int error, seg; 851 struct pciide_dma_maps *dma_maps = 852 &sc->pciide_channels[channel].dma_maps[drive]; 853 854 error = bus_dmamap_load(sc->sc_dmat, 855 dma_maps->dmamap_xfer, 856 databuf, datalen, NULL, BUS_DMA_NOWAIT); 857 if (error) { 858 printf("%s:%d: unable to load xfer DMA map for" 859 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 860 channel, drive, error); 861 return error; 862 } 863 864 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 865 dma_maps->dmamap_xfer->dm_mapsize, 866 (flags & WDC_DMA_READ) ? 867 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 868 869 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 870 #ifdef DIAGNOSTIC 871 /* A segment must not cross a 64k boundary */ 872 { 873 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 874 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 875 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 876 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 877 printf("pciide_dma: segment %d physical addr 0x%lx" 878 " len 0x%lx not properly aligned\n", 879 seg, phys, len); 880 panic("pciide_dma: buf align"); 881 } 882 } 883 #endif 884 dma_maps->dma_table[seg].base_addr = 885 dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 886 dma_maps->dma_table[seg].byte_count = 887 dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 888 IDEDMA_BYTE_COUNT_MASK; 889 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 890 seg, dma_maps->dma_table[seg].byte_count, 891 dma_maps->dma_table[seg].base_addr), DEBUG_DMA); 892 893 } 894 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 895 IDEDMA_BYTE_COUNT_EOT; 896 897 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 898 dma_maps->dmamap_table->dm_mapsize, 899 BUS_DMASYNC_PREWRITE); 900 901 /* Maps are ready. Start DMA function */ 902 #ifdef DIAGNOSTIC 903 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 904 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 905 dma_maps->dmamap_table->dm_segs[0].ds_addr); 906 panic("pciide_dma_init: table align"); 907 } 908 #endif 909 910 /* Clear status bits */ 911 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 912 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 913 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 914 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 915 /* Write table addr */ 916 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 917 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 918 dma_maps->dmamap_table->dm_segs[0].ds_addr); 919 /* set read/write */ 920 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 921 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 922 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 923 return 0; 924 } 925 926 void 927 pciide_dma_start(v, channel, drive, flags) 928 void *v; 929 int channel, drive, flags; 930 { 931 struct pciide_softc *sc = v; 932 933 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 934 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 935 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 936 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 937 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 938 } 939 940 int 941 pciide_dma_finish(v, channel, drive, flags) 942 void *v; 943 int channel, drive; 944 int flags; 945 { 946 struct pciide_softc *sc = v; 947 u_int8_t status; 948 struct pciide_dma_maps *dma_maps = 949 &sc->pciide_channels[channel].dma_maps[drive]; 950 951 /* Unload the map of the data buffer */ 952 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 953 dma_maps->dmamap_xfer->dm_mapsize, 954 (flags & WDC_DMA_READ) ? 955 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 956 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 957 958 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 959 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 960 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 961 DEBUG_XFERS); 962 963 /* stop DMA channel */ 964 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 965 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 966 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 967 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 968 969 /* Clear status bits */ 970 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 971 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 972 status); 973 974 if ((status & IDEDMA_CTL_ERR) != 0) { 975 printf("%s:%d:%d: Bus-Master DMA error: status=0x%x\n", 976 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 977 return -1; 978 } 979 980 if ((flags & WDC_DMA_POLL) == 0 && (status & IDEDMA_CTL_INTR) == 0) { 981 printf("%s:%d:%d: Bus-Master DMA error: missing interrupt, " 982 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 983 drive, status); 984 return -1; 985 } 986 987 if ((status & IDEDMA_CTL_ACT) != 0) { 988 /* data underrun, may be a valid condition for ATAPI */ 989 return 1; 990 } 991 return 0; 992 } 993 994 /* some common code used by several chip channel_map */ 995 void 996 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep) 997 struct pci_attach_args *pa; 998 int interface; 999 struct pciide_channel *cp; 1000 bus_size_t *cmdsizep, *ctlsizep; 1001 { 1002 struct channel_softc *wdc_cp = &cp->wdc_channel; 1003 1004 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1005 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep); 1006 else 1007 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1008 wdc_cp->channel, cmdsizep, ctlsizep); 1009 if (cp->hw_ok == 0) 1010 return; 1011 wdc_cp->data32iot = wdc_cp->cmd_iot; 1012 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1013 wdcattach(wdc_cp); 1014 } 1015 1016 /* 1017 * Generic code to call to know if a channel can be disabled. Return 1 1018 * if channel can be disabled, 0 if not 1019 */ 1020 int 1021 pciiide_chan_candisable(cp) 1022 struct pciide_channel *cp; 1023 { 1024 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1025 struct channel_softc *wdc_cp = &cp->wdc_channel; 1026 1027 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1028 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1029 printf("%s: disabling %s channel (no drives)\n", 1030 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1031 cp->hw_ok = 0; 1032 return 1; 1033 } 1034 return 0; 1035 } 1036 1037 /* 1038 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1039 * Set hw_ok=0 on failure 1040 */ 1041 void 1042 pciide_map_compat_intr(pa, cp, compatchan, interface) 1043 struct pci_attach_args *pa; 1044 struct pciide_channel *cp; 1045 int compatchan, interface; 1046 { 1047 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1048 struct channel_softc *wdc_cp = &cp->wdc_channel; 1049 1050 if (cp->hw_ok == 0) 1051 return; 1052 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1053 return; 1054 1055 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1056 pa, compatchan, pciide_compat_intr, cp); 1057 if (cp->ih == NULL) { 1058 printf("%s: no compatibility interrupt for use by %s " 1059 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1060 cp->hw_ok = 0; 1061 } 1062 } 1063 1064 void 1065 pciide_print_modes(cp) 1066 struct pciide_channel *cp; 1067 { 1068 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1069 int drive; 1070 struct channel_softc *chp; 1071 struct ata_drive_datas *drvp; 1072 1073 chp = &cp->wdc_channel; 1074 for (drive = 0; drive < 2; drive++) { 1075 drvp = &chp->ch_drive[drive]; 1076 if ((drvp->drive_flags & DRIVE) == 0) 1077 continue; 1078 printf("%s(%s:%d:%d): using PIO mode %d", 1079 drvp->drv_softc->dv_xname, 1080 sc->sc_wdcdev.sc_dev.dv_xname, 1081 chp->channel, drive, drvp->PIO_mode); 1082 if (drvp->drive_flags & DRIVE_DMA) 1083 printf(", DMA mode %d", drvp->DMA_mode); 1084 if (drvp->drive_flags & DRIVE_UDMA) 1085 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1086 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1087 printf(" (using DMA data transfers)"); 1088 printf("\n"); 1089 } 1090 } 1091 1092 void 1093 default_setup_cap(sc) 1094 struct pciide_softc *sc; 1095 { 1096 if (sc->sc_dma_ok) 1097 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1098 sc->sc_wdcdev.PIO_cap = 0; 1099 sc->sc_wdcdev.DMA_cap = 0; 1100 } 1101 1102 void 1103 default_setup_chip(sc) 1104 struct pciide_softc *sc; 1105 { 1106 int channel, drive, idedma_ctl; 1107 struct channel_softc *chp; 1108 struct ata_drive_datas *drvp; 1109 1110 if (sc->sc_dma_ok == 0) 1111 return; /* nothing to do */ 1112 1113 /* Allocate DMA maps */ 1114 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1115 idedma_ctl = 0; 1116 chp = &sc->pciide_channels[channel].wdc_channel; 1117 for (drive = 0; drive < 2; drive++) { 1118 drvp = &chp->ch_drive[drive]; 1119 /* If no drive, skip */ 1120 if ((drvp->drive_flags & DRIVE) == 0) 1121 continue; 1122 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1123 continue; 1124 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1125 /* Abort DMA setup */ 1126 printf("%s:%d:%d: can't allocate DMA maps, " 1127 "using PIO transfers\n", 1128 sc->sc_wdcdev.sc_dev.dv_xname, 1129 channel, drive); 1130 drvp->drive_flags &= ~DRIVE_DMA; 1131 } 1132 printf("%s:%d:%d: using DMA data tranferts\n", 1133 sc->sc_wdcdev.sc_dev.dv_xname, 1134 channel, drive); 1135 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1136 } 1137 if (idedma_ctl != 0) { 1138 /* Add software bits in status register */ 1139 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1140 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1141 idedma_ctl); 1142 } 1143 } 1144 1145 } 1146 1147 void 1148 default_channel_map(pa, cp) 1149 struct pci_attach_args *pa; 1150 struct pciide_channel *cp; 1151 { 1152 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1153 bus_size_t cmdsize, ctlsize; 1154 pcireg_t csr; 1155 const char *failreason = NULL; 1156 struct channel_softc *wdc_cp = &cp->wdc_channel; 1157 int interface = 1158 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1159 1160 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1161 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize); 1162 else 1163 cp->hw_ok = pciide_mapregs_compat(pa, cp, wdc_cp->channel, 1164 &cmdsize, &ctlsize); 1165 if (cp->hw_ok == 0) 1166 return; 1167 1168 /* 1169 * Check to see if something appears to be there. 1170 */ 1171 if (!wdcprobe(wdc_cp)) { 1172 failreason = "not responding; disabled or no drives?"; 1173 goto out; 1174 } 1175 1176 /* 1177 * Now, make sure it's actually attributable to this PCI IDE 1178 * channel by trying to access the channel again while the 1179 * PCI IDE controller's I/O space is disabled. (If the 1180 * channel no longer appears to be there, it belongs to 1181 * this controller.) YUCK! 1182 */ 1183 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1184 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1185 csr & ~PCI_COMMAND_IO_ENABLE); 1186 if (wdcprobe(wdc_cp)) 1187 failreason = "other hardware responding at addresses"; 1188 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr); 1189 1190 out: 1191 if (failreason) { 1192 printf("%s: %s channel ignored (%s)\n", 1193 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1194 failreason); 1195 cp->hw_ok = 0; 1196 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, cmdsize); 1197 bus_space_unmap(wdc_cp->ctl_iot, wdc_cp->ctl_ioh, ctlsize); 1198 } 1199 pciide_map_compat_intr(pa, cp, wdc_cp->channel, interface); 1200 if (cp->hw_ok) { 1201 wdc_cp->data32iot = wdc_cp->cmd_iot; 1202 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1203 wdcattach(wdc_cp); 1204 } 1205 } 1206 1207 void 1208 piix_setup_cap(sc) 1209 struct pciide_softc *sc; 1210 { 1211 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371AB_IDE) 1212 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1213 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE | 1214 WDC_CAPABILITY_DMA; 1215 sc->sc_wdcdev.PIO_cap = 4; 1216 sc->sc_wdcdev.DMA_cap = 2; 1217 sc->sc_wdcdev.UDMA_cap = 2; 1218 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371SB_IDE || 1219 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371AB_IDE) 1220 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1221 else 1222 sc->sc_wdcdev.set_modes = piix_setup_channel; 1223 } 1224 1225 void 1226 piix_setup_chip(sc) 1227 struct pciide_softc *sc; 1228 { 1229 u_int8_t channel; 1230 1231 1232 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x\n", 1233 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), DEBUG_PROBE); 1234 1235 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1236 piix_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1237 } 1238 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x\n", 1239 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), DEBUG_PROBE); 1240 } 1241 1242 void 1243 piix_setup_channel(chp) 1244 struct channel_softc *chp; 1245 { 1246 u_int8_t mode[2], drive; 1247 u_int32_t oidetim, idetim, idedma_ctl; 1248 struct pciide_channel *cp = (struct pciide_channel*)chp; 1249 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1250 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1251 1252 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1253 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1254 idedma_ctl = 0; 1255 1256 /* set up new idetim: Enable IDE registers decode */ 1257 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1258 chp->channel); 1259 1260 /* setup DMA */ 1261 pciide_channel_dma_setup(cp); 1262 1263 /* 1264 * Here we have to mess up with drives mode: PIIX can't have 1265 * different timings for master and slave drives. 1266 * We need to find the best combination. 1267 */ 1268 1269 /* If both drives supports DMA, take the lower mode */ 1270 if ((drvp[0].drive_flags & DRIVE_DMA) && 1271 (drvp[1].drive_flags & DRIVE_DMA)) { 1272 mode[0] = mode[1] = 1273 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1274 drvp[0].DMA_mode = mode[0]; 1275 goto ok; 1276 } 1277 /* 1278 * If only one drive supports DMA, use its mode, and 1279 * put the other one in PIO mode 0 if mode not compatible 1280 */ 1281 if (drvp[0].drive_flags & DRIVE_DMA) { 1282 mode[0] = drvp[0].DMA_mode; 1283 mode[1] = drvp[1].PIO_mode; 1284 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1285 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1286 mode[1] = 0; 1287 goto ok; 1288 } 1289 if (drvp[1].drive_flags & DRIVE_DMA) { 1290 mode[1] = drvp[1].DMA_mode; 1291 mode[0] = drvp[0].PIO_mode; 1292 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1293 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1294 mode[0] = 0; 1295 goto ok; 1296 } 1297 /* 1298 * If both drives are not DMA, takes the lower mode, unless 1299 * one of them is PIO mode < 2 1300 */ 1301 if (drvp[0].PIO_mode < 2) { 1302 mode[0] = 0; 1303 mode[1] = drvp[1].PIO_mode; 1304 } else if (drvp[1].PIO_mode < 2) { 1305 mode[1] = 0; 1306 mode[0] = drvp[0].PIO_mode; 1307 } else { 1308 mode[0] = mode[1] = 1309 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1310 } 1311 ok: /* The modes are setup */ 1312 for (drive = 0; drive < 2; drive++) { 1313 if (drvp[drive].drive_flags & DRIVE_DMA) { 1314 drvp[drive].DMA_mode = mode[drive]; 1315 idetim |= piix_setup_idetim_timings( 1316 mode[drive], 1, chp->channel); 1317 goto end; 1318 } else 1319 drvp[drive].PIO_mode = mode[drive]; 1320 } 1321 /* If we are there, none of the drives are DMA */ 1322 if (mode[0] >= 2) 1323 idetim |= piix_setup_idetim_timings( 1324 mode[0], 0, chp->channel); 1325 else 1326 idetim |= piix_setup_idetim_timings( 1327 mode[1], 0, chp->channel); 1328 end: /* 1329 * timing mode is now set up in the controller. Enable 1330 * it per-drive 1331 */ 1332 for (drive = 0; drive < 2; drive++) { 1333 /* If no drive, skip */ 1334 if ((drvp[drive].drive_flags & DRIVE) == 0) 1335 continue; 1336 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1337 if (drvp[drive].drive_flags & DRIVE_DMA) 1338 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1339 } 1340 if (idedma_ctl != 0) { 1341 /* Add software bits in status register */ 1342 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1343 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1344 idedma_ctl); 1345 } 1346 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1347 pciide_print_modes(cp); 1348 } 1349 1350 void 1351 piix3_4_setup_chip(sc) 1352 struct pciide_softc *sc; 1353 { 1354 int channel; 1355 1356 WDCDEBUG_PRINT(("piix3_4_setup_chip: old idetim=0x%x, sidetim=0x%x", 1357 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM), 1358 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), DEBUG_PROBE); 1359 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1360 WDCDEBUG_PRINT((", udamreg 0x%x", 1361 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1362 DEBUG_PROBE); 1363 } 1364 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1365 1366 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1367 piix3_4_setup_channel( 1368 &sc->pciide_channels[channel].wdc_channel); 1369 } 1370 1371 WDCDEBUG_PRINT(("piix3_4_setup_chip: idetim=0x%x, sidetim=0x%x", 1372 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM), 1373 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), DEBUG_PROBE); 1374 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1375 WDCDEBUG_PRINT((", udmareg=0x%x", 1376 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1377 DEBUG_PROBE); 1378 } 1379 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1380 } 1381 1382 void 1383 piix3_4_setup_channel(chp) 1384 struct channel_softc *chp; 1385 { 1386 struct ata_drive_datas *drvp; 1387 u_int32_t oidetim, idetim, sidetim, udmareg, idedma_ctl; 1388 struct pciide_channel *cp = (struct pciide_channel*)chp; 1389 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1390 int drive; 1391 1392 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1393 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1394 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1395 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1396 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(chp->channel) | 1397 PIIX_SIDETIM_RTC_MASK(chp->channel)); 1398 1399 idedma_ctl = 0; 1400 /* If channel disabled, no need to go further */ 1401 if ((PIIX_IDETIM_READ(oidetim, chp->channel) & PIIX_IDETIM_IDE) == 0) 1402 return; 1403 /* set up new idetim: Enable IDE registers decode */ 1404 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, chp->channel); 1405 1406 /* setup DMA if needed */ 1407 pciide_channel_dma_setup(cp); 1408 1409 for (drive = 0; drive < 2; drive++) { 1410 udmareg &= ~(PIIX_UDMACTL_DRV_EN(chp->channel, drive) | 1411 PIIX_UDMATIM_SET(0x3, chp->channel, drive)); 1412 drvp = &chp->ch_drive[drive]; 1413 /* If no drive, skip */ 1414 if ((drvp->drive_flags & DRIVE) == 0) 1415 continue; 1416 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1417 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1418 goto pio; 1419 1420 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1421 (drvp->drive_flags & DRIVE_UDMA)) { 1422 /* use Ultra/DMA */ 1423 drvp->drive_flags &= ~DRIVE_DMA; 1424 udmareg |= PIIX_UDMACTL_DRV_EN( 1425 chp->channel, drive); 1426 udmareg |= PIIX_UDMATIM_SET( 1427 piix4_sct_udma[drvp->UDMA_mode], 1428 chp->channel, drive); 1429 } else { 1430 /* use Multiword DMA */ 1431 drvp->drive_flags &= ~DRIVE_UDMA; 1432 if (drive == 0) { 1433 idetim |= piix_setup_idetim_timings( 1434 drvp->DMA_mode, 1, chp->channel); 1435 } else { 1436 sidetim |= piix_setup_sidetim_timings( 1437 drvp->DMA_mode, 1, chp->channel); 1438 idetim =PIIX_IDETIM_SET(idetim, 1439 PIIX_IDETIM_SITRE, chp->channel); 1440 } 1441 } 1442 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1443 1444 pio: /* use PIO mode */ 1445 idetim |= piix_setup_idetim_drvs(drvp); 1446 if (drive == 0) { 1447 idetim |= piix_setup_idetim_timings( 1448 drvp->PIO_mode, 0, chp->channel); 1449 } else { 1450 sidetim |= piix_setup_sidetim_timings( 1451 drvp->PIO_mode, 0, chp->channel); 1452 idetim =PIIX_IDETIM_SET(idetim, 1453 PIIX_IDETIM_SITRE, chp->channel); 1454 } 1455 } 1456 if (idedma_ctl != 0) { 1457 /* Add software bits in status register */ 1458 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1459 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1460 idedma_ctl); 1461 } 1462 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1463 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1464 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1465 pciide_print_modes(cp); 1466 } 1467 1468 1469 /* setup ISP and RTC fields, based on mode */ 1470 static u_int32_t 1471 piix_setup_idetim_timings(mode, dma, channel) 1472 u_int8_t mode; 1473 u_int8_t dma; 1474 u_int8_t channel; 1475 { 1476 1477 if (dma) 1478 return PIIX_IDETIM_SET(0, 1479 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1480 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1481 channel); 1482 else 1483 return PIIX_IDETIM_SET(0, 1484 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1485 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1486 channel); 1487 } 1488 1489 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1490 static u_int32_t 1491 piix_setup_idetim_drvs(drvp) 1492 struct ata_drive_datas *drvp; 1493 { 1494 u_int32_t ret = 0; 1495 struct channel_softc *chp = drvp->chnl_softc; 1496 u_int8_t channel = chp->channel; 1497 u_int8_t drive = drvp->drive; 1498 1499 /* 1500 * If drive is using UDMA, timings setups are independant 1501 * So just check DMA and PIO here. 1502 */ 1503 if (drvp->drive_flags & DRIVE_DMA) { 1504 /* if mode = DMA mode 0, use compatible timings */ 1505 if ((drvp->drive_flags & DRIVE_DMA) && 1506 drvp->DMA_mode == 0) { 1507 drvp->PIO_mode = 0; 1508 return ret; 1509 } 1510 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1511 /* 1512 * PIO and DMA timings are the same, use fast timings for PIO 1513 * too, else use compat timings. 1514 */ 1515 if ((piix_isp_pio[drvp->PIO_mode] != 1516 piix_isp_dma[drvp->DMA_mode]) || 1517 (piix_rtc_pio[drvp->PIO_mode] != 1518 piix_rtc_dma[drvp->DMA_mode])) 1519 drvp->PIO_mode = 0; 1520 /* if PIO mode <= 2, use compat timings for PIO */ 1521 if (drvp->PIO_mode <= 2) { 1522 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1523 channel); 1524 return ret; 1525 } 1526 } 1527 1528 /* 1529 * Now setup PIO modes. If mode < 2, use compat timings. 1530 * Else enable fast timings. Enable IORDY and prefetch/post 1531 * if PIO mode >= 3. 1532 */ 1533 1534 if (drvp->PIO_mode < 2) 1535 return ret; 1536 1537 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1538 if (drvp->PIO_mode >= 3) { 1539 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1540 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1541 } 1542 return ret; 1543 } 1544 1545 /* setup values in SIDETIM registers, based on mode */ 1546 static u_int32_t 1547 piix_setup_sidetim_timings(mode, dma, channel) 1548 u_int8_t mode; 1549 u_int8_t dma; 1550 u_int8_t channel; 1551 { 1552 if (dma) 1553 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1554 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1555 else 1556 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1557 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1558 } 1559 1560 void 1561 piix_channel_map(pa, cp) 1562 struct pci_attach_args *pa; 1563 struct pciide_channel *cp; 1564 { 1565 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1566 bus_size_t cmdsize, ctlsize; 1567 struct channel_softc *wdc_cp = &cp->wdc_channel; 1568 u_int32_t idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1569 1570 if ((PIIX_IDETIM_READ(idetim, wdc_cp->channel) & 1571 PIIX_IDETIM_IDE) == 0) { 1572 printf("%s: %s channel ignored (disabled)\n", 1573 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1574 return; 1575 } 1576 1577 /* PIIX are compat-only pciide devices */ 1578 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize); 1579 if (cp->hw_ok == 0) 1580 return; 1581 if (pciiide_chan_candisable(cp)) { 1582 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1583 wdc_cp->channel); 1584 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1585 } 1586 pciide_map_compat_intr(pa, cp, wdc_cp->channel, 0); 1587 } 1588 1589 void 1590 apollo_setup_cap(sc) 1591 struct pciide_softc *sc; 1592 { 1593 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1594 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1595 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE | 1596 WDC_CAPABILITY_DMA; 1597 sc->sc_wdcdev.PIO_cap = 4; 1598 sc->sc_wdcdev.DMA_cap = 2; 1599 sc->sc_wdcdev.UDMA_cap = 2; 1600 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1601 1602 } 1603 1604 void 1605 apollo_setup_chip(sc) 1606 struct pciide_softc *sc; 1607 { 1608 int channel; 1609 1610 WDCDEBUG_PRINT(("apollo_setup_chip: old APO_IDECONF=0x%x, " 1611 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1612 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1613 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1614 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1615 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1616 DEBUG_PROBE); 1617 1618 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1619 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1620 } 1621 WDCDEBUG_PRINT(("apollo_setup_chip: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1622 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1623 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1624 } 1625 1626 void 1627 apollo_setup_channel(chp) 1628 struct channel_softc *chp; 1629 { 1630 u_int32_t udmatim_reg, datatim_reg; 1631 u_int8_t idedma_ctl; 1632 int mode, drive; 1633 struct ata_drive_datas *drvp; 1634 struct pciide_channel *cp = (struct pciide_channel*)chp; 1635 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1636 1637 idedma_ctl = 0; 1638 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1639 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1640 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1641 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1642 1643 /* setup DMA if needed */ 1644 pciide_channel_dma_setup(cp); 1645 1646 for (drive = 0; drive < 2; drive++) { 1647 drvp = &chp->ch_drive[drive]; 1648 /* If no drive, skip */ 1649 if ((drvp->drive_flags & DRIVE) == 0) 1650 continue; 1651 /* add timing values, setup DMA if needed */ 1652 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1653 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1654 mode = drvp->PIO_mode; 1655 goto pio; 1656 } 1657 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1658 (drvp->drive_flags & DRIVE_UDMA)) { 1659 /* use Ultra/DMA */ 1660 drvp->drive_flags &= ~DRIVE_DMA; 1661 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1662 APO_UDMA_EN_MTH(chp->channel, drive) | 1663 APO_UDMA_TIME(chp->channel, drive, 1664 apollo_udma_tim[drvp->UDMA_mode]); 1665 /* can use PIO timings, MW DMA unused */ 1666 mode = drvp->PIO_mode; 1667 } else { 1668 /* use Multiword DMA */ 1669 drvp->drive_flags &= ~DRIVE_UDMA; 1670 /* mode = min(pio, dma+2) */ 1671 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1672 mode = drvp->PIO_mode; 1673 else 1674 mode = drvp->DMA_mode; 1675 } 1676 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1677 1678 pio: /* setup PIO mode */ 1679 datatim_reg |= 1680 APO_DATATIM_PULSE(chp->channel, drive, 1681 apollo_pio_set[mode]) | 1682 APO_DATATIM_RECOV(chp->channel, drive, 1683 apollo_pio_rec[mode]); 1684 drvp->PIO_mode = mode; 1685 drvp->DMA_mode = mode - 2; 1686 } 1687 if (idedma_ctl != 0) { 1688 /* Add software bits in status register */ 1689 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1690 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1691 idedma_ctl); 1692 } 1693 pciide_print_modes(cp); 1694 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1695 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1696 } 1697 1698 void 1699 apollo_channel_map(pa, cp) 1700 struct pci_attach_args *pa; 1701 struct pciide_channel *cp; 1702 { 1703 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1704 bus_size_t cmdsize, ctlsize; 1705 struct channel_softc *wdc_cp = &cp->wdc_channel; 1706 u_int32_t ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1707 int interface = 1708 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1709 1710 if ((ideconf & APO_IDECONF_EN(wdc_cp->channel)) == 0) { 1711 printf("%s: %s channel ignored (disabled)\n", 1712 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1713 return; 1714 } 1715 1716 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize); 1717 if (cp->hw_ok == 0) 1718 return; 1719 if (pciiide_chan_candisable(cp)) { 1720 ideconf &= ~APO_IDECONF_EN(wdc_cp->channel); 1721 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, ideconf); 1722 } 1723 pciide_map_compat_intr(pa, cp, wdc_cp->channel, interface); 1724 } 1725 1726 void 1727 cmd_channel_map(pa, cp) 1728 struct pci_attach_args *pa; 1729 struct pciide_channel *cp; 1730 { 1731 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1732 bus_size_t cmdsize, ctlsize; 1733 struct channel_softc *wdc_cp = &cp->wdc_channel; 1734 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1735 int interface = 1736 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1737 1738 /* 1739 * with a CMD PCI64x, if we get here, the first channel is enabled: 1740 * there's no way to disable the first channel without disabling 1741 * the whole device 1742 */ 1743 if (wdc_cp->channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1744 printf("%s: %s channel ignored (disabled)\n", 1745 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1746 return; 1747 } 1748 1749 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize); 1750 if (cp->hw_ok == 0) 1751 return; 1752 if (wdc_cp->channel == 1) { 1753 if (pciiide_chan_candisable(cp)) { 1754 ctrl &= ~CMD_CTRL_2PORT; 1755 pciide_pci_write(pa->pa_pc, pa->pa_tag, 1756 CMD_CTRL, ctrl); 1757 } 1758 } 1759 pciide_map_compat_intr(pa, cp, wdc_cp->channel, interface); 1760 } 1761 1762 void 1763 cmd0643_6_setup_cap(sc) 1764 struct pciide_softc *sc; 1765 { 1766 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE | 1767 WDC_CAPABILITY_DMA; 1768 sc->sc_wdcdev.PIO_cap = 4; 1769 sc->sc_wdcdev.DMA_cap = 2; 1770 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 1771 } 1772 1773 void 1774 cmd0643_6_setup_chip(sc) 1775 struct pciide_softc *sc; 1776 { 1777 int channel; 1778 1779 WDCDEBUG_PRINT(("cmd0643_6_setup_chip: old timings reg 0x%x 0x%x\n", 1780 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 1781 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 1782 DEBUG_PROBE); 1783 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1784 cmd0643_6_setup_channel( 1785 &sc->pciide_channels[channel].wdc_channel); 1786 } 1787 /* configure for DMA read multiple */ 1788 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 1789 WDCDEBUG_PRINT(("cmd0643_6_setup_chip: timings reg now 0x%x 0x%x\n", 1790 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 1791 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 1792 DEBUG_PROBE); 1793 } 1794 1795 void 1796 cmd0643_6_setup_channel(chp) 1797 struct channel_softc *chp; 1798 { 1799 struct ata_drive_datas *drvp; 1800 u_int8_t tim; 1801 u_int32_t idedma_ctl; 1802 int drive; 1803 struct pciide_channel *cp = (struct pciide_channel*)chp; 1804 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1805 1806 idedma_ctl = 0; 1807 /* setup DMA if needed */ 1808 pciide_channel_dma_setup(cp); 1809 1810 for (drive = 0; drive < 2; drive++) { 1811 drvp = &chp->ch_drive[drive]; 1812 /* If no drive, skip */ 1813 if ((drvp->drive_flags & DRIVE) == 0) 1814 continue; 1815 /* add timing values, setup DMA if needed */ 1816 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 1817 if (drvp->drive_flags & DRIVE_DMA) { 1818 /* 1819 * use Multiword DMA. 1820 * Timings will be used for both PIO and DMA, so adjust 1821 * DMA mode if needed 1822 */ 1823 if (drvp->PIO_mode >= 3 && 1824 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 1825 drvp->DMA_mode = drvp->PIO_mode - 2; 1826 } 1827 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 1828 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1829 } 1830 pciide_pci_write(sc->sc_pc, sc->sc_tag, 1831 CMD_DATA_TIM(chp->channel, drive), tim); 1832 } 1833 if (idedma_ctl != 0) { 1834 /* Add software bits in status register */ 1835 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1836 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1837 idedma_ctl); 1838 } 1839 pciide_print_modes(cp); 1840 } 1841 1842 void 1843 cy693_setup_cap(sc) 1844 struct pciide_softc *sc; 1845 { 1846 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE | 1847 WDC_CAPABILITY_DMA; 1848 sc->sc_wdcdev.PIO_cap = 4; 1849 sc->sc_wdcdev.DMA_cap = 2; 1850 sc->sc_wdcdev.set_modes = cy693_setup_channel; 1851 } 1852 1853 void 1854 cy693_setup_chip(sc) 1855 struct pciide_softc *sc; 1856 { 1857 WDCDEBUG_PRINT(("cy693_setup_chip: old timings reg 0x%x\n", 1858 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), 1859 DEBUG_PROBE); 1860 cy693_setup_channel(&sc->pciide_channels[0].wdc_channel); 1861 WDCDEBUG_PRINT(("cy693_setup_chip: new timings reg 0x%x\n", 1862 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 1863 } 1864 1865 void 1866 cy693_setup_channel(chp) 1867 struct channel_softc *chp; 1868 { 1869 struct ata_drive_datas *drvp; 1870 int drive; 1871 u_int32_t cy_cmd_ctrl; 1872 u_int32_t idedma_ctl; 1873 struct pciide_channel *cp = (struct pciide_channel*)chp; 1874 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1875 1876 cy_cmd_ctrl = idedma_ctl = 0; 1877 1878 /* setup DMA if needed */ 1879 pciide_channel_dma_setup(cp); 1880 1881 for (drive = 0; drive < 2; drive++) { 1882 drvp = &chp->ch_drive[drive]; 1883 /* If no drive, skip */ 1884 if ((drvp->drive_flags & DRIVE) == 0) 1885 continue; 1886 /* add timing values, setup DMA if needed */ 1887 if (drvp->drive_flags & DRIVE_DMA) { 1888 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1889 /* 1890 * use Multiword DMA 1891 * Timings will be used for both PIO and DMA, so adjust 1892 * DMA mode if needed 1893 */ 1894 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 1895 drvp->PIO_mode = drvp->DMA_mode + 2; 1896 if (drvp->DMA_mode == 0) 1897 drvp->PIO_mode = 0; 1898 } 1899 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 1900 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 1901 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 1902 CY_CMD_CTRL_IOW_REC_OFF(drive)); 1903 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 1904 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 1905 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 1906 CY_CMD_CTRL_IOR_REC_OFF(drive)); 1907 } 1908 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 1909 pciide_print_modes(cp); 1910 if (idedma_ctl != 0) { 1911 /* Add software bits in status register */ 1912 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1913 IDEDMA_CTL, idedma_ctl); 1914 } 1915 } 1916 1917 void 1918 cy693_channel_map(pa, cp) 1919 struct pci_attach_args *pa; 1920 struct pciide_channel *cp; 1921 { 1922 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1923 bus_size_t cmdsize, ctlsize; 1924 struct channel_softc *wdc_cp = &cp->wdc_channel; 1925 int interface = 1926 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1927 int compatchan; 1928 1929 #ifdef DIAGNOSTIC 1930 if (wdc_cp->channel != 0) 1931 panic("cy693_channel_map: channel %d", wdc_cp->channel); 1932 #endif 1933 1934 /* 1935 * this chip has 2 PCI IDE functions, one for primary and one for 1936 * secondary. So we need to call pciide_mapregs_compat() with 1937 * the real channel 1938 */ 1939 if (pa->pa_function == 1) { 1940 compatchan = 0; 1941 } else if (pa->pa_function == 2) { 1942 compatchan = 1; 1943 } else { 1944 printf("%s: unexpected PCI function %d\n", 1945 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 1946 cp->hw_ok = 0; 1947 return; 1948 } 1949 1950 /* Only one channel for this chip; if we are here it's enabled */ 1951 if (interface & PCIIDE_INTERFACE_PCI(0)) 1952 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize); 1953 else 1954 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 1955 &cmdsize, &ctlsize); 1956 if (cp->hw_ok == 0) 1957 return; 1958 wdc_cp->data32iot = wdc_cp->cmd_iot; 1959 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1960 wdcattach(wdc_cp); 1961 if (pciiide_chan_candisable(cp)) { 1962 pci_conf_write(sc->sc_pc, sc->sc_tag, 1963 PCI_COMMAND_STATUS_REG, 0); 1964 } 1965 pciide_map_compat_intr(pa, cp, compatchan, interface); 1966 } 1967 1968 void 1969 sis_setup_cap(sc) 1970 struct pciide_softc *sc; 1971 { 1972 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE | 1973 WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1974 sc->sc_wdcdev.PIO_cap = 4; 1975 sc->sc_wdcdev.DMA_cap = 2; 1976 sc->sc_wdcdev.UDMA_cap = 2; 1977 sc->sc_wdcdev.set_modes = sis_setup_channel; 1978 } 1979 1980 void 1981 sis_setup_chip(sc) 1982 struct pciide_softc *sc; 1983 { 1984 int channel; 1985 1986 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1987 sis_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1988 } 1989 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 1990 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 1991 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 1992 } 1993 1994 void 1995 sis_setup_channel(chp) 1996 struct channel_softc *chp; 1997 { 1998 struct ata_drive_datas *drvp; 1999 int drive; 2000 u_int32_t sis_tim; 2001 u_int32_t idedma_ctl; 2002 struct pciide_channel *cp = (struct pciide_channel*)chp; 2003 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2004 2005 WDCDEBUG_PRINT(("sis_setup_chip: old timings reg for " 2006 "channel %d 0x%x\n", chp->channel, 2007 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2008 DEBUG_PROBE); 2009 sis_tim = 0; 2010 idedma_ctl = 0; 2011 /* setup DMA if needed */ 2012 pciide_channel_dma_setup(cp); 2013 2014 for (drive = 0; drive < 2; drive++) { 2015 drvp = &chp->ch_drive[drive]; 2016 /* If no drive, skip */ 2017 if ((drvp->drive_flags & DRIVE) == 0) 2018 continue; 2019 /* add timing values, setup DMA if needed */ 2020 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2021 (drvp->drive_flags & DRIVE_UDMA) == 0) 2022 goto pio; 2023 2024 if (drvp->drive_flags & DRIVE_UDMA) { 2025 /* use Ultra/DMA */ 2026 drvp->drive_flags &= ~DRIVE_DMA; 2027 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2028 SIS_TIM_UDMA_TIME_OFF(drive); 2029 sis_tim |= SIS_TIM_UDMA_EN(drive); 2030 } else { 2031 /* 2032 * use Multiword DMA 2033 * Timings will be used for both PIO and DMA, 2034 * so adjust DMA mode if needed 2035 */ 2036 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2037 drvp->PIO_mode = drvp->DMA_mode + 2; 2038 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2039 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2040 drvp->PIO_mode - 2 : 0; 2041 if (drvp->DMA_mode == 0) 2042 drvp->PIO_mode = 0; 2043 } 2044 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2045 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2046 SIS_TIM_ACT_OFF(drive); 2047 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2048 SIS_TIM_REC_OFF(drive); 2049 } 2050 WDCDEBUG_PRINT(("sis_setup_chip: new timings reg for " 2051 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2052 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2053 if (idedma_ctl != 0) { 2054 /* Add software bits in status register */ 2055 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2056 IDEDMA_CTL, idedma_ctl); 2057 } 2058 pciide_print_modes(cp); 2059 } 2060 2061 void 2062 sis_channel_map(pa, cp) 2063 struct pci_attach_args *pa; 2064 struct pciide_channel *cp; 2065 { 2066 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2067 bus_size_t cmdsize, ctlsize; 2068 struct channel_softc *wdc_cp = &cp->wdc_channel; 2069 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2070 int interface = 2071 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2072 2073 if ((wdc_cp->channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2074 (wdc_cp->channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2075 printf("%s: %s channel ignored (disabled)\n", 2076 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2077 return; 2078 } 2079 2080 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize); 2081 if (cp->hw_ok == 0) 2082 return; 2083 if (pciiide_chan_candisable(cp)) { 2084 if (wdc_cp->channel == 0) 2085 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2086 else 2087 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2088 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, sis_ctr0); 2089 } 2090 pciide_map_compat_intr(pa, cp, wdc_cp->channel, interface); 2091 } 2092 2093 void 2094 acer_setup_cap(sc) 2095 struct pciide_softc *sc; 2096 { 2097 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE | 2098 WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2099 sc->sc_wdcdev.PIO_cap = 4; 2100 sc->sc_wdcdev.DMA_cap = 2; 2101 sc->sc_wdcdev.UDMA_cap = 2; 2102 sc->sc_wdcdev.set_modes = acer_setup_channel; 2103 } 2104 2105 void 2106 acer_setup_chip(sc) 2107 struct pciide_softc *sc; 2108 { 2109 int channel; 2110 2111 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2112 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2113 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2114 2115 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2116 acer_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2117 } 2118 } 2119 2120 void 2121 acer_setup_channel(chp) 2122 struct channel_softc *chp; 2123 { 2124 struct ata_drive_datas *drvp; 2125 int drive; 2126 u_int32_t acer_fifo_udma; 2127 u_int32_t idedma_ctl; 2128 struct pciide_channel *cp = (struct pciide_channel*)chp; 2129 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2130 2131 idedma_ctl = 0; 2132 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2133 WDCDEBUG_PRINT(("acer_setup_chip: old fifo/udma reg 0x%x\n", 2134 acer_fifo_udma), DEBUG_PROBE); 2135 /* setup DMA if needed */ 2136 pciide_channel_dma_setup(cp); 2137 2138 for (drive = 0; drive < 2; drive++) { 2139 drvp = &chp->ch_drive[drive]; 2140 /* If no drive, skip */ 2141 if ((drvp->drive_flags & DRIVE) == 0) 2142 continue; 2143 WDCDEBUG_PRINT(("acer_setup_chip: old timings reg for " 2144 "channel %d drive %d 0x%x\n", chp->channel, drive, 2145 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2146 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2147 /* clear FIFO/DMA mode */ 2148 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2149 ACER_UDMA_EN(chp->channel, drive) | 2150 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2151 2152 /* add timing values, setup DMA if needed */ 2153 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2154 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2155 acer_fifo_udma |= 2156 ACER_FTH_OPL(chp->channel, drive, 0x1); 2157 goto pio; 2158 } 2159 2160 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2161 if (drvp->drive_flags & DRIVE_UDMA) { 2162 /* use Ultra/DMA */ 2163 drvp->drive_flags &= ~DRIVE_DMA; 2164 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2165 acer_fifo_udma |= 2166 ACER_UDMA_TIM(chp->channel, drive, 2167 acer_udma[drvp->UDMA_mode]); 2168 } else { 2169 /* 2170 * use Multiword DMA 2171 * Timings will be used for both PIO and DMA, 2172 * so adjust DMA mode if needed 2173 */ 2174 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2175 drvp->PIO_mode = drvp->DMA_mode + 2; 2176 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2177 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2178 drvp->PIO_mode - 2 : 0; 2179 if (drvp->DMA_mode == 0) 2180 drvp->PIO_mode = 0; 2181 } 2182 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2183 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2184 ACER_IDETIM(chp->channel, drive), 2185 acer_pio[drvp->PIO_mode]); 2186 } 2187 WDCDEBUG_PRINT(("acer_setup_chip: new fifo/udma reg 0x%x\n", 2188 acer_fifo_udma), DEBUG_PROBE); 2189 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2190 if (idedma_ctl != 0) { 2191 /* Add software bits in status register */ 2192 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2193 IDEDMA_CTL, idedma_ctl); 2194 } 2195 pciide_print_modes(cp); 2196 } 2197 2198 void 2199 acer_channel_map(pa, cp) 2200 struct pci_attach_args *pa; 2201 struct pciide_channel *cp; 2202 { 2203 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2204 bus_size_t cmdsize, ctlsize; 2205 struct channel_softc *wdc_cp = &cp->wdc_channel; 2206 u_int32_t cr; 2207 int interface; 2208 2209 /* 2210 * Enable "microsoft register bits" R/W. Will be done 2 times 2211 * (one for each channel) but should'nt be a problem. There's no 2212 * better place where to put this. 2213 */ 2214 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2215 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2216 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2217 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2218 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2219 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2220 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2221 ~ACER_CHANSTATUSREGS_RO); 2222 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2223 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2224 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2225 /* Don't use cr, re-read the real register content instead */ 2226 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2227 PCI_CLASS_REG)); 2228 2229 if ((interface & PCIIDE_CHAN_EN(wdc_cp->channel)) == 0) { 2230 printf("%s: %s channel ignored (disabled)\n", 2231 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2232 return; 2233 } 2234 2235 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize); 2236 if (cp->hw_ok == 0) 2237 return; 2238 if (pciiide_chan_candisable(cp)) { 2239 cr &= ~(PCIIDE_CHAN_EN(wdc_cp->channel) << PCI_INTERFACE_SHIFT); 2240 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2241 } 2242 pciide_map_compat_intr(pa, cp, wdc_cp->channel, interface); 2243 } 2244