1 /* $NetBSD: pci.c,v 1.143 2012/10/20 06:04:01 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.143 2012/10/20 06:04:01 matt Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/module.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <net/if.h> 54 55 #include "locators.h" 56 57 static bool pci_child_register(device_t); 58 59 #ifdef PCI_CONFIG_DUMP 60 int pci_config_dump = 1; 61 #else 62 int pci_config_dump = 0; 63 #endif 64 65 int pciprint(void *, const char *); 66 67 #ifdef PCI_MACHDEP_ENUMERATE_BUS 68 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 69 #else 70 int pci_enumerate_bus(struct pci_softc *, const int *, 71 int (*)(const struct pci_attach_args *), struct pci_attach_args *); 72 #endif 73 74 /* 75 * Important note about PCI-ISA bridges: 76 * 77 * Callbacks are used to configure these devices so that ISA/EISA bridges 78 * can attach their child busses after PCI configuration is done. 79 * 80 * This works because: 81 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 82 * (2) any ISA/EISA bridges must be attached to primary PCI 83 * busses (i.e. bus zero). 84 * 85 * That boils down to: there can only be one of these outstanding 86 * at a time, it is cleared when configuring PCI bus 0 before any 87 * subdevices have been found, and it is run after all subdevices 88 * of PCI bus 0 have been found. 89 * 90 * This is needed because there are some (legacy) PCI devices which 91 * can show up as ISA/EISA devices as well (the prime example of which 92 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 93 * and the bridge is seen before the video board is, the board can show 94 * up as an ISA device, and that can (bogusly) complicate the PCI device's 95 * attach code, or make the PCI device not be properly attached at all. 96 * 97 * We use the generic config_defer() facility to achieve this. 98 */ 99 100 int 101 pcirescan(device_t self, const char *ifattr, const int *locators) 102 { 103 struct pci_softc *sc = device_private(self); 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus(sc, locators, NULL, NULL); 109 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return 0; 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return 0; 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return 1; 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 sc->sc_dev = self; 146 147 pci_attach_hook(parent, self, pba); 148 149 aprint_naive("\n"); 150 aprint_normal("\n"); 151 152 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 153 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 154 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 155 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 156 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 157 158 if (io_enabled == 0 && mem_enabled == 0) { 159 aprint_error_dev(self, "no spaces enabled!\n"); 160 goto fail; 161 } 162 163 #define PRINT(str) \ 164 do { \ 165 aprint_verbose("%s%s", sep, str); \ 166 sep = ", "; \ 167 } while (/*CONSTCOND*/0) 168 169 aprint_verbose_dev(self, ""); 170 171 if (io_enabled) 172 PRINT("i/o space"); 173 if (mem_enabled) 174 PRINT("memory space"); 175 aprint_verbose(" enabled"); 176 177 if (mrl_enabled || mrm_enabled || mwi_enabled) { 178 if (mrl_enabled) 179 PRINT("rd/line"); 180 if (mrm_enabled) 181 PRINT("rd/mult"); 182 if (mwi_enabled) 183 PRINT("wr/inv"); 184 aprint_verbose(" ok"); 185 } 186 187 aprint_verbose("\n"); 188 189 #undef PRINT 190 191 sc->sc_iot = pba->pba_iot; 192 sc->sc_memt = pba->pba_memt; 193 sc->sc_dmat = pba->pba_dmat; 194 sc->sc_dmat64 = pba->pba_dmat64; 195 sc->sc_pc = pba->pba_pc; 196 sc->sc_bus = pba->pba_bus; 197 sc->sc_bridgetag = pba->pba_bridgetag; 198 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 199 sc->sc_intrswiz = pba->pba_intrswiz; 200 sc->sc_intrtag = pba->pba_intrtag; 201 sc->sc_flags = pba->pba_flags; 202 203 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 204 205 pcirescan(sc->sc_dev, "pci", wildcard); 206 207 fail: 208 if (!pmf_device_register(self, NULL, NULL)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 } 211 212 int 213 pcidetach(device_t self, int flags) 214 { 215 int rc; 216 217 if ((rc = config_detach_children(self, flags)) != 0) 218 return rc; 219 pmf_device_deregister(self); 220 return 0; 221 } 222 223 int 224 pciprint(void *aux, const char *pnp) 225 { 226 struct pci_attach_args *pa = aux; 227 char devinfo[256]; 228 const struct pci_quirkdata *qd; 229 230 if (pnp) { 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 aprint_normal("%s at %s", devinfo, pnp); 233 } 234 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 235 if (pci_config_dump) { 236 printf(": "); 237 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 238 if (!pnp) 239 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 240 printf("%s at %s", devinfo, pnp ? pnp : "?"); 241 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 242 #ifdef __i386__ 243 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 244 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 245 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 246 #else 247 printf("intrswiz %#lx, intrpin %#lx", 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #endif 250 printf(", i/o %s, mem %s,", 251 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 252 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 253 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 254 PCI_PRODUCT(pa->pa_id)); 255 if (qd == NULL) { 256 printf(" no quirks"); 257 } else { 258 snprintb(devinfo, sizeof (devinfo), 259 "\002\001multifn\002singlefn\003skipfunc0" 260 "\004skipfunc1\005skipfunc2\006skipfunc3" 261 "\007skipfunc4\010skipfunc5\011skipfunc6" 262 "\012skipfunc7", qd->quirks); 263 printf(" quirks %s", devinfo); 264 } 265 printf(")"); 266 } 267 return UNCONF; 268 } 269 270 int 271 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 272 int (*match)(const struct pci_attach_args *), 273 struct pci_attach_args *pap) 274 { 275 pci_chipset_tag_t pc = sc->sc_pc; 276 struct pci_attach_args pa; 277 pcireg_t id, csr, class, intr, bhlcr, bar, endbar; 278 int ret, pin, bus, device, function, i, width; 279 int locs[PCICF_NLOCS]; 280 281 pci_decompose_tag(pc, tag, &bus, &device, &function); 282 283 /* a driver already attached? */ 284 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 285 return 0; 286 287 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 288 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 289 return 0; 290 291 id = pci_conf_read(pc, tag, PCI_ID_REG); 292 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 293 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 294 295 /* Invalid vendor ID value? */ 296 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 297 return 0; 298 /* XXX Not invalid, but we've done this ~forever. */ 299 if (PCI_VENDOR(id) == 0) 300 return 0; 301 302 /* Collect memory range info */ 303 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 304 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 305 i = 0; 306 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 307 case PCI_HDRTYPE_PPB: 308 endbar = PCI_MAPREG_PPB_END; 309 break; 310 case PCI_HDRTYPE_PCB: 311 endbar = PCI_MAPREG_PCB_END; 312 break; 313 default: 314 endbar = PCI_MAPREG_END; 315 break; 316 } 317 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 318 struct pci_range *r; 319 pcireg_t type; 320 321 width = 4; 322 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 323 continue; 324 325 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 326 if (PCI_MAPREG_MEM_TYPE(type) == 327 PCI_MAPREG_MEM_TYPE_64BIT) 328 width = 8; 329 330 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 331 if (pci_mapreg_info(pc, tag, bar, type, 332 &r->r_offset, &r->r_size, &r->r_flags) != 0) 333 break; 334 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 335 && (r->r_size == 0x1000000)) { 336 struct pci_range *nr; 337 /* 338 * this has to be a mach64 339 * split things up so each half-aperture can 340 * be mapped PREFETCHABLE except the last page 341 * which may contain registers 342 */ 343 r->r_size = 0x7ff000; 344 r->r_flags = BUS_SPACE_MAP_LINEAR | 345 BUS_SPACE_MAP_PREFETCHABLE; 346 nr = &sc->PCI_SC_DEVICESC(device, 347 function).c_range[i++]; 348 nr->r_offset = r->r_offset + 0x800000; 349 nr->r_size = 0x7ff000; 350 nr->r_flags = BUS_SPACE_MAP_LINEAR | 351 BUS_SPACE_MAP_PREFETCHABLE; 352 } 353 354 } 355 } 356 357 pa.pa_iot = sc->sc_iot; 358 pa.pa_memt = sc->sc_memt; 359 pa.pa_dmat = sc->sc_dmat; 360 pa.pa_dmat64 = sc->sc_dmat64; 361 pa.pa_pc = pc; 362 pa.pa_bus = bus; 363 pa.pa_device = device; 364 pa.pa_function = function; 365 pa.pa_tag = tag; 366 pa.pa_id = id; 367 pa.pa_class = class; 368 369 /* 370 * Set up memory, I/O enable, and PCI command flags 371 * as appropriate. 372 */ 373 pa.pa_flags = sc->sc_flags; 374 375 /* 376 * If the cache line size is not configured, then 377 * clear the MRL/MRM/MWI command-ok flags. 378 */ 379 if (PCI_CACHELINE(bhlcr) == 0) { 380 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 381 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 382 } 383 384 if (sc->sc_bridgetag == NULL) { 385 pa.pa_intrswiz = 0; 386 pa.pa_intrtag = tag; 387 } else { 388 pa.pa_intrswiz = sc->sc_intrswiz + device; 389 pa.pa_intrtag = sc->sc_intrtag; 390 } 391 392 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 393 394 pin = PCI_INTERRUPT_PIN(intr); 395 pa.pa_rawintrpin = pin; 396 if (pin == PCI_INTERRUPT_PIN_NONE) { 397 /* no interrupt */ 398 pa.pa_intrpin = 0; 399 } else { 400 /* 401 * swizzle it based on the number of busses we're 402 * behind and our device number. 403 */ 404 pa.pa_intrpin = /* XXX */ 405 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 406 } 407 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 408 409 if (match != NULL) { 410 ret = (*match)(&pa); 411 if (ret != 0 && pap != NULL) 412 *pap = pa; 413 } else { 414 struct pci_child *c; 415 locs[PCICF_DEV] = device; 416 locs[PCICF_FUNCTION] = function; 417 418 c = &sc->PCI_SC_DEVICESC(device, function); 419 pci_conf_capture(pc, tag, &c->c_conf); 420 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 421 c->c_psok = true; 422 else 423 c->c_psok = false; 424 425 c->c_dev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 426 pciprint, config_stdsubmatch); 427 428 ret = (c->c_dev != NULL); 429 } 430 431 return ret; 432 } 433 434 void 435 pcidevdetached(device_t self, device_t child) 436 { 437 struct pci_softc *sc = device_private(self); 438 int d, f; 439 pcitag_t tag; 440 struct pci_child *c; 441 442 d = device_locator(child, PCICF_DEV); 443 f = device_locator(child, PCICF_FUNCTION); 444 445 c = &sc->PCI_SC_DEVICESC(d, f); 446 447 KASSERT(c->c_dev == child); 448 449 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 450 if (c->c_psok) 451 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 452 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 453 c->c_dev = NULL; 454 } 455 456 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 457 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 458 DVF_DETACH_SHUTDOWN); 459 460 int 461 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 462 int *offset, pcireg_t *value) 463 { 464 pcireg_t reg; 465 unsigned int ofs; 466 467 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 468 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 469 return 0; 470 471 /* Determine the Capability List Pointer register to start with. */ 472 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 473 switch (PCI_HDRTYPE_TYPE(reg)) { 474 case 0: /* standard device header */ 475 case 1: /* PCI-PCI bridge header */ 476 ofs = PCI_CAPLISTPTR_REG; 477 break; 478 case 2: /* PCI-CardBus Bridge header */ 479 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 480 break; 481 default: 482 return 0; 483 } 484 485 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 486 while (ofs != 0) { 487 if ((ofs & 3) || (ofs < 0x40)) { 488 int bus, device, function; 489 490 pci_decompose_tag(pc, tag, &bus, &device, &function); 491 492 printf("Skipping broken PCI header on %d:%d:%d\n", 493 bus, device, function); 494 break; 495 } 496 reg = pci_conf_read(pc, tag, ofs); 497 if (PCI_CAPLIST_CAP(reg) == capid) { 498 if (offset) 499 *offset = ofs; 500 if (value) 501 *value = reg; 502 return 1; 503 } 504 ofs = PCI_CAPLIST_NEXT(reg); 505 } 506 507 return 0; 508 } 509 510 int 511 pci_find_device(struct pci_attach_args *pa, 512 int (*match)(const struct pci_attach_args *)) 513 { 514 extern struct cfdriver pci_cd; 515 device_t pcidev; 516 int i; 517 static const int wildcard[2] = { 518 PCICF_DEV_DEFAULT, 519 PCICF_FUNCTION_DEFAULT 520 }; 521 522 for (i = 0; i < pci_cd.cd_ndevs; i++) { 523 pcidev = device_lookup(&pci_cd, i); 524 if (pcidev != NULL && 525 pci_enumerate_bus(device_private(pcidev), wildcard, 526 match, pa) != 0) 527 return 1; 528 } 529 return 0; 530 } 531 532 #ifndef PCI_MACHDEP_ENUMERATE_BUS 533 /* 534 * Generic PCI bus enumeration routine. Used unless machine-dependent 535 * code needs to provide something else. 536 */ 537 int 538 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 539 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 540 { 541 pci_chipset_tag_t pc = sc->sc_pc; 542 int device, function, nfunctions, ret; 543 const struct pci_quirkdata *qd; 544 pcireg_t id, bhlcr; 545 pcitag_t tag; 546 uint8_t devs[32]; 547 int i, n; 548 549 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 550 for (i = 0; i < n; i++) { 551 device = devs[i]; 552 553 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 554 (locators[PCICF_DEV] != device)) 555 continue; 556 557 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 558 559 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 560 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 561 continue; 562 563 id = pci_conf_read(pc, tag, PCI_ID_REG); 564 565 /* Invalid vendor ID value? */ 566 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 567 continue; 568 /* XXX Not invalid, but we've done this ~forever. */ 569 if (PCI_VENDOR(id) == 0) 570 continue; 571 572 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 573 574 if (qd != NULL && 575 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 576 nfunctions = 8; 577 else if (qd != NULL && 578 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 579 nfunctions = 1; 580 else 581 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 582 583 #ifdef __PCI_DEV_FUNCORDER 584 char funcs[8]; 585 int j; 586 for (j = 0; j < nfunctions; j++) { 587 funcs[j] = j; 588 } 589 if (j < __arraycount(funcs)) 590 funcs[j] = -1; 591 if (nfunctions > 1) { 592 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 593 nfunctions, funcs); 594 } 595 for (j = 0; 596 j < 8 && (function = funcs[j]) < 8 && function >= 0; 597 j++) { 598 #else 599 for (function = 0; function < nfunctions; function++) { 600 #endif 601 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 602 && (locators[PCICF_FUNCTION] != function)) 603 continue; 604 605 if (qd != NULL && 606 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 607 continue; 608 tag = pci_make_tag(pc, sc->sc_bus, device, function); 609 ret = pci_probe_device(sc, tag, match, pap); 610 if (match != NULL && ret != 0) 611 return ret; 612 } 613 } 614 return 0; 615 } 616 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 617 618 619 /* 620 * Vital Product Data (PCI 2.2) 621 */ 622 623 int 624 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 625 pcireg_t *data) 626 { 627 uint32_t reg; 628 int ofs, i, j; 629 630 KASSERT(data != NULL); 631 KASSERT((offset + count) < 0x7fff); 632 633 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 634 return 1; 635 636 for (i = 0; i < count; offset += sizeof(*data), i++) { 637 reg &= 0x0000ffff; 638 reg &= ~PCI_VPD_OPFLAG; 639 reg |= PCI_VPD_ADDRESS(offset); 640 pci_conf_write(pc, tag, ofs, reg); 641 642 /* 643 * PCI 2.2 does not specify how long we should poll 644 * for completion nor whether the operation can fail. 645 */ 646 j = 0; 647 do { 648 if (j++ == 20) 649 return 1; 650 delay(4); 651 reg = pci_conf_read(pc, tag, ofs); 652 } while ((reg & PCI_VPD_OPFLAG) == 0); 653 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 654 } 655 656 return 0; 657 } 658 659 int 660 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 661 pcireg_t *data) 662 { 663 pcireg_t reg; 664 int ofs, i, j; 665 666 KASSERT(data != NULL); 667 KASSERT((offset + count) < 0x7fff); 668 669 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 670 return 1; 671 672 for (i = 0; i < count; offset += sizeof(*data), i++) { 673 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 674 675 reg &= 0x0000ffff; 676 reg |= PCI_VPD_OPFLAG; 677 reg |= PCI_VPD_ADDRESS(offset); 678 pci_conf_write(pc, tag, ofs, reg); 679 680 /* 681 * PCI 2.2 does not specify how long we should poll 682 * for completion nor whether the operation can fail. 683 */ 684 j = 0; 685 do { 686 if (j++ == 20) 687 return 1; 688 delay(1); 689 reg = pci_conf_read(pc, tag, ofs); 690 } while (reg & PCI_VPD_OPFLAG); 691 } 692 693 return 0; 694 } 695 696 int 697 pci_dma64_available(const struct pci_attach_args *pa) 698 { 699 #ifdef _PCI_HAVE_DMA64 700 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 701 return 1; 702 #endif 703 return 0; 704 } 705 706 void 707 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 708 struct pci_conf_state *pcs) 709 { 710 int off; 711 712 for (off = 0; off < 16; off++) 713 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 714 715 return; 716 } 717 718 void 719 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 720 struct pci_conf_state *pcs) 721 { 722 int off; 723 pcireg_t val; 724 725 for (off = 15; off >= 0; off--) { 726 val = pci_conf_read(pc, tag, (off * 4)); 727 if (val != pcs->reg[off]) 728 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 729 } 730 731 return; 732 } 733 734 /* 735 * Power Management Capability (Rev 2.2) 736 */ 737 static int 738 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 739 int offset) 740 { 741 pcireg_t value, now; 742 743 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 744 now = value & PCI_PMCSR_STATE_MASK; 745 switch (now) { 746 case PCI_PMCSR_STATE_D0: 747 case PCI_PMCSR_STATE_D1: 748 case PCI_PMCSR_STATE_D2: 749 case PCI_PMCSR_STATE_D3: 750 *state = now; 751 return 0; 752 default: 753 return EINVAL; 754 } 755 } 756 757 int 758 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 759 { 760 int offset; 761 pcireg_t value; 762 763 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 764 return EOPNOTSUPP; 765 766 return pci_get_powerstate_int(pc, tag, state, offset); 767 } 768 769 static int 770 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 771 int offset, pcireg_t cap_reg) 772 { 773 pcireg_t value, cap, now; 774 775 cap = cap_reg >> PCI_PMCR_SHIFT; 776 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 777 now = value & PCI_PMCSR_STATE_MASK; 778 value &= ~PCI_PMCSR_STATE_MASK; 779 780 if (now == state) 781 return 0; 782 switch (state) { 783 case PCI_PMCSR_STATE_D0: 784 break; 785 case PCI_PMCSR_STATE_D1: 786 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 787 printf("invalid transition from %d to D1\n", (int)now); 788 return EINVAL; 789 } 790 if (!(cap & PCI_PMCR_D1SUPP)) { 791 printf("D1 not supported\n"); 792 return EOPNOTSUPP; 793 } 794 break; 795 case PCI_PMCSR_STATE_D2: 796 if (now == PCI_PMCSR_STATE_D3) { 797 printf("invalid transition from %d to D2\n", (int)now); 798 return EINVAL; 799 } 800 if (!(cap & PCI_PMCR_D2SUPP)) { 801 printf("D2 not supported\n"); 802 return EOPNOTSUPP; 803 } 804 break; 805 case PCI_PMCSR_STATE_D3: 806 break; 807 default: 808 return EINVAL; 809 } 810 value |= state; 811 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 812 /* delay according to pcipm1.2, ch. 5.6.1 */ 813 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 814 DELAY(10000); 815 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 816 DELAY(200); 817 818 return 0; 819 } 820 821 int 822 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 823 { 824 int offset; 825 pcireg_t value; 826 827 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 828 printf("pci_set_powerstate not supported\n"); 829 return EOPNOTSUPP; 830 } 831 832 return pci_set_powerstate_int(pc, tag, state, offset, value); 833 } 834 835 int 836 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 837 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 838 { 839 pcireg_t pmode; 840 int error; 841 842 if ((error = pci_get_powerstate(pc, tag, &pmode))) 843 return error; 844 845 switch (pmode) { 846 case PCI_PMCSR_STATE_D0: 847 break; 848 case PCI_PMCSR_STATE_D3: 849 if (wakefun == NULL) { 850 /* 851 * The card has lost all configuration data in 852 * this state, so punt. 853 */ 854 aprint_error_dev(dev, 855 "unable to wake up from power state D3\n"); 856 return EOPNOTSUPP; 857 } 858 /*FALLTHROUGH*/ 859 default: 860 if (wakefun) { 861 error = (*wakefun)(pc, tag, dev, pmode); 862 if (error) 863 return error; 864 } 865 aprint_normal_dev(dev, "waking up from power state D%d\n", 866 pmode); 867 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 868 return error; 869 } 870 return 0; 871 } 872 873 int 874 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 875 device_t dev, pcireg_t state) 876 { 877 return 0; 878 } 879 880 struct pci_child_power { 881 struct pci_conf_state p_pciconf; 882 pci_chipset_tag_t p_pc; 883 pcitag_t p_tag; 884 bool p_has_pm; 885 int p_pm_offset; 886 pcireg_t p_pm_cap; 887 pcireg_t p_class; 888 pcireg_t p_csr; 889 }; 890 891 static bool 892 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 893 { 894 struct pci_child_power *priv = device_pmf_bus_private(dv); 895 pcireg_t ocsr, csr; 896 897 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 898 899 if (!priv->p_has_pm) 900 return true; /* ??? hopefully handled by ACPI */ 901 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 902 return true; /* XXX */ 903 904 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 905 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 906 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 907 | PCI_COMMAND_MASTER_ENABLE); 908 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 909 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 910 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 911 pci_conf_write(priv->p_pc, priv->p_tag, 912 PCI_COMMAND_STATUS_REG, ocsr); 913 aprint_error_dev(dv, "unsupported state, continuing.\n"); 914 return false; 915 } 916 return true; 917 } 918 919 static bool 920 pci_child_resume(device_t dv, const pmf_qual_t *qual) 921 { 922 struct pci_child_power *priv = device_pmf_bus_private(dv); 923 924 if (priv->p_has_pm && 925 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 926 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 927 aprint_error_dev(dv, "unsupported state, continuing.\n"); 928 return false; 929 } 930 931 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 932 933 return true; 934 } 935 936 static bool 937 pci_child_shutdown(device_t dv, int how) 938 { 939 struct pci_child_power *priv = device_pmf_bus_private(dv); 940 pcireg_t csr; 941 942 /* restore original bus-mastering state */ 943 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 944 csr &= ~PCI_COMMAND_MASTER_ENABLE; 945 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 946 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 947 return true; 948 } 949 950 static void 951 pci_child_deregister(device_t dv) 952 { 953 struct pci_child_power *priv = device_pmf_bus_private(dv); 954 955 free(priv, M_DEVBUF); 956 } 957 958 static bool 959 pci_child_register(device_t child) 960 { 961 device_t self = device_parent(child); 962 struct pci_softc *sc = device_private(self); 963 struct pci_child_power *priv; 964 int device, function, off; 965 pcireg_t reg; 966 967 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 968 969 device = device_locator(child, PCICF_DEV); 970 function = device_locator(child, PCICF_FUNCTION); 971 972 priv->p_pc = sc->sc_pc; 973 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 974 function); 975 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 976 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 977 PCI_COMMAND_STATUS_REG); 978 979 if (pci_get_capability(priv->p_pc, priv->p_tag, 980 PCI_CAP_PWRMGMT, &off, ®)) { 981 priv->p_has_pm = true; 982 priv->p_pm_offset = off; 983 priv->p_pm_cap = reg; 984 } else { 985 priv->p_has_pm = false; 986 priv->p_pm_offset = -1; 987 } 988 989 device_pmf_bus_register(child, priv, pci_child_suspend, 990 pci_child_resume, pci_child_shutdown, pci_child_deregister); 991 992 return true; 993 } 994 995 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 996 997 static int 998 pci_modcmd(modcmd_t cmd, void *priv) 999 { 1000 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1001 return 0; 1002 return ENOTTY; 1003 } 1004