1 /* $NetBSD: if_txp.c,v 1.71 2020/03/09 01:55:16 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.71 2020/03/09 01:55:16 thorpej Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 #include <sys/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 #include <net/if_media.h> 56 #include <net/bpf.h> 57 58 #ifdef INET 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/pci/if_txpreg.h> 73 74 #include <dev/microcode/typhoon/3c990img.h> 75 76 /* 77 * These currently break the 3c990 firmware, hopefully will be resolved 78 * at some point. 79 */ 80 #undef TRY_TX_UDP_CSUM 81 #undef TRY_TX_TCP_CSUM 82 83 static int txp_probe(device_t, cfdata_t, void *); 84 static void txp_attach(device_t, device_t, void *); 85 static int txp_intr(void *); 86 static void txp_tick(void *); 87 static bool txp_shutdown(device_t, int); 88 static int txp_ioctl(struct ifnet *, u_long, void *); 89 static void txp_start(struct ifnet *); 90 static void txp_stop(struct txp_softc *); 91 static void txp_init(struct txp_softc *); 92 static void txp_watchdog(struct ifnet *); 93 94 static int txp_chip_init(struct txp_softc *); 95 static int txp_reset_adapter(struct txp_softc *); 96 static int txp_download_fw(struct txp_softc *); 97 static int txp_download_fw_wait(struct txp_softc *); 98 static int txp_download_fw_section(struct txp_softc *, 99 const struct txp_fw_section_header *, int); 100 static int txp_alloc_rings(struct txp_softc *); 101 static void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 102 static int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 103 static void txp_set_filter(struct txp_softc *); 104 105 static int txp_cmd_desc_numfree(struct txp_softc *); 106 static int txp_command(struct txp_softc *, uint16_t, uint16_t, uint32_t, 107 uint32_t, uint16_t *, uint32_t *, uint32_t *, int); 108 static int txp_command2(struct txp_softc *, uint16_t, uint16_t, 109 uint32_t, uint32_t, struct txp_ext_desc *, uint8_t, 110 struct txp_rsp_desc **, int); 111 static int txp_response(struct txp_softc *, uint32_t, uint16_t, uint16_t, 112 struct txp_rsp_desc **); 113 static void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 114 struct txp_rsp_desc *); 115 static void txp_capabilities(struct txp_softc *); 116 117 static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 static int txp_ifmedia_upd(struct ifnet *); 119 static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 120 struct txp_dma_alloc *); 121 static void txp_rxbuf_reclaim(struct txp_softc *); 122 static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 123 struct txp_dma_alloc *); 124 125 static void txp_rxd_free(struct txp_softc *, struct txp_swdesc *); 126 static struct txp_swdesc *txp_rxd_alloc(struct txp_softc *); 127 128 CFATTACH_DECL_NEW(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 129 NULL, NULL); 130 131 static const struct txp_pci_match { 132 int vid, did, flags; 133 } txp_devices[] = { 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 142 }; 143 144 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 145 146 static const struct { 147 uint16_t mask, value; 148 int flags; 149 } txp_subsysinfo[] = { 150 {0xf000, 0x2000, TXP_SERVERVERSION}, 151 {0x0100, 0x0100, TXP_FIBER}, 152 #if 0 /* information from 3com header, unused */ 153 {0x0010, 0x0010, /* secured firmware */}, 154 {0x0003, 0x0000, /* variable DES */}, 155 {0x0003, 0x0001, /* single DES - "95" */}, 156 {0x0003, 0x0002, /* triple DES - "97" */}, 157 #endif 158 }; 159 160 static const struct txp_pci_match * 161 txp_pcilookup(pcireg_t id) 162 { 163 int i; 164 165 for (i = 0; i < __arraycount(txp_devices); i++) 166 if (PCI_VENDOR(id) == txp_devices[i].vid && 167 PCI_PRODUCT(id) == txp_devices[i].did) 168 return &txp_devices[i]; 169 return (0); 170 } 171 172 static int 173 txp_probe(device_t parent, cfdata_t match, void *aux) 174 { 175 struct pci_attach_args *pa = aux; 176 177 if (txp_pcilookup(pa->pa_id)) 178 return (1); 179 return (0); 180 } 181 182 static void 183 txp_attach(device_t parent, device_t self, void *aux) 184 { 185 struct txp_softc *sc = device_private(self); 186 struct pci_attach_args *pa = aux; 187 pci_chipset_tag_t pc = pa->pa_pc; 188 pci_intr_handle_t ih; 189 const char *intrstr = NULL; 190 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 191 uint32_t command; 192 uint16_t p1; 193 uint32_t p2; 194 u_char enaddr[6]; 195 const struct txp_pci_match *match; 196 uint16_t subsys; 197 int i, flags; 198 char devinfo[256]; 199 char intrbuf[PCI_INTRSTR_LEN]; 200 201 sc->sc_dev = self; 202 sc->sc_cold = 1; 203 204 match = txp_pcilookup(pa->pa_id); 205 flags = match->flags; 206 if (match->flags & TXP_USESUBSYSTEM) { 207 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 208 PCI_SUBSYS_ID_REG)); 209 for (i = 0; 210 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 211 i++) 212 if ((subsys & txp_subsysinfo[i].mask) == 213 txp_subsysinfo[i].value) 214 flags |= txp_subsysinfo[i].flags; 215 } 216 sc->sc_flags = flags; 217 218 aprint_naive("\n"); 219 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 220 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM | TXP_SERVERVERSION)) == \ 221 (TXP_USESUBSYSTEM | TXP_SERVERVERSION) ? " (SVR)" : "") 222 aprint_normal(": %s%s\n%s", devinfo, TXP_EXTRAINFO, 223 device_xname(sc->sc_dev)); 224 225 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 226 227 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 228 aprint_error(": failed to enable bus mastering\n"); 229 return; 230 } 231 232 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 233 aprint_error(": failed to enable memory mapping\n"); 234 return; 235 } 236 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 237 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 238 aprint_error(": can't map mem space %d\n", 0); 239 return; 240 } 241 242 if (pci_dma64_available(pa)) 243 sc->sc_dmat = pa->pa_dmat64; 244 else 245 sc->sc_dmat = pa->pa_dmat; 246 247 /* 248 * Allocate our interrupt. 249 */ 250 if (pci_intr_map(pa, &ih)) { 251 aprint_error(": couldn't map interrupt\n"); 252 return; 253 } 254 255 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 256 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, txp_intr, sc, 257 device_xname(self)); 258 if (sc->sc_ih == NULL) { 259 aprint_error(": couldn't establish interrupt"); 260 if (intrstr != NULL) 261 aprint_normal(" at %s", intrstr); 262 aprint_normal("\n"); 263 return; 264 } 265 aprint_normal(": interrupting at %s\n", intrstr); 266 267 if (txp_chip_init(sc)) 268 goto cleanupintr; 269 270 if (txp_download_fw(sc)) 271 goto cleanupintr; 272 273 if (txp_alloc_rings(sc)) 274 goto cleanupintr; 275 276 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 277 NULL, NULL, NULL, 1)) 278 goto cleanupintr; 279 280 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 281 &p1, &p2, NULL, 1)) 282 goto cleanupintr; 283 284 p1 = htole16(p1); 285 enaddr[0] = ((uint8_t *)&p1)[1]; 286 enaddr[1] = ((uint8_t *)&p1)[0]; 287 p2 = htole32(p2); 288 enaddr[2] = ((uint8_t *)&p2)[3]; 289 enaddr[3] = ((uint8_t *)&p2)[2]; 290 enaddr[4] = ((uint8_t *)&p2)[1]; 291 enaddr[5] = ((uint8_t *)&p2)[0]; 292 293 aprint_normal_dev(self, "Ethernet address %s\n", 294 ether_sprintf(enaddr)); 295 sc->sc_cold = 0; 296 297 /* Initialize ifmedia structures. */ 298 sc->sc_arpcom.ec_ifmedia = &sc->sc_ifmedia; 299 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 300 if (flags & TXP_FIBER) { 301 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX, 302 0, NULL); 303 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX | IFM_FDX, 304 0, NULL); 305 } else { 306 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 307 0, NULL); 308 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 309 0, NULL); 310 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 311 0, NULL); 312 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 313 0, NULL); 314 } 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 316 317 sc->sc_xcvr = TXP_XCVR_AUTO; 318 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 319 NULL, NULL, NULL, 0); 320 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 321 322 ifp->if_softc = sc; 323 ifp->if_mtu = ETHERMTU; 324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 325 ifp->if_ioctl = txp_ioctl; 326 ifp->if_start = txp_start; 327 ifp->if_watchdog = txp_watchdog; 328 ifp->if_baudrate = 10000000; 329 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 330 IFQ_SET_READY(&ifp->if_snd); 331 ifp->if_capabilities = 0; 332 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 333 334 txp_capabilities(sc); 335 336 callout_init(&sc->sc_tick, 0); 337 callout_setfunc(&sc->sc_tick, txp_tick, sc); 338 339 /* 340 * Attach us everywhere 341 */ 342 if_attach(ifp); 343 if_deferred_start_init(ifp, NULL); 344 ether_ifattach(ifp, enaddr); 345 346 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 347 pmf_class_network_register(self, ifp); 348 else 349 aprint_error_dev(self, "couldn't establish power handler\n"); 350 351 return; 352 353 cleanupintr: 354 pci_intr_disestablish(pc, sc->sc_ih); 355 356 return; 357 358 } 359 360 static int 361 txp_chip_init(struct txp_softc *sc) 362 { 363 /* disable interrupts */ 364 WRITE_REG(sc, TXP_IER, 0); 365 WRITE_REG(sc, TXP_IMR, 366 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 367 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 368 TXP_INT_LATCH); 369 370 /* ack all interrupts */ 371 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 372 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 373 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 374 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 375 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 376 377 if (txp_reset_adapter(sc)) 378 return (-1); 379 380 /* disable interrupts */ 381 WRITE_REG(sc, TXP_IER, 0); 382 WRITE_REG(sc, TXP_IMR, 383 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 384 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 385 TXP_INT_LATCH); 386 387 /* ack all interrupts */ 388 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 389 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 390 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 391 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 392 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 393 394 return (0); 395 } 396 397 static int 398 txp_reset_adapter(struct txp_softc *sc) 399 { 400 uint32_t r; 401 int i; 402 403 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 404 DELAY(1000); 405 WRITE_REG(sc, TXP_SRR, 0); 406 407 /* Should wait max 6 seconds */ 408 for (i = 0; i < 6000; i++) { 409 r = READ_REG(sc, TXP_A2H_0); 410 if (r == STAT_WAITING_FOR_HOST_REQUEST) 411 break; 412 DELAY(1000); 413 } 414 415 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 416 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 417 return (-1); 418 } 419 420 return (0); 421 } 422 423 static int 424 txp_download_fw(struct txp_softc *sc) 425 { 426 const struct txp_fw_file_header *fileheader; 427 const struct txp_fw_section_header *secthead; 428 int sect; 429 uint32_t r, i, ier, imr; 430 431 ier = READ_REG(sc, TXP_IER); 432 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 433 434 imr = READ_REG(sc, TXP_IMR); 435 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 436 437 for (i = 0; i < 10000; i++) { 438 r = READ_REG(sc, TXP_A2H_0); 439 if (r == STAT_WAITING_FOR_HOST_REQUEST) 440 break; 441 DELAY(50); 442 } 443 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 444 printf(": not waiting for host request\n"); 445 return (-1); 446 } 447 448 /* Ack the status */ 449 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 450 451 fileheader = (const struct txp_fw_file_header *)tc990image; 452 if (memcmp("TYPHOON", fileheader->magicid, 453 sizeof(fileheader->magicid))) { 454 printf(": fw invalid magic\n"); 455 return (-1); 456 } 457 458 /* Tell boot firmware to get ready for image */ 459 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 460 WRITE_REG(sc, TXP_H2A_2, le32toh(fileheader->hmac[0])); 461 WRITE_REG(sc, TXP_H2A_3, le32toh(fileheader->hmac[1])); 462 WRITE_REG(sc, TXP_H2A_4, le32toh(fileheader->hmac[2])); 463 WRITE_REG(sc, TXP_H2A_5, le32toh(fileheader->hmac[3])); 464 WRITE_REG(sc, TXP_H2A_6, le32toh(fileheader->hmac[4])); 465 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 466 467 if (txp_download_fw_wait(sc)) { 468 printf("%s: fw wait failed, initial\n", 469 device_xname(sc->sc_dev)); 470 return (-1); 471 } 472 473 secthead = (const struct txp_fw_section_header *) 474 (((const uint8_t *)tc990image) + 475 sizeof(struct txp_fw_file_header)); 476 477 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 478 if (txp_download_fw_section(sc, secthead, sect)) 479 return (-1); 480 secthead = (const struct txp_fw_section_header *) 481 (((const uint8_t *)secthead) + le32toh(secthead->nbytes) + 482 sizeof(*secthead)); 483 } 484 485 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 486 487 for (i = 0; i < 10000; i++) { 488 r = READ_REG(sc, TXP_A2H_0); 489 if (r == STAT_WAITING_FOR_BOOT) 490 break; 491 DELAY(50); 492 } 493 if (r != STAT_WAITING_FOR_BOOT) { 494 printf(": not waiting for boot\n"); 495 return (-1); 496 } 497 498 WRITE_REG(sc, TXP_IER, ier); 499 WRITE_REG(sc, TXP_IMR, imr); 500 501 return (0); 502 } 503 504 static int 505 txp_download_fw_wait(struct txp_softc *sc) 506 { 507 uint32_t i, r; 508 509 for (i = 0; i < 10000; i++) { 510 r = READ_REG(sc, TXP_ISR); 511 if (r & TXP_INT_A2H_0) 512 break; 513 DELAY(50); 514 } 515 516 if (!(r & TXP_INT_A2H_0)) { 517 printf(": fw wait failed comm0\n"); 518 return (-1); 519 } 520 521 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 522 523 r = READ_REG(sc, TXP_A2H_0); 524 if (r != STAT_WAITING_FOR_SEGMENT) { 525 printf(": fw not waiting for segment\n"); 526 return (-1); 527 } 528 return (0); 529 } 530 531 static int 532 txp_download_fw_section(struct txp_softc *sc, 533 const struct txp_fw_section_header *sect, int sectnum) 534 { 535 struct txp_dma_alloc dma; 536 int rseg, err = 0; 537 struct mbuf m; 538 #ifdef INET 539 uint16_t csum; 540 #endif 541 542 /* Skip zero length sections */ 543 if (sect->nbytes == 0) 544 return (0); 545 546 /* Make sure we aren't past the end of the image */ 547 rseg = ((const uint8_t *)sect) - ((const uint8_t *)tc990image); 548 if (rseg >= sizeof(tc990image)) { 549 printf(": fw invalid section address, section %d\n", sectnum); 550 return (-1); 551 } 552 553 /* Make sure this section doesn't go past the end */ 554 rseg += le32toh(sect->nbytes); 555 if (rseg >= sizeof(tc990image)) { 556 printf(": fw truncated section %d\n", sectnum); 557 return (-1); 558 } 559 560 /* map a buffer, copy segment to it, get physaddr */ 561 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 562 printf(": fw dma malloc failed, section %d\n", sectnum); 563 return (-1); 564 } 565 566 memcpy(dma.dma_vaddr, ((const uint8_t *)sect) + sizeof(*sect), 567 le32toh(sect->nbytes)); 568 569 /* 570 * dummy up mbuf and verify section checksum 571 */ 572 m.m_type = MT_DATA; 573 m.m_next = m.m_nextpkt = NULL; 574 m.m_owner = NULL; 575 m.m_len = le32toh(sect->nbytes); 576 m.m_data = dma.dma_vaddr; 577 m.m_flags = 0; 578 #ifdef INET 579 csum = in_cksum(&m, le32toh(sect->nbytes)); 580 if (csum != sect->cksum) { 581 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 582 sectnum, sect->cksum, csum); 583 txp_dma_free(sc, &dma); 584 return -1; 585 } 586 #endif 587 588 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 589 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 590 591 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 592 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 593 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 594 WRITE_REG(sc, TXP_H2A_4, BUS_ADDR_HI32(dma.dma_paddr)); 595 WRITE_REG(sc, TXP_H2A_5, BUS_ADDR_LO32(dma.dma_paddr)); 596 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 597 598 if (txp_download_fw_wait(sc)) { 599 printf("%s: fw wait failed, section %d\n", 600 device_xname(sc->sc_dev), sectnum); 601 err = -1; 602 } 603 604 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 605 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 606 607 txp_dma_free(sc, &dma); 608 return (err); 609 } 610 611 static int 612 txp_intr(void *vsc) 613 { 614 struct txp_softc *sc = vsc; 615 struct txp_hostvar *hv = sc->sc_hostvar; 616 uint32_t isr; 617 int claimed = 0; 618 619 /* mask all interrupts */ 620 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 621 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 622 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 623 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 624 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 625 626 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 627 sizeof(struct txp_hostvar), 628 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 629 630 isr = READ_REG(sc, TXP_ISR); 631 while (isr) { 632 claimed = 1; 633 WRITE_REG(sc, TXP_ISR, isr); 634 635 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 636 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 637 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 638 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 639 640 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 641 txp_rxbuf_reclaim(sc); 642 643 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 644 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 645 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 646 647 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 648 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 649 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 650 651 isr = READ_REG(sc, TXP_ISR); 652 } 653 654 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 655 sizeof(struct txp_hostvar), 656 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 657 658 /* unmask all interrupts */ 659 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 660 661 if_schedule_deferred_start(&sc->sc_arpcom.ec_if); 662 663 return (claimed); 664 } 665 666 static struct txp_swdesc * 667 txp_rxd_alloc(struct txp_softc *sc) 668 { 669 if (sc->sc_txd_pool_ptr == 0) 670 return NULL; 671 return sc->sc_rxd_pool[--sc->sc_txd_pool_ptr]; 672 } 673 674 static void 675 txp_rxd_free(struct txp_softc *sc, struct txp_swdesc *sd) 676 { 677 KASSERT(sc->sc_txd_pool_ptr < RXBUF_ENTRIES); 678 sc->sc_rxd_pool[sc->sc_txd_pool_ptr++] = sd; 679 } 680 681 static inline uint32_t 682 txp_rxd_idx(struct txp_softc *sc, struct txp_swdesc *sd) 683 { 684 KASSERT(sd >= &sc->sc_rxd[0] && sd < &sc->sc_rxd[RXBUF_ENTRIES]); 685 return (uint32_t)(sd - &sc->sc_rxd[0]); 686 } 687 688 static void 689 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 690 struct txp_dma_alloc *dma) 691 { 692 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 693 struct txp_rx_desc *rxd; 694 struct mbuf *m; 695 struct txp_swdesc *sd; 696 uint32_t roff, woff; 697 int sumflags = 0; 698 int idx; 699 700 roff = le32toh(*r->r_roff); 701 woff = le32toh(*r->r_woff); 702 idx = roff / sizeof(struct txp_rx_desc); 703 rxd = r->r_desc + idx; 704 705 while (roff != woff) { 706 707 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 708 idx * sizeof(struct txp_rx_desc), 709 sizeof(struct txp_rx_desc), BUS_DMASYNC_POSTREAD); 710 711 if (rxd->rx_flags & RX_FLAGS_ERROR) { 712 printf("%s: error 0x%x\n", device_xname(sc->sc_dev), 713 le32toh(rxd->rx_stat)); 714 if_statinc(ifp, if_ierrors); 715 goto next; 716 } 717 718 /* retrieve stashed pointer */ 719 KASSERT(rxd->rx_vaddrlo < RXBUF_ENTRIES); 720 sd = &sc->sc_rxd[rxd->rx_vaddrlo]; 721 722 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 723 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 724 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 725 m = sd->sd_mbuf; 726 txp_rxd_free(sc, sd); 727 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 728 729 #ifdef __STRICT_ALIGNMENT 730 { 731 /* 732 * XXX Nice chip, except it won't accept "off by 2" 733 * buffers, so we're force to copy. Supposedly 734 * this will be fixed in a newer firmware rev 735 * and this will be temporary. 736 */ 737 struct mbuf *mnew; 738 739 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 740 if (mnew == NULL) { 741 m_freem(m); 742 goto next; 743 } 744 if (m->m_len > (MHLEN - 2)) { 745 MCLGET(mnew, M_DONTWAIT); 746 if (!(mnew->m_flags & M_EXT)) { 747 m_freem(mnew); 748 m_freem(m); 749 goto next; 750 } 751 } 752 m_set_rcvif(mnew, ifp); 753 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 754 mnew->m_data += 2; 755 memcpy(mnew->m_data, m->m_data, m->m_len); 756 m_freem(m); 757 m = mnew; 758 } 759 #endif 760 761 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 762 sumflags |= (M_CSUM_IPv4 | M_CSUM_IPv4_BAD); 763 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 764 sumflags |= M_CSUM_IPv4; 765 766 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 767 sumflags |= (M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD); 768 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 769 sumflags |= M_CSUM_TCPv4; 770 771 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 772 sumflags |= (M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD); 773 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 774 sumflags |= M_CSUM_UDPv4; 775 776 m->m_pkthdr.csum_flags = sumflags; 777 778 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 779 vlan_set_tag(m, htons(rxd->rx_vlan >> 16)); 780 } 781 782 if_percpuq_enqueue(ifp->if_percpuq, m); 783 784 next: 785 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 786 idx * sizeof(struct txp_rx_desc), 787 sizeof(struct txp_rx_desc), BUS_DMASYNC_PREREAD); 788 789 roff += sizeof(struct txp_rx_desc); 790 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 791 idx = 0; 792 roff = 0; 793 rxd = r->r_desc; 794 } else { 795 idx++; 796 rxd++; 797 } 798 woff = le32toh(*r->r_woff); 799 } 800 801 *r->r_roff = htole32(woff); 802 } 803 804 static void 805 txp_rxbuf_reclaim(struct txp_softc *sc) 806 { 807 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 808 struct txp_hostvar *hv = sc->sc_hostvar; 809 struct txp_rxbuf_desc *rbd; 810 struct txp_swdesc *sd; 811 uint32_t i, end; 812 813 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 814 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 815 816 if (++i == RXBUF_ENTRIES) 817 i = 0; 818 819 rbd = sc->sc_rxbufs + i; 820 821 while (i != end) { 822 sd = txp_rxd_alloc(sc); 823 if (sd == NULL) 824 break; 825 826 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 827 if (sd->sd_mbuf == NULL) 828 goto err_sd; 829 830 MCLGET(sd->sd_mbuf, M_DONTWAIT); 831 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 832 goto err_mbuf; 833 m_set_rcvif(sd->sd_mbuf, ifp); 834 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 835 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 836 BUS_DMA_NOWAIT)) { 837 goto err_mbuf; 838 } 839 840 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 841 i * sizeof(struct txp_rxbuf_desc), 842 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 843 844 /* stash away pointer */ 845 rbd->rb_vaddrlo = txp_rxd_idx(sc, sd); 846 847 rbd->rb_paddrlo = 848 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[0].ds_addr)); 849 rbd->rb_paddrhi = 850 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[0].ds_addr)); 851 852 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 853 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 854 855 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 856 i * sizeof(struct txp_rxbuf_desc), 857 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 858 859 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 860 861 if (++i == RXBUF_ENTRIES) { 862 i = 0; 863 rbd = sc->sc_rxbufs; 864 } else 865 rbd++; 866 } 867 return; 868 869 err_mbuf: 870 m_freem(sd->sd_mbuf); 871 err_sd: 872 txp_rxd_free(sc, sd); 873 } 874 875 /* 876 * Reclaim mbufs and entries from a transmit ring. 877 */ 878 static void 879 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 880 struct txp_dma_alloc *dma) 881 { 882 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 883 uint32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 884 uint32_t cons = r->r_cons, cnt = r->r_cnt; 885 struct txp_tx_desc *txd = r->r_desc + cons; 886 struct txp_swdesc *sd = sc->sc_txd + cons; 887 struct mbuf *m; 888 889 while (cons != idx) { 890 if (cnt == 0) 891 break; 892 893 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 894 cons * sizeof(struct txp_tx_desc), 895 sizeof(struct txp_tx_desc), 896 BUS_DMASYNC_POSTWRITE); 897 898 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 899 TX_FLAGS_TYPE_DATA) { 900 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 901 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 902 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 903 m = sd->sd_mbuf; 904 if (m != NULL) { 905 m_freem(m); 906 txd->tx_addrlo = 0; 907 txd->tx_addrhi = 0; 908 if_statinc(ifp, if_opackets); 909 } 910 } 911 ifp->if_flags &= ~IFF_OACTIVE; 912 913 if (++cons == TX_ENTRIES) { 914 txd = r->r_desc; 915 cons = 0; 916 sd = sc->sc_txd; 917 } else { 918 txd++; 919 sd++; 920 } 921 922 cnt--; 923 } 924 925 r->r_cons = cons; 926 r->r_cnt = cnt; 927 if (cnt == 0) 928 ifp->if_timer = 0; 929 } 930 931 static bool 932 txp_shutdown(device_t self, int howto) 933 { 934 struct txp_softc *sc; 935 936 sc = device_private(self); 937 938 /* mask all interrupts */ 939 WRITE_REG(sc, TXP_IMR, 940 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 941 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 942 TXP_INT_LATCH); 943 944 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 945 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 946 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 947 948 return true; 949 } 950 951 static int 952 txp_alloc_rings(struct txp_softc *sc) 953 { 954 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 955 struct txp_boot_record *boot; 956 struct txp_swdesc *sd; 957 uint32_t r; 958 int i, j, nb; 959 960 /* boot record */ 961 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), 962 &sc->sc_boot_dma, BUS_DMA_COHERENT)) { 963 printf(": can't allocate boot record\n"); 964 return (-1); 965 } 966 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 967 memset(boot, 0, sizeof(*boot)); 968 sc->sc_boot = boot; 969 970 /* host variables */ 971 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 972 BUS_DMA_COHERENT)) { 973 printf(": can't allocate host ring\n"); 974 goto bail_boot; 975 } 976 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 977 boot->br_hostvar_lo = htole32(BUS_ADDR_LO32(sc->sc_host_dma.dma_paddr)); 978 boot->br_hostvar_hi = htole32(BUS_ADDR_HI32(sc->sc_host_dma.dma_paddr)); 979 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 980 981 /* high priority tx ring */ 982 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 983 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 984 printf(": can't allocate high tx ring\n"); 985 goto bail_host; 986 } 987 memset(sc->sc_txhiring_dma.dma_vaddr, 0, 988 sizeof(struct txp_tx_desc) * TX_ENTRIES); 989 boot->br_txhipri_lo = 990 htole32(BUS_ADDR_LO32(sc->sc_txhiring_dma.dma_paddr)); 991 boot->br_txhipri_hi = 992 htole32(BUS_ADDR_HI32(sc->sc_txhiring_dma.dma_paddr)); 993 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 994 sc->sc_txhir.r_reg = TXP_H2A_1; 995 sc->sc_txhir.r_desc = 996 (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 997 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 998 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 999 for (i = 0; i < TX_ENTRIES; i++) { 1000 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1001 TXP_MAXTXSEGS, TXP_MAX_SEGLEN, 0, BUS_DMA_NOWAIT, 1002 &sc->sc_txd[i].sd_map) != 0) { 1003 for (j = 0; j < i; j++) { 1004 bus_dmamap_destroy(sc->sc_dmat, 1005 sc->sc_txd[j].sd_map); 1006 sc->sc_txd[j].sd_map = NULL; 1007 } 1008 goto bail_txhiring; 1009 } 1010 } 1011 1012 /* low priority tx ring */ 1013 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1014 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 1015 printf(": can't allocate low tx ring\n"); 1016 goto bail_txhiring; 1017 } 1018 memset(sc->sc_txloring_dma.dma_vaddr, 0, 1019 sizeof(struct txp_tx_desc) * TX_ENTRIES); 1020 boot->br_txlopri_lo = 1021 htole32(BUS_ADDR_LO32(sc->sc_txloring_dma.dma_paddr)); 1022 boot->br_txlopri_hi = 1023 htole32(BUS_ADDR_HI32(sc->sc_txloring_dma.dma_paddr)); 1024 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1025 sc->sc_txlor.r_reg = TXP_H2A_3; 1026 sc->sc_txlor.r_desc = 1027 (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1028 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1029 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1030 1031 /* high priority rx ring */ 1032 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1033 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1034 printf(": can't allocate high rx ring\n"); 1035 goto bail_txloring; 1036 } 1037 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, 1038 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1039 boot->br_rxhipri_lo = 1040 htole32(BUS_ADDR_LO32(sc->sc_rxhiring_dma.dma_paddr)); 1041 boot->br_rxhipri_hi = 1042 htole32(BUS_ADDR_HI32(sc->sc_rxhiring_dma.dma_paddr)); 1043 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1044 sc->sc_rxhir.r_desc = 1045 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1046 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1047 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1048 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1049 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1050 1051 /* low priority ring */ 1052 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1053 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1054 printf(": can't allocate low rx ring\n"); 1055 goto bail_rxhiring; 1056 } 1057 memset(sc->sc_rxloring_dma.dma_vaddr, 0, 1058 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1059 boot->br_rxlopri_lo = 1060 htole32(BUS_ADDR_LO32(sc->sc_rxloring_dma.dma_paddr)); 1061 boot->br_rxlopri_hi = 1062 htole32(BUS_ADDR_HI32(sc->sc_rxloring_dma.dma_paddr)); 1063 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1064 sc->sc_rxlor.r_desc = 1065 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1066 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1067 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1068 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1069 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1070 1071 /* command ring */ 1072 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1073 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1074 printf(": can't allocate command ring\n"); 1075 goto bail_rxloring; 1076 } 1077 memset(sc->sc_cmdring_dma.dma_vaddr, 0, 1078 sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1079 boot->br_cmd_lo = htole32(BUS_ADDR_LO32(sc->sc_cmdring_dma.dma_paddr)); 1080 boot->br_cmd_hi = htole32(BUS_ADDR_HI32(sc->sc_cmdring_dma.dma_paddr)); 1081 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1082 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1083 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1084 sc->sc_cmdring.lastwrite = 0; 1085 1086 /* response ring */ 1087 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1088 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1089 printf(": can't allocate response ring\n"); 1090 goto bail_cmdring; 1091 } 1092 memset(sc->sc_rspring_dma.dma_vaddr, 0, 1093 sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1094 boot->br_resp_lo = htole32(BUS_ADDR_LO32(sc->sc_rspring_dma.dma_paddr)); 1095 boot->br_resp_hi = htole32(BUS_ADDR_HI32(sc->sc_rspring_dma.dma_paddr)); 1096 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1097 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1098 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1099 sc->sc_rspring.lastwrite = 0; 1100 1101 /* receive buffer ring */ 1102 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1103 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1104 printf(": can't allocate rx buffer ring\n"); 1105 goto bail_rspring; 1106 } 1107 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, 1108 sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1109 boot->br_rxbuf_lo = htole32(BUS_ADDR_LO32(sc->sc_rxbufring_dma.dma_paddr)); 1110 boot->br_rxbuf_hi = htole32(BUS_ADDR_HI32(sc->sc_rxbufring_dma.dma_paddr)); 1111 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1112 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1113 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1114 sd = &sc->sc_rxd[nb]; 1115 1116 /* stash away pointer */ 1117 sc->sc_rxbufs[nb].rb_vaddrlo = txp_rxd_idx(sc, sd); 1118 1119 MGETHDR(sd->sd_mbuf, M_WAIT, MT_DATA); 1120 if (sd->sd_mbuf == NULL) { 1121 goto bail_rxbufring; 1122 } 1123 1124 MCLGET(sd->sd_mbuf, M_WAIT); 1125 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1126 goto bail_rxbufring; 1127 } 1128 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1129 m_set_rcvif(sd->sd_mbuf, ifp); 1130 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1131 TXP_MAX_PKTLEN, 0, BUS_DMA_WAITOK, &sd->sd_map)) { 1132 goto bail_rxbufring; 1133 } 1134 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1135 BUS_DMA_WAITOK)) { 1136 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1137 goto bail_rxbufring; 1138 } 1139 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1140 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1141 1142 sc->sc_rxbufs[nb].rb_paddrlo = 1143 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[0].ds_addr)); 1144 sc->sc_rxbufs[nb].rb_paddrhi = 1145 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[0].ds_addr)); 1146 } 1147 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1148 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1149 BUS_DMASYNC_PREWRITE); 1150 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1151 sizeof(struct txp_rxbuf_desc)); 1152 1153 /* zero dma */ 1154 if (txp_dma_malloc(sc, sizeof(uint32_t), &sc->sc_zero_dma, 1155 BUS_DMA_COHERENT)) { 1156 printf(": can't allocate response ring\n"); 1157 goto bail_rxbufring; 1158 } 1159 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(uint32_t)); 1160 boot->br_zero_lo = htole32(BUS_ADDR_LO32(sc->sc_zero_dma.dma_paddr)); 1161 boot->br_zero_hi = htole32(BUS_ADDR_HI32(sc->sc_zero_dma.dma_paddr)); 1162 1163 /* See if it's waiting for boot, and try to boot it */ 1164 for (i = 0; i < 10000; i++) { 1165 r = READ_REG(sc, TXP_A2H_0); 1166 if (r == STAT_WAITING_FOR_BOOT) 1167 break; 1168 DELAY(50); 1169 } 1170 if (r != STAT_WAITING_FOR_BOOT) { 1171 printf(": not waiting for boot\n"); 1172 goto bail; 1173 } 1174 WRITE_REG(sc, TXP_H2A_2, BUS_ADDR_HI32(sc->sc_boot_dma.dma_paddr)); 1175 WRITE_REG(sc, TXP_H2A_1, BUS_ADDR_LO32(sc->sc_boot_dma.dma_paddr)); 1176 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1177 1178 /* See if it booted */ 1179 for (i = 0; i < 10000; i++) { 1180 r = READ_REG(sc, TXP_A2H_0); 1181 if (r == STAT_RUNNING) 1182 break; 1183 DELAY(50); 1184 } 1185 if (r != STAT_RUNNING) { 1186 printf(": fw not running\n"); 1187 goto bail; 1188 } 1189 1190 /* Clear TX and CMD ring write registers */ 1191 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1192 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1193 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1194 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1195 1196 return (0); 1197 1198 bail: 1199 txp_dma_free(sc, &sc->sc_zero_dma); 1200 bail_rxbufring: 1201 if (nb == RXBUF_ENTRIES) 1202 nb--; 1203 for (i = 0; i <= nb; i++) { 1204 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1205 sizeof(sd)); 1206 /* XXXJRT */ 1207 } 1208 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1209 bail_rspring: 1210 txp_dma_free(sc, &sc->sc_rspring_dma); 1211 bail_cmdring: 1212 txp_dma_free(sc, &sc->sc_cmdring_dma); 1213 bail_rxloring: 1214 txp_dma_free(sc, &sc->sc_rxloring_dma); 1215 bail_rxhiring: 1216 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1217 bail_txloring: 1218 txp_dma_free(sc, &sc->sc_txloring_dma); 1219 bail_txhiring: 1220 txp_dma_free(sc, &sc->sc_txhiring_dma); 1221 bail_host: 1222 txp_dma_free(sc, &sc->sc_host_dma); 1223 bail_boot: 1224 txp_dma_free(sc, &sc->sc_boot_dma); 1225 return (-1); 1226 } 1227 1228 static int 1229 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1230 struct txp_dma_alloc *dma, int mapflags) 1231 { 1232 int r; 1233 1234 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1235 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1236 goto fail_0; 1237 1238 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1239 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1240 goto fail_1; 1241 1242 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1243 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1244 goto fail_2; 1245 1246 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1247 size, NULL, BUS_DMA_NOWAIT)) != 0) 1248 goto fail_3; 1249 1250 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1251 return (0); 1252 1253 fail_3: 1254 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1255 fail_2: 1256 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1257 fail_1: 1258 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1259 fail_0: 1260 return (r); 1261 } 1262 1263 static void 1264 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1265 { 1266 bus_size_t mapsize = dma->dma_map->dm_mapsize; 1267 1268 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1269 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, mapsize); 1270 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1271 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1272 } 1273 1274 static int 1275 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1276 { 1277 struct txp_softc *sc = ifp->if_softc; 1278 struct ifaddr *ifa = (struct ifaddr *)data; 1279 int s, error = 0; 1280 1281 s = splnet(); 1282 1283 #if 0 1284 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1285 splx(s); 1286 return error; 1287 } 1288 #endif 1289 1290 switch (command) { 1291 case SIOCINITIFADDR: 1292 ifp->if_flags |= IFF_UP; 1293 txp_init(sc); 1294 switch (ifa->ifa_addr->sa_family) { 1295 #ifdef INET 1296 case AF_INET: 1297 arp_ifinit(ifp, ifa); 1298 break; 1299 #endif /* INET */ 1300 default: 1301 break; 1302 } 1303 break; 1304 case SIOCSIFFLAGS: 1305 if ((error = ifioctl_common(ifp, command, data)) != 0) 1306 break; 1307 if (ifp->if_flags & IFF_UP) { 1308 txp_init(sc); 1309 } else { 1310 if (ifp->if_flags & IFF_RUNNING) 1311 txp_stop(sc); 1312 } 1313 break; 1314 case SIOCADDMULTI: 1315 case SIOCDELMULTI: 1316 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1317 break; 1318 1319 error = 0; 1320 1321 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1322 ; 1323 else if (ifp->if_flags & IFF_RUNNING) { 1324 /* 1325 * Multicast list has changed; set the hardware 1326 * filter accordingly. 1327 */ 1328 txp_set_filter(sc); 1329 } 1330 break; 1331 default: 1332 error = ether_ioctl(ifp, command, data); 1333 break; 1334 } 1335 1336 splx(s); 1337 1338 return (error); 1339 } 1340 1341 static void 1342 txp_init(struct txp_softc *sc) 1343 { 1344 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1345 int s; 1346 1347 txp_stop(sc); 1348 1349 s = splnet(); 1350 1351 txp_set_filter(sc); 1352 1353 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1354 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1355 1356 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1357 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1358 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1359 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1360 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1361 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1362 1363 ifp->if_flags |= IFF_RUNNING; 1364 ifp->if_flags &= ~IFF_OACTIVE; 1365 ifp->if_timer = 0; 1366 1367 if (!callout_pending(&sc->sc_tick)) 1368 callout_schedule(&sc->sc_tick, hz); 1369 1370 splx(s); 1371 } 1372 1373 static void 1374 txp_tick(void *vsc) 1375 { 1376 struct txp_softc *sc = vsc; 1377 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1378 struct txp_rsp_desc *rsp = NULL; 1379 struct txp_ext_desc *ext; 1380 int s; 1381 1382 s = splnet(); 1383 txp_rxbuf_reclaim(sc); 1384 1385 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1386 &rsp, 1)) 1387 goto out; 1388 if (rsp->rsp_numdesc != 6) 1389 goto out; 1390 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1391 NULL, NULL, NULL, 1)) 1392 goto out; 1393 ext = (struct txp_ext_desc *)(rsp + 1); 1394 1395 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1396 if_statadd_ref(nsr, if_ierrors, 1397 ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1398 ext[4].ext_1 + ext[4].ext_4); 1399 if_statadd_ref(nsr, if_oerrors, 1400 ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + ext[2].ext_1); 1401 if_statadd_ref(nsr, if_collisions, 1402 ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + ext[1].ext_3); 1403 if_statadd_ref(nsr, if_opackets, rsp->rsp_par2); 1404 IF_STAT_PUTREF(ifp); 1405 1406 out: 1407 if (rsp != NULL) 1408 free(rsp, M_DEVBUF); 1409 1410 splx(s); 1411 callout_schedule(&sc->sc_tick, hz); 1412 } 1413 1414 static void 1415 txp_start(struct ifnet *ifp) 1416 { 1417 struct txp_softc *sc = ifp->if_softc; 1418 struct txp_tx_ring *r = &sc->sc_txhir; 1419 struct txp_tx_desc *txd; 1420 int txdidx; 1421 struct txp_frag_desc *fxd; 1422 struct mbuf *m, *mnew; 1423 struct txp_swdesc *sd; 1424 uint32_t prod, cnt, i; 1425 int error; 1426 1427 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1428 return; 1429 1430 prod = r->r_prod; 1431 cnt = r->r_cnt; 1432 1433 while (1) { 1434 if (cnt >= TX_ENTRIES - TXP_MAXTXSEGS - 4) { 1435 ifp->if_flags |= IFF_OACTIVE; 1436 break; 1437 } 1438 1439 IFQ_POLL(&ifp->if_snd, m); 1440 if (m == NULL) 1441 break; 1442 mnew = NULL; 1443 1444 sd = sc->sc_txd + prod; 1445 1446 /* 1447 * Load the DMA map. If this fails, the packet either 1448 * didn't fit in the alloted number of segments, or we 1449 * were short on resources. In this case, we'll copy 1450 * and try again. 1451 */ 1452 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1453 BUS_DMA_NOWAIT) != 0) { 1454 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1455 if (mnew == NULL) { 1456 printf("%s: unable to allocate Tx mbuf\n", 1457 device_xname(sc->sc_dev)); 1458 break; 1459 } 1460 if (m->m_pkthdr.len > MHLEN) { 1461 MCLGET(mnew, M_DONTWAIT); 1462 if ((mnew->m_flags & M_EXT) == 0) { 1463 printf("%s: unable to allocate Tx " 1464 "cluster\n", 1465 device_xname(sc->sc_dev)); 1466 m_freem(mnew); 1467 break; 1468 } 1469 } 1470 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1471 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1472 error = bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, 1473 mnew, BUS_DMA_NOWAIT); 1474 if (error) { 1475 printf("%s: unable to load Tx buffer, " 1476 "error = %d\n", device_xname(sc->sc_dev), 1477 error); 1478 m_freem(mnew); 1479 break; 1480 } 1481 } 1482 1483 IFQ_DEQUEUE(&ifp->if_snd, m); 1484 if (mnew != NULL) { 1485 m_freem(m); 1486 m = mnew; 1487 } 1488 1489 /* 1490 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1491 */ 1492 1493 sd->sd_mbuf = m; 1494 1495 txd = r->r_desc + prod; 1496 txdidx = prod; 1497 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1498 txd->tx_numdesc = 0; 1499 txd->tx_addrlo = 0; 1500 txd->tx_addrhi = 0; 1501 txd->tx_totlen = m->m_pkthdr.len; 1502 txd->tx_pflags = 0; 1503 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1504 1505 if (++prod == TX_ENTRIES) 1506 prod = 0; 1507 1508 if (vlan_has_tag(m)) 1509 txd->tx_pflags = TX_PFLAGS_VLAN | 1510 (htons(vlan_get_tag(m)) << TX_PFLAGS_VLANTAG_S); 1511 1512 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1513 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1514 #ifdef TRY_TX_TCP_CSUM 1515 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1516 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1517 #endif 1518 #ifdef TRY_TX_UDP_CSUM 1519 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1520 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1521 #endif 1522 1523 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1524 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1525 1526 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1527 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1528 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1529 FRAG_FLAGS_VALID; 1530 fxd->frag_rsvd1 = 0; 1531 fxd->frag_len = htole16(sd->sd_map->dm_segs[i].ds_len); 1532 fxd->frag_addrlo = 1533 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[i].ds_addr)); 1534 fxd->frag_addrhi = 1535 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[i].ds_addr)); 1536 fxd->frag_rsvd2 = 0; 1537 1538 bus_dmamap_sync(sc->sc_dmat, 1539 sc->sc_txhiring_dma.dma_map, 1540 prod * sizeof(struct txp_frag_desc), 1541 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1542 1543 if (++prod == TX_ENTRIES) { 1544 fxd = (struct txp_frag_desc *)r->r_desc; 1545 prod = 0; 1546 } else 1547 fxd++; 1548 1549 } 1550 1551 ifp->if_timer = 5; 1552 1553 bpf_mtap(ifp, m, BPF_D_OUT); 1554 1555 txd->tx_flags |= TX_FLAGS_VALID; 1556 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1557 txdidx * sizeof(struct txp_tx_desc), 1558 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1559 1560 #if 0 1561 { 1562 struct mbuf *mx; 1563 int i; 1564 1565 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1566 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1567 txd->tx_pflags); 1568 for (mx = m; mx != NULL; mx = mx->m_next) { 1569 for (i = 0; i < mx->m_len; i++) { 1570 printf(":%02x", 1571 (uint8_t)m->m_data[i]); 1572 } 1573 } 1574 printf("\n"); 1575 } 1576 #endif 1577 1578 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1579 } 1580 1581 r->r_prod = prod; 1582 r->r_cnt = cnt; 1583 } 1584 1585 /* 1586 * Handle simple commands sent to the typhoon 1587 */ 1588 static int 1589 txp_command(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1590 uint32_t in3, uint16_t *out1, uint32_t *out2, uint32_t *out3, int wait) 1591 { 1592 struct txp_rsp_desc *rsp = NULL; 1593 1594 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1595 return (-1); 1596 1597 if (!wait) 1598 return (0); 1599 1600 if (out1 != NULL) 1601 *out1 = le16toh(rsp->rsp_par1); 1602 if (out2 != NULL) 1603 *out2 = le32toh(rsp->rsp_par2); 1604 if (out3 != NULL) 1605 *out3 = le32toh(rsp->rsp_par3); 1606 free(rsp, M_DEVBUF); 1607 return (0); 1608 } 1609 1610 static int 1611 txp_command2(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1612 uint32_t in3, struct txp_ext_desc *in_extp, uint8_t in_extn, 1613 struct txp_rsp_desc **rspp, int wait) 1614 { 1615 struct txp_hostvar *hv = sc->sc_hostvar; 1616 struct txp_cmd_desc *cmd; 1617 struct txp_ext_desc *ext; 1618 uint32_t idx, i; 1619 uint16_t seq; 1620 1621 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1622 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1623 return (-1); 1624 } 1625 1626 idx = sc->sc_cmdring.lastwrite; 1627 cmd = (struct txp_cmd_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1628 memset(cmd, 0, sizeof(*cmd)); 1629 1630 cmd->cmd_numdesc = in_extn; 1631 seq = sc->sc_seq++; 1632 cmd->cmd_seq = htole16(seq); 1633 cmd->cmd_id = htole16(id); 1634 cmd->cmd_par1 = htole16(in1); 1635 cmd->cmd_par2 = htole32(in2); 1636 cmd->cmd_par3 = htole32(in3); 1637 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1638 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1639 1640 idx += sizeof(struct txp_cmd_desc); 1641 if (idx == sc->sc_cmdring.size) 1642 idx = 0; 1643 1644 for (i = 0; i < in_extn; i++) { 1645 ext = (struct txp_ext_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1646 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1647 in_extp++; 1648 idx += sizeof(struct txp_cmd_desc); 1649 if (idx == sc->sc_cmdring.size) 1650 idx = 0; 1651 } 1652 1653 sc->sc_cmdring.lastwrite = idx; 1654 1655 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1656 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1657 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1658 1659 if (!wait) 1660 return (0); 1661 1662 for (i = 0; i < 10000; i++) { 1663 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1664 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1665 idx = le32toh(hv->hv_resp_read_idx); 1666 if (idx != le32toh(hv->hv_resp_write_idx)) { 1667 *rspp = NULL; 1668 if (txp_response(sc, idx, id, seq, rspp)) 1669 return (-1); 1670 if (*rspp != NULL) 1671 break; 1672 } 1673 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1674 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1675 DELAY(50); 1676 } 1677 if (i == 1000 || (*rspp) == NULL) { 1678 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1679 return (-1); 1680 } 1681 1682 return (0); 1683 } 1684 1685 static int 1686 txp_response(struct txp_softc *sc, uint32_t ridx, uint16_t id, uint16_t seq, 1687 struct txp_rsp_desc **rspp) 1688 { 1689 struct txp_hostvar *hv = sc->sc_hostvar; 1690 struct txp_rsp_desc *rsp; 1691 1692 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1693 rsp = (struct txp_rsp_desc *)(((uint8_t *)sc->sc_rspring.base) + ridx); 1694 1695 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1696 *rspp = (struct txp_rsp_desc *)malloc( 1697 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1698 M_DEVBUF, M_NOWAIT); 1699 if ((*rspp) == NULL) 1700 return (-1); 1701 txp_rsp_fixup(sc, rsp, *rspp); 1702 return (0); 1703 } 1704 1705 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1706 printf("%s: response error: id 0x%x\n", 1707 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1708 txp_rsp_fixup(sc, rsp, NULL); 1709 ridx = le32toh(hv->hv_resp_read_idx); 1710 continue; 1711 } 1712 1713 switch (le16toh(rsp->rsp_id)) { 1714 case TXP_CMD_CYCLE_STATISTICS: 1715 case TXP_CMD_MEDIA_STATUS_READ: 1716 break; 1717 case TXP_CMD_HELLO_RESPONSE: 1718 printf("%s: hello\n", TXP_DEVNAME(sc)); 1719 break; 1720 default: 1721 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1722 le16toh(rsp->rsp_id)); 1723 } 1724 1725 txp_rsp_fixup(sc, rsp, NULL); 1726 ridx = le32toh(hv->hv_resp_read_idx); 1727 hv->hv_resp_read_idx = le32toh(ridx); 1728 } 1729 1730 return (0); 1731 } 1732 1733 static void 1734 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1735 struct txp_rsp_desc *dst) 1736 { 1737 struct txp_rsp_desc *src = rsp; 1738 struct txp_hostvar *hv = sc->sc_hostvar; 1739 uint32_t i, ridx; 1740 1741 ridx = le32toh(hv->hv_resp_read_idx); 1742 1743 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1744 if (dst != NULL) 1745 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1746 ridx += sizeof(struct txp_rsp_desc); 1747 if (ridx == sc->sc_rspring.size) { 1748 src = sc->sc_rspring.base; 1749 ridx = 0; 1750 } else 1751 src++; 1752 sc->sc_rspring.lastwrite = ridx; 1753 hv->hv_resp_read_idx = htole32(ridx); 1754 } 1755 1756 hv->hv_resp_read_idx = htole32(ridx); 1757 } 1758 1759 static int 1760 txp_cmd_desc_numfree(struct txp_softc *sc) 1761 { 1762 struct txp_hostvar *hv = sc->sc_hostvar; 1763 struct txp_boot_record *br = sc->sc_boot; 1764 uint32_t widx, ridx, nfree; 1765 1766 widx = sc->sc_cmdring.lastwrite; 1767 ridx = le32toh(hv->hv_cmd_read_idx); 1768 1769 if (widx == ridx) { 1770 /* Ring is completely free */ 1771 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1772 } else { 1773 if (widx > ridx) 1774 nfree = le32toh(br->br_cmd_siz) - 1775 (widx - ridx + sizeof(struct txp_cmd_desc)); 1776 else 1777 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1778 } 1779 1780 return (nfree / sizeof(struct txp_cmd_desc)); 1781 } 1782 1783 static void 1784 txp_stop(struct txp_softc *sc) 1785 { 1786 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1787 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1788 1789 if (callout_pending(&sc->sc_tick)) 1790 callout_stop(&sc->sc_tick); 1791 } 1792 1793 static void 1794 txp_watchdog(struct ifnet *ifp) 1795 { 1796 } 1797 1798 static int 1799 txp_ifmedia_upd(struct ifnet *ifp) 1800 { 1801 struct txp_softc *sc = ifp->if_softc; 1802 struct ifmedia *ifm = &sc->sc_ifmedia; 1803 uint16_t new_xcvr; 1804 1805 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1806 return (EINVAL); 1807 1808 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1809 if ((ifm->ifm_media & IFM_FDX) != 0) 1810 new_xcvr = TXP_XCVR_10_FDX; 1811 else 1812 new_xcvr = TXP_XCVR_10_HDX; 1813 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1814 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1815 if ((ifm->ifm_media & IFM_FDX) != 0) 1816 new_xcvr = TXP_XCVR_100_FDX; 1817 else 1818 new_xcvr = TXP_XCVR_100_HDX; 1819 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1820 new_xcvr = TXP_XCVR_AUTO; 1821 } else 1822 return (EINVAL); 1823 1824 /* nothing to do */ 1825 if (sc->sc_xcvr == new_xcvr) 1826 return (0); 1827 1828 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1829 NULL, NULL, NULL, 0); 1830 sc->sc_xcvr = new_xcvr; 1831 1832 return (0); 1833 } 1834 1835 static void 1836 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1837 { 1838 struct txp_softc *sc = ifp->if_softc; 1839 struct ifmedia *ifm = &sc->sc_ifmedia; 1840 uint16_t bmsr, bmcr, anlpar; 1841 1842 ifmr->ifm_status = IFM_AVALID; 1843 ifmr->ifm_active = IFM_ETHER; 1844 1845 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1846 &bmsr, NULL, NULL, 1)) 1847 goto bail; 1848 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1849 &bmsr, NULL, NULL, 1)) 1850 goto bail; 1851 1852 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1853 &bmcr, NULL, NULL, 1)) 1854 goto bail; 1855 1856 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1857 &anlpar, NULL, NULL, 1)) 1858 goto bail; 1859 1860 if (bmsr & BMSR_LINK) 1861 ifmr->ifm_status |= IFM_ACTIVE; 1862 1863 if (bmcr & BMCR_ISO) { 1864 ifmr->ifm_active |= IFM_NONE; 1865 ifmr->ifm_status = 0; 1866 return; 1867 } 1868 1869 if (bmcr & BMCR_LOOP) 1870 ifmr->ifm_active |= IFM_LOOP; 1871 1872 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1873 if ((bmsr & BMSR_ACOMP) == 0) { 1874 ifmr->ifm_active |= IFM_NONE; 1875 return; 1876 } 1877 1878 if (anlpar & ANLPAR_TX_FD) 1879 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 1880 else if (anlpar & ANLPAR_T4) 1881 ifmr->ifm_active |= IFM_100_T4 | IFM_HDX; 1882 else if (anlpar & ANLPAR_TX) 1883 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 1884 else if (anlpar & ANLPAR_10_FD) 1885 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 1886 else if (anlpar & ANLPAR_10) 1887 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 1888 else 1889 ifmr->ifm_active |= IFM_NONE; 1890 } else 1891 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1892 return; 1893 1894 bail: 1895 ifmr->ifm_active |= IFM_NONE; 1896 ifmr->ifm_status &= ~IFM_AVALID; 1897 } 1898 1899 #if 0 /* XXX XXX XXX UNUSED */ 1900 static void 1901 txp_show_descriptor(void *d) 1902 { 1903 struct txp_cmd_desc *cmd = d; 1904 struct txp_rsp_desc *rsp = d; 1905 struct txp_tx_desc *txd = d; 1906 struct txp_frag_desc *frgd = d; 1907 1908 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1909 case CMD_FLAGS_TYPE_CMD: 1910 /* command descriptor */ 1911 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1912 "0x%x par3 0x%x]\n", 1913 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1914 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1915 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1916 break; 1917 case CMD_FLAGS_TYPE_RESP: 1918 /* response descriptor */ 1919 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1920 "0x%x par3 0x%x]\n", 1921 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1922 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1923 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1924 break; 1925 case CMD_FLAGS_TYPE_DATA: 1926 /* data header (assuming tx for now) */ 1927 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x " 1928 "pflags 0x%x]", 1929 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1930 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1931 break; 1932 case CMD_FLAGS_TYPE_FRAG: 1933 /* fragment descriptor */ 1934 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x " 1935 "rsvd2 0x%x]", 1936 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1937 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1938 break; 1939 default: 1940 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 " 1941 "0x%x par2 0x%x par3 0x%x]\n", 1942 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1943 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1944 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1945 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1946 break; 1947 } 1948 } 1949 #endif 1950 1951 static void 1952 txp_set_filter(struct txp_softc *sc) 1953 { 1954 struct ethercom *ec = &sc->sc_arpcom; 1955 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1956 uint32_t crc, carry, hashbit, hash[2]; 1957 uint16_t filter; 1958 uint8_t octet; 1959 int i, j, mcnt = 0; 1960 struct ether_multi *enm; 1961 struct ether_multistep step; 1962 1963 if (ifp->if_flags & IFF_PROMISC) { 1964 filter = TXP_RXFILT_PROMISC; 1965 goto setit; 1966 } 1967 1968 again: 1969 filter = TXP_RXFILT_DIRECT; 1970 1971 if (ifp->if_flags & IFF_BROADCAST) 1972 filter |= TXP_RXFILT_BROADCAST; 1973 1974 if (ifp->if_flags & IFF_ALLMULTI) 1975 filter |= TXP_RXFILT_ALLMULTI; 1976 else { 1977 hash[0] = hash[1] = 0; 1978 1979 ETHER_LOCK(ec); 1980 ETHER_FIRST_MULTI(step, ec, enm); 1981 while (enm != NULL) { 1982 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1983 ETHER_ADDR_LEN)) { 1984 /* 1985 * We must listen to a range of multicast 1986 * addresses. For now, just accept all 1987 * multicasts, rather than trying to set only 1988 * those filter bits needed to match the range. 1989 * (At this time, the only use of address 1990 * ranges is for IP multicast routing, for 1991 * which the range is big enough to require 1992 * all bits set.) 1993 */ 1994 ifp->if_flags |= IFF_ALLMULTI; 1995 ETHER_UNLOCK(ec); 1996 goto again; 1997 } 1998 1999 mcnt++; 2000 crc = 0xffffffff; 2001 2002 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2003 octet = enm->enm_addrlo[i]; 2004 for (j = 0; j < 8; j++) { 2005 carry = ((crc & 0x80000000) ? 1 : 0) ^ 2006 (octet & 1); 2007 crc <<= 1; 2008 octet >>= 1; 2009 if (carry) 2010 crc = (crc ^ TXP_POLYNOMIAL) | 2011 carry; 2012 } 2013 } 2014 hashbit = (uint16_t)(crc & (64 - 1)); 2015 hash[hashbit / 32] |= (1 << hashbit % 32); 2016 ETHER_NEXT_MULTI(step, enm); 2017 } 2018 ETHER_UNLOCK(ec); 2019 2020 if (mcnt > 0) { 2021 filter |= TXP_RXFILT_HASHMULTI; 2022 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 2023 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2024 } 2025 } 2026 2027 setit: 2028 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2029 NULL, NULL, NULL, 1); 2030 } 2031 2032 static void 2033 txp_capabilities(struct txp_softc *sc) 2034 { 2035 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2036 struct txp_rsp_desc *rsp = NULL; 2037 struct txp_ext_desc *ext; 2038 2039 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2040 goto out; 2041 2042 if (rsp->rsp_numdesc != 1) 2043 goto out; 2044 ext = (struct txp_ext_desc *)(rsp + 1); 2045 2046 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2047 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2048 2049 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2050 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2051 sc->sc_tx_capability |= OFFLOAD_VLAN; 2052 sc->sc_rx_capability |= OFFLOAD_VLAN; 2053 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2054 sc->sc_arpcom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 2055 } 2056 2057 #if 0 2058 /* not ready yet */ 2059 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2060 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2061 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2062 ifp->if_capabilities |= IFCAP_IPSEC; 2063 } 2064 #endif 2065 2066 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2067 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2068 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2069 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2070 } 2071 2072 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2073 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2074 #ifdef TRY_TX_TCP_CSUM 2075 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2076 ifp->if_capabilities |= 2077 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2078 #endif 2079 } 2080 2081 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2082 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2083 #ifdef TRY_TX_UDP_CSUM 2084 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2085 ifp->if_capabilities |= 2086 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2087 #endif 2088 } 2089 2090 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2091 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2092 goto out; 2093 2094 out: 2095 if (rsp != NULL) 2096 free(rsp, M_DEVBUF); 2097 } 2098