1 /* $NetBSD: if_stge.c,v 1.70 2019/07/09 08:46:59 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.70 2019/07/09 08:46:59 msaitoh Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stgereg.h> 72 73 #include <prop/proplib.h> 74 75 /* #define STGE_CU_BUG 1 */ 76 #define STGE_VLAN_UNTAG 1 77 /* #define STGE_VLAN_CFI 1 */ 78 79 /* 80 * Transmit descriptor list size. 81 */ 82 #define STGE_NTXDESC 256 83 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 84 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 85 86 /* 87 * Receive descriptor list size. 88 */ 89 #define STGE_NRXDESC 256 90 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 91 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 92 93 /* 94 * Only interrupt every N frames. Must be a power-of-two. 95 */ 96 #define STGE_TXINTR_SPACING 16 97 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 98 99 /* 100 * Control structures are DMA'd to the TC9021 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct stge_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 114 }; 115 116 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 117 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 118 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct stge_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct stge_softc { 132 device_t sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 int sc_rev; /* silicon revision */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 callout_t sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 152 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct stge_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 #ifdef STGE_EVENT_COUNTERS 162 /* 163 * Event counters. 164 */ 165 struct evcnt sc_ev_txstall; /* Tx stalled */ 166 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 167 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 168 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 169 170 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 171 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 172 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 173 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 174 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 175 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 176 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 177 178 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 179 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 180 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 181 182 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 183 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 184 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 185 #endif /* STGE_EVENT_COUNTERS */ 186 187 int sc_txpending; /* number of Tx requests pending */ 188 int sc_txdirty; /* first dirty Tx descriptor */ 189 int sc_txlast; /* last used Tx descriptor */ 190 191 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 192 int sc_rxdiscard; 193 int sc_rxlen; 194 struct mbuf *sc_rxhead; 195 struct mbuf *sc_rxtail; 196 struct mbuf **sc_rxtailp; 197 198 int sc_txthresh; /* Tx threshold */ 199 uint32_t sc_usefiber:1; /* if we're fiber */ 200 uint32_t sc_stge1023:1; /* are we a 1023 */ 201 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 202 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 203 uint16_t sc_IntEnable; /* prototype IntEnable register */ 204 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 205 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 206 }; 207 208 #define STGE_RXCHAIN_RESET(sc) \ 209 do { \ 210 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 211 *(sc)->sc_rxtailp = NULL; \ 212 (sc)->sc_rxlen = 0; \ 213 } while (/*CONSTCOND*/0) 214 215 #define STGE_RXCHAIN_LINK(sc, m) \ 216 do { \ 217 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 218 (sc)->sc_rxtailp = &(m)->m_next; \ 219 } while (/*CONSTCOND*/0) 220 221 #ifdef STGE_EVENT_COUNTERS 222 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 223 #else 224 #define STGE_EVCNT_INCR(ev) /* nothing */ 225 #endif 226 227 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 228 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 229 230 #define STGE_CDTXSYNC(sc, x, ops) \ 231 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 232 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 233 234 #define STGE_CDRXSYNC(sc, x, ops) \ 235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 236 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 237 238 #define STGE_INIT_RXDESC(sc, x) \ 239 do { \ 240 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 241 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 242 \ 243 /* \ 244 * Note: We scoot the packet forward 2 bytes in the buffer \ 245 * so that the payload after the Ethernet header is aligned \ 246 * to a 4-byte boundary. \ 247 */ \ 248 __rfd->rfd_frag.frag_word0 = \ 249 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 250 FRAG_LEN(MCLBYTES - 2)); \ 251 __rfd->rfd_next = \ 252 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 253 __rfd->rfd_status = 0; \ 254 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 255 } while (/*CONSTCOND*/0) 256 257 #define STGE_TIMEOUT 1000 258 259 static void stge_start(struct ifnet *); 260 static void stge_watchdog(struct ifnet *); 261 static int stge_ioctl(struct ifnet *, u_long, void *); 262 static int stge_init(struct ifnet *); 263 static void stge_stop(struct ifnet *, int); 264 265 static bool stge_shutdown(device_t, int); 266 267 static void stge_reset(struct stge_softc *); 268 static void stge_rxdrain(struct stge_softc *); 269 static int stge_add_rxbuf(struct stge_softc *, int); 270 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 271 static void stge_tick(void *); 272 273 static void stge_stats_update(struct stge_softc *); 274 275 static void stge_set_filter(struct stge_softc *); 276 277 static int stge_intr(void *); 278 static void stge_txintr(struct stge_softc *); 279 static void stge_rxintr(struct stge_softc *); 280 281 static int stge_mii_readreg(device_t, int, int, uint16_t *); 282 static int stge_mii_writereg(device_t, int, int, uint16_t); 283 static void stge_mii_statchg(struct ifnet *); 284 285 static int stge_match(device_t, cfdata_t, void *); 286 static void stge_attach(device_t, device_t, void *); 287 288 int stge_copy_small = 0; 289 290 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 291 stge_match, stge_attach, NULL, NULL); 292 293 static uint32_t stge_mii_bitbang_read(device_t); 294 static void stge_mii_bitbang_write(device_t, uint32_t); 295 296 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 297 stge_mii_bitbang_read, 298 stge_mii_bitbang_write, 299 { 300 PC_MgmtData, /* MII_BIT_MDO */ 301 PC_MgmtData, /* MII_BIT_MDI */ 302 PC_MgmtClk, /* MII_BIT_MDC */ 303 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 304 0, /* MII_BIT_DIR_PHY_HOST */ 305 } 306 }; 307 308 /* 309 * Devices supported by this driver. 310 */ 311 static const struct stge_product { 312 pci_vendor_id_t stge_vendor; 313 pci_product_id_t stge_product; 314 const char *stge_name; 315 } stge_products[] = { 316 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 317 "Sundance ST-1023 Gigabit Ethernet" }, 318 319 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 320 "Sundance ST-2021 Gigabit Ethernet" }, 321 322 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 323 "Tamarack TC9021 Gigabit Ethernet" }, 324 325 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 326 "Tamarack TC9021 Gigabit Ethernet" }, 327 328 /* 329 * The Sundance sample boards use the Sundance vendor ID, 330 * but the Tamarack product ID. 331 */ 332 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 333 "Sundance TC9021 Gigabit Ethernet" }, 334 335 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 336 "Sundance TC9021 Gigabit Ethernet" }, 337 338 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 339 "D-Link DL-4000 Gigabit Ethernet" }, 340 341 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 342 "Antares Gigabit Ethernet" }, 343 344 { 0, 0, 345 NULL }, 346 }; 347 348 static const struct stge_product * 349 stge_lookup(const struct pci_attach_args *pa) 350 { 351 const struct stge_product *sp; 352 353 for (sp = stge_products; sp->stge_name != NULL; sp++) { 354 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 355 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 356 return (sp); 357 } 358 return (NULL); 359 } 360 361 static int 362 stge_match(device_t parent, cfdata_t cf, void *aux) 363 { 364 struct pci_attach_args *pa = aux; 365 366 if (stge_lookup(pa) != NULL) 367 return (1); 368 369 return (0); 370 } 371 372 static void 373 stge_attach(device_t parent, device_t self, void *aux) 374 { 375 struct stge_softc *sc = device_private(self); 376 struct pci_attach_args *pa = aux; 377 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 378 struct mii_data * const mii = &sc->sc_mii; 379 pci_chipset_tag_t pc = pa->pa_pc; 380 pci_intr_handle_t ih; 381 const char *intrstr = NULL; 382 bus_space_tag_t iot, memt; 383 bus_space_handle_t ioh, memh; 384 bus_dma_segment_t seg; 385 prop_data_t data; 386 int ioh_valid, memh_valid; 387 int i, rseg, error; 388 const struct stge_product *sp; 389 uint8_t enaddr[ETHER_ADDR_LEN]; 390 char intrbuf[PCI_INTRSTR_LEN]; 391 392 callout_init(&sc->sc_tick_ch, 0); 393 394 sp = stge_lookup(pa); 395 if (sp == NULL) { 396 printf("\n"); 397 panic("ste_attach: impossible"); 398 } 399 400 sc->sc_rev = PCI_REVISION(pa->pa_class); 401 402 pci_aprint_devinfo_fancy(pa, NULL, sp->stge_name, 1); 403 404 /* 405 * Map the device. 406 */ 407 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 408 PCI_MAPREG_TYPE_IO, 0, 409 &iot, &ioh, NULL, NULL) == 0); 410 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 411 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 412 &memt, &memh, NULL, NULL) == 0); 413 414 if (memh_valid) { 415 sc->sc_st = memt; 416 sc->sc_sh = memh; 417 } else if (ioh_valid) { 418 sc->sc_st = iot; 419 sc->sc_sh = ioh; 420 } else { 421 aprint_error_dev(self, "unable to map device registers\n"); 422 return; 423 } 424 425 sc->sc_dmat = pa->pa_dmat; 426 427 /* Enable bus mastering. */ 428 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 429 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 430 PCI_COMMAND_MASTER_ENABLE); 431 432 /* power up chip */ 433 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 434 error != EOPNOTSUPP) { 435 aprint_error_dev(self, "cannot activate %d\n", error); 436 return; 437 } 438 /* 439 * Map and establish our interrupt. 440 */ 441 if (pci_intr_map(pa, &ih)) { 442 aprint_error_dev(self, "unable to map interrupt\n"); 443 return; 444 } 445 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 446 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, stge_intr, sc, 447 device_xname(self)); 448 if (sc->sc_ih == NULL) { 449 aprint_error_dev(self, "unable to establish interrupt"); 450 if (intrstr != NULL) 451 aprint_error(" at %s", intrstr); 452 aprint_error("\n"); 453 return; 454 } 455 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 456 457 /* 458 * Allocate the control data structures, and create and load the 459 * DMA map for it. 460 */ 461 if ((error = bus_dmamem_alloc(sc->sc_dmat, 462 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 463 0)) != 0) { 464 aprint_error_dev(self, 465 "unable to allocate control data, error = %d\n", error); 466 goto fail_0; 467 } 468 469 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 470 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 471 BUS_DMA_COHERENT)) != 0) { 472 aprint_error_dev(self, 473 "unable to map control data, error = %d\n", error); 474 goto fail_1; 475 } 476 477 if ((error = bus_dmamap_create(sc->sc_dmat, 478 sizeof(struct stge_control_data), 1, 479 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 480 aprint_error_dev(self, 481 "unable to create control data DMA map, error = %d\n", 482 error); 483 goto fail_2; 484 } 485 486 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 487 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 488 0)) != 0) { 489 aprint_error_dev(self, 490 "unable to load control data DMA map, error = %d\n", 491 error); 492 goto fail_3; 493 } 494 495 /* 496 * Create the transmit buffer DMA maps. Note that rev B.3 497 * and earlier seem to have a bug regarding multi-fragment 498 * packets. We need to limit the number of Tx segments on 499 * such chips to 1. 500 */ 501 for (i = 0; i < STGE_NTXDESC; i++) { 502 if ((error = bus_dmamap_create(sc->sc_dmat, 503 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 504 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 505 aprint_error_dev(self, 506 "unable to create tx DMA map %d, error = %d\n", 507 i, error); 508 goto fail_4; 509 } 510 } 511 512 /* 513 * Create the receive buffer DMA maps. 514 */ 515 for (i = 0; i < STGE_NRXDESC; i++) { 516 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 517 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 518 aprint_error_dev(self, 519 "unable to create rx DMA map %d, error = %d\n", 520 i, error); 521 goto fail_5; 522 } 523 sc->sc_rxsoft[i].ds_mbuf = NULL; 524 } 525 526 /* 527 * Determine if we're copper or fiber. It affects how we 528 * reset the card. 529 */ 530 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 531 AC_PhyMedia) 532 sc->sc_usefiber = 1; 533 else 534 sc->sc_usefiber = 0; 535 536 /* 537 * Reset the chip to a known state. 538 */ 539 stge_reset(sc); 540 541 /* 542 * Reading the station address from the EEPROM doesn't seem 543 * to work, at least on my sample boards. Instead, since 544 * the reset sequence does AutoInit, read it from the station 545 * address registers. For Sundance 1023 you can only read it 546 * from EEPROM. 547 */ 548 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 549 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 550 STGE_StationAddress0) & 0xff; 551 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 552 STGE_StationAddress0) >> 8; 553 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 554 STGE_StationAddress1) & 0xff; 555 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 556 STGE_StationAddress1) >> 8; 557 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 558 STGE_StationAddress2) & 0xff; 559 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 560 STGE_StationAddress2) >> 8; 561 sc->sc_stge1023 = 0; 562 } else { 563 data = prop_dictionary_get(device_properties(self), 564 "mac-address"); 565 if (data != NULL) { 566 /* 567 * Try to get the station address from device 568 * properties first, in case the EEPROM is missing. 569 */ 570 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 571 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 572 (void)memcpy(enaddr, prop_data_data_nocopy(data), 573 ETHER_ADDR_LEN); 574 } else { 575 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 576 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 577 stge_read_eeprom(sc, 578 STGE_EEPROM_StationAddress0 + i, 579 &myaddr[i]); 580 myaddr[i] = le16toh(myaddr[i]); 581 } 582 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 583 } 584 sc->sc_stge1023 = 1; 585 } 586 587 aprint_normal_dev(self, "Ethernet address %s\n", 588 ether_sprintf(enaddr)); 589 590 /* 591 * Read some important bits from the PhyCtrl register. 592 */ 593 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 594 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 595 596 /* 597 * Initialize our media structures and probe the MII. 598 */ 599 mii->mii_ifp = ifp; 600 mii->mii_readreg = stge_mii_readreg; 601 mii->mii_writereg = stge_mii_writereg; 602 mii->mii_statchg = stge_mii_statchg; 603 sc->sc_ethercom.ec_mii = mii; 604 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 605 ether_mediastatus); 606 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 607 MII_OFFSET_ANY, MIIF_DOPAUSE); 608 if (LIST_FIRST(&mii->mii_phys) == NULL) { 609 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 610 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 611 } else 612 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 613 614 ifp = &sc->sc_ethercom.ec_if; 615 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 616 ifp->if_softc = sc; 617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 618 ifp->if_ioctl = stge_ioctl; 619 ifp->if_start = stge_start; 620 ifp->if_watchdog = stge_watchdog; 621 ifp->if_init = stge_init; 622 ifp->if_stop = stge_stop; 623 IFQ_SET_READY(&ifp->if_snd); 624 625 /* 626 * The manual recommends disabling early transmit, so we 627 * do. It's disabled anyway, if using IP checksumming, 628 * since the entire packet must be in the FIFO in order 629 * for the chip to perform the checksum. 630 */ 631 sc->sc_txthresh = 0x0fff; 632 633 /* 634 * Disable MWI if the PCI layer tells us to. 635 */ 636 sc->sc_DMACtrl = 0; 637 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 638 sc->sc_DMACtrl |= DMAC_MWIDisable; 639 640 /* 641 * We can support 802.1Q VLAN-sized frames and jumbo 642 * Ethernet frames. 643 * 644 * XXX Figure out how to do hw-assisted VLAN tagging in 645 * XXX a reasonable way on this chip. 646 */ 647 sc->sc_ethercom.ec_capabilities |= 648 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 649 ETHERCAP_VLAN_HWTAGGING; 650 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 651 652 /* 653 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 654 */ 655 sc->sc_ethercom.ec_if.if_capabilities |= 656 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 657 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 658 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 659 660 /* 661 * Attach the interface. 662 */ 663 if_attach(ifp); 664 if_deferred_start_init(ifp, NULL); 665 ether_ifattach(ifp, enaddr); 666 667 #ifdef STGE_EVENT_COUNTERS 668 /* 669 * Attach event counters. 670 */ 671 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 672 NULL, device_xname(self), "txstall"); 673 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 674 NULL, device_xname(self), "txdmaintr"); 675 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 676 NULL, device_xname(self), "txindintr"); 677 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 678 NULL, device_xname(self), "rxintr"); 679 680 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 681 NULL, device_xname(self), "txseg1"); 682 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 683 NULL, device_xname(self), "txseg2"); 684 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 685 NULL, device_xname(self), "txseg3"); 686 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 687 NULL, device_xname(self), "txseg4"); 688 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 689 NULL, device_xname(self), "txseg5"); 690 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 691 NULL, device_xname(self), "txsegmore"); 692 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 693 NULL, device_xname(self), "txcopy"); 694 695 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 696 NULL, device_xname(self), "rxipsum"); 697 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 698 NULL, device_xname(self), "rxtcpsum"); 699 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 700 NULL, device_xname(self), "rxudpsum"); 701 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 702 NULL, device_xname(self), "txipsum"); 703 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 704 NULL, device_xname(self), "txtcpsum"); 705 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 706 NULL, device_xname(self), "txudpsum"); 707 #endif /* STGE_EVENT_COUNTERS */ 708 709 /* 710 * Make sure the interface is shutdown during reboot. 711 */ 712 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 713 pmf_class_network_register(self, ifp); 714 else 715 aprint_error_dev(self, "couldn't establish power handler\n"); 716 717 return; 718 719 /* 720 * Free any resources we've allocated during the failed attach 721 * attempt. Do this in reverse order and fall through. 722 */ 723 fail_5: 724 for (i = 0; i < STGE_NRXDESC; i++) { 725 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 726 bus_dmamap_destroy(sc->sc_dmat, 727 sc->sc_rxsoft[i].ds_dmamap); 728 } 729 fail_4: 730 for (i = 0; i < STGE_NTXDESC; i++) { 731 if (sc->sc_txsoft[i].ds_dmamap != NULL) 732 bus_dmamap_destroy(sc->sc_dmat, 733 sc->sc_txsoft[i].ds_dmamap); 734 } 735 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 736 fail_3: 737 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 738 fail_2: 739 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 740 sizeof(struct stge_control_data)); 741 fail_1: 742 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 743 fail_0: 744 return; 745 } 746 747 /* 748 * stge_shutdown: 749 * 750 * Make sure the interface is stopped at reboot time. 751 */ 752 static bool 753 stge_shutdown(device_t self, int howto) 754 { 755 struct stge_softc *sc = device_private(self); 756 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 757 758 stge_stop(ifp, 1); 759 stge_reset(sc); 760 return true; 761 } 762 763 static void 764 stge_dma_wait(struct stge_softc *sc) 765 { 766 int i; 767 768 for (i = 0; i < STGE_TIMEOUT; i++) { 769 delay(2); 770 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 771 DMAC_TxDMAInProg) == 0) 772 break; 773 } 774 775 if (i == STGE_TIMEOUT) 776 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 777 } 778 779 /* 780 * stge_start: [ifnet interface function] 781 * 782 * Start packet transmission on the interface. 783 */ 784 static void 785 stge_start(struct ifnet *ifp) 786 { 787 struct stge_softc *sc = ifp->if_softc; 788 struct mbuf *m0; 789 struct stge_descsoft *ds; 790 struct stge_tfd *tfd; 791 bus_dmamap_t dmamap; 792 int error, firsttx, nexttx, opending, seg, totlen; 793 uint64_t csum_flags; 794 795 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 796 return; 797 798 /* 799 * Remember the previous number of pending transmissions 800 * and the first descriptor we will use. 801 */ 802 opending = sc->sc_txpending; 803 firsttx = STGE_NEXTTX(sc->sc_txlast); 804 805 /* 806 * Loop through the send queue, setting up transmit descriptors 807 * until we drain the queue, or use up all available transmit 808 * descriptors. 809 */ 810 for (;;) { 811 uint64_t tfc; 812 bool have_vtag; 813 uint16_t vtag; 814 815 /* 816 * Grab a packet off the queue. 817 */ 818 IFQ_POLL(&ifp->if_snd, m0); 819 if (m0 == NULL) 820 break; 821 822 /* 823 * Leave one unused descriptor at the end of the 824 * list to prevent wrapping completely around. 825 */ 826 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 827 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 828 break; 829 } 830 831 /* 832 * See if we have any VLAN stuff. 833 */ 834 have_vtag = vlan_has_tag(m0); 835 if (have_vtag) 836 vtag = vlan_get_tag(m0); 837 838 /* 839 * Get the last and next available transmit descriptor. 840 */ 841 nexttx = STGE_NEXTTX(sc->sc_txlast); 842 tfd = &sc->sc_txdescs[nexttx]; 843 ds = &sc->sc_txsoft[nexttx]; 844 845 dmamap = ds->ds_dmamap; 846 847 /* 848 * Load the DMA map. If this fails, the packet either 849 * didn't fit in the alloted number of segments, or we 850 * were short on resources. For the too-many-segments 851 * case, we simply report an error and drop the packet, 852 * since we can't sanely copy a jumbo packet to a single 853 * buffer. 854 */ 855 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 856 BUS_DMA_NOWAIT); 857 if (error) { 858 if (error == EFBIG) { 859 printf("%s: Tx packet consumes too many " 860 "DMA segments, dropping...\n", 861 device_xname(sc->sc_dev)); 862 IFQ_DEQUEUE(&ifp->if_snd, m0); 863 m_freem(m0); 864 continue; 865 } 866 /* 867 * Short on resources, just stop for now. 868 */ 869 break; 870 } 871 872 IFQ_DEQUEUE(&ifp->if_snd, m0); 873 874 /* 875 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 876 */ 877 878 /* Sync the DMA map. */ 879 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 880 BUS_DMASYNC_PREWRITE); 881 882 /* Initialize the fragment list. */ 883 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 884 tfd->tfd_frags[seg].frag_word0 = 885 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 886 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 887 totlen += dmamap->dm_segs[seg].ds_len; 888 } 889 890 #ifdef STGE_EVENT_COUNTERS 891 switch (dmamap->dm_nsegs) { 892 case 1: 893 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 894 break; 895 case 2: 896 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 897 break; 898 case 3: 899 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 900 break; 901 case 4: 902 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 903 break; 904 case 5: 905 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 906 break; 907 default: 908 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 909 break; 910 } 911 #endif /* STGE_EVENT_COUNTERS */ 912 913 /* 914 * Initialize checksumming flags in the descriptor. 915 * Byte-swap constants so the compiler can optimize. 916 */ 917 csum_flags = 0; 918 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 919 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 920 csum_flags |= TFD_IPChecksumEnable; 921 } 922 923 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 924 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 925 csum_flags |= TFD_TCPChecksumEnable; 926 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 927 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 928 csum_flags |= TFD_UDPChecksumEnable; 929 } 930 931 /* 932 * Initialize the descriptor and give it to the chip. 933 * Check to see if we have a VLAN tag to insert. 934 */ 935 936 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 937 TFD_FragCount(seg) | csum_flags | 938 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 939 TFD_TxDMAIndicate : 0); 940 if (have_vtag) { 941 #if 0 942 struct ether_header *eh = 943 mtod(m0, struct ether_header *); 944 uint16_t etype = ntohs(eh->ether_type); 945 printf("%s: xmit (tag %d) etype %x\n", 946 ifp->if_xname, *mtod(n, int *), etype); 947 #endif 948 tfc |= TFD_VLANTagInsert | 949 #ifdef STGE_VLAN_CFI 950 TFD_CFI | 951 #endif 952 TFD_VID(vtag); 953 } 954 tfd->tfd_control = htole64(tfc); 955 956 /* Sync the descriptor. */ 957 STGE_CDTXSYNC(sc, nexttx, 958 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 959 960 /* 961 * Kick the transmit DMA logic. 962 */ 963 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 964 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 965 966 /* 967 * Store a pointer to the packet so we can free it later. 968 */ 969 ds->ds_mbuf = m0; 970 971 /* Advance the tx pointer. */ 972 sc->sc_txpending++; 973 sc->sc_txlast = nexttx; 974 975 /* 976 * Pass the packet to any BPF listeners. 977 */ 978 bpf_mtap(ifp, m0, BPF_D_OUT); 979 } 980 981 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 982 /* No more slots left; notify upper layer. */ 983 ifp->if_flags |= IFF_OACTIVE; 984 } 985 986 if (sc->sc_txpending != opending) { 987 /* 988 * We enqueued packets. If the transmitter was idle, 989 * reset the txdirty pointer. 990 */ 991 if (opending == 0) 992 sc->sc_txdirty = firsttx; 993 994 /* Set a watchdog timer in case the chip flakes out. */ 995 ifp->if_timer = 5; 996 } 997 } 998 999 /* 1000 * stge_watchdog: [ifnet interface function] 1001 * 1002 * Watchdog timer handler. 1003 */ 1004 static void 1005 stge_watchdog(struct ifnet *ifp) 1006 { 1007 struct stge_softc *sc = ifp->if_softc; 1008 1009 /* 1010 * Sweep up first, since we don't interrupt every frame. 1011 */ 1012 stge_txintr(sc); 1013 if (sc->sc_txpending != 0) { 1014 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1015 ifp->if_oerrors++; 1016 1017 (void) stge_init(ifp); 1018 1019 /* Try to get more packets going. */ 1020 stge_start(ifp); 1021 } 1022 } 1023 1024 /* 1025 * stge_ioctl: [ifnet interface function] 1026 * 1027 * Handle control requests from the operator. 1028 */ 1029 static int 1030 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1031 { 1032 struct stge_softc *sc = ifp->if_softc; 1033 int s, error; 1034 1035 s = splnet(); 1036 1037 error = ether_ioctl(ifp, cmd, data); 1038 if (error == ENETRESET) { 1039 error = 0; 1040 1041 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1042 ; 1043 else if (ifp->if_flags & IFF_RUNNING) { 1044 /* 1045 * Multicast list has changed; set the hardware filter 1046 * accordingly. 1047 */ 1048 stge_set_filter(sc); 1049 } 1050 } 1051 1052 /* Try to get more packets going. */ 1053 stge_start(ifp); 1054 1055 splx(s); 1056 return (error); 1057 } 1058 1059 /* 1060 * stge_intr: 1061 * 1062 * Interrupt service routine. 1063 */ 1064 static int 1065 stge_intr(void *arg) 1066 { 1067 struct stge_softc *sc = arg; 1068 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1069 uint32_t txstat; 1070 int wantinit; 1071 uint16_t isr; 1072 1073 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1074 IS_InterruptStatus) == 0) 1075 return (0); 1076 1077 for (wantinit = 0; wantinit == 0;) { 1078 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1079 if ((isr & sc->sc_IntEnable) == 0) 1080 break; 1081 1082 /* Host interface errors. */ 1083 if (isr & IS_HostError) { 1084 printf("%s: Host interface error\n", 1085 device_xname(sc->sc_dev)); 1086 wantinit = 1; 1087 continue; 1088 } 1089 1090 /* Receive interrupts. */ 1091 if (isr & (IS_RxDMAComplete | IS_RFDListEnd)) { 1092 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1093 stge_rxintr(sc); 1094 if (isr & IS_RFDListEnd) { 1095 printf("%s: receive ring overflow\n", 1096 device_xname(sc->sc_dev)); 1097 /* 1098 * XXX Should try to recover from this 1099 * XXX more gracefully. 1100 */ 1101 wantinit = 1; 1102 } 1103 } 1104 1105 /* Transmit interrupts. */ 1106 if (isr & (IS_TxDMAComplete | IS_TxComplete)) { 1107 #ifdef STGE_EVENT_COUNTERS 1108 if (isr & IS_TxDMAComplete) 1109 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1110 #endif 1111 stge_txintr(sc); 1112 } 1113 1114 /* Statistics overflow. */ 1115 if (isr & IS_UpdateStats) 1116 stge_stats_update(sc); 1117 1118 /* Transmission errors. */ 1119 if (isr & IS_TxComplete) { 1120 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1121 for (;;) { 1122 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1123 STGE_TxStatus); 1124 if ((txstat & TS_TxComplete) == 0) 1125 break; 1126 if (txstat & TS_TxUnderrun) { 1127 sc->sc_txthresh++; 1128 if (sc->sc_txthresh > 0x0fff) 1129 sc->sc_txthresh = 0x0fff; 1130 printf("%s: transmit underrun, new " 1131 "threshold: %d bytes\n", 1132 device_xname(sc->sc_dev), 1133 sc->sc_txthresh << 5); 1134 } 1135 if (txstat & TS_MaxCollisions) 1136 printf("%s: excessive collisions\n", 1137 device_xname(sc->sc_dev)); 1138 } 1139 wantinit = 1; 1140 } 1141 1142 } 1143 1144 if (wantinit) 1145 stge_init(ifp); 1146 1147 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1148 sc->sc_IntEnable); 1149 1150 /* Try to get more packets going. */ 1151 if_schedule_deferred_start(ifp); 1152 1153 return (1); 1154 } 1155 1156 /* 1157 * stge_txintr: 1158 * 1159 * Helper; handle transmit interrupts. 1160 */ 1161 static void 1162 stge_txintr(struct stge_softc *sc) 1163 { 1164 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1165 struct stge_descsoft *ds; 1166 uint64_t control; 1167 int i; 1168 1169 ifp->if_flags &= ~IFF_OACTIVE; 1170 1171 /* 1172 * Go through our Tx list and free mbufs for those 1173 * frames which have been transmitted. 1174 */ 1175 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1176 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1177 ds = &sc->sc_txsoft[i]; 1178 1179 STGE_CDTXSYNC(sc, i, 1180 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1181 1182 control = le64toh(sc->sc_txdescs[i].tfd_control); 1183 if ((control & TFD_TFDDone) == 0) 1184 break; 1185 1186 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1187 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1188 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1189 m_freem(ds->ds_mbuf); 1190 ds->ds_mbuf = NULL; 1191 } 1192 1193 /* Update the dirty transmit buffer pointer. */ 1194 sc->sc_txdirty = i; 1195 1196 /* 1197 * If there are no more pending transmissions, cancel the watchdog 1198 * timer. 1199 */ 1200 if (sc->sc_txpending == 0) 1201 ifp->if_timer = 0; 1202 } 1203 1204 /* 1205 * stge_rxintr: 1206 * 1207 * Helper; handle receive interrupts. 1208 */ 1209 static void 1210 stge_rxintr(struct stge_softc *sc) 1211 { 1212 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1213 struct stge_descsoft *ds; 1214 struct mbuf *m, *tailm; 1215 uint64_t status; 1216 int i, len; 1217 1218 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1219 ds = &sc->sc_rxsoft[i]; 1220 1221 STGE_CDRXSYNC(sc, i, 1222 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1223 1224 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1225 1226 if ((status & RFD_RFDDone) == 0) 1227 break; 1228 1229 if (__predict_false(sc->sc_rxdiscard)) { 1230 STGE_INIT_RXDESC(sc, i); 1231 if (status & RFD_FrameEnd) { 1232 /* Reset our state. */ 1233 sc->sc_rxdiscard = 0; 1234 } 1235 continue; 1236 } 1237 1238 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1239 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1240 1241 m = ds->ds_mbuf; 1242 1243 /* 1244 * Add a new receive buffer to the ring. 1245 */ 1246 if (stge_add_rxbuf(sc, i) != 0) { 1247 /* 1248 * Failed, throw away what we've done so 1249 * far, and discard the rest of the packet. 1250 */ 1251 ifp->if_ierrors++; 1252 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1253 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1254 STGE_INIT_RXDESC(sc, i); 1255 if ((status & RFD_FrameEnd) == 0) 1256 sc->sc_rxdiscard = 1; 1257 if (sc->sc_rxhead != NULL) 1258 m_freem(sc->sc_rxhead); 1259 STGE_RXCHAIN_RESET(sc); 1260 continue; 1261 } 1262 1263 #ifdef DIAGNOSTIC 1264 if (status & RFD_FrameStart) { 1265 KASSERT(sc->sc_rxhead == NULL); 1266 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1267 } 1268 #endif 1269 1270 STGE_RXCHAIN_LINK(sc, m); 1271 1272 /* 1273 * If this is not the end of the packet, keep 1274 * looking. 1275 */ 1276 if ((status & RFD_FrameEnd) == 0) { 1277 sc->sc_rxlen += m->m_len; 1278 continue; 1279 } 1280 1281 /* 1282 * Okay, we have the entire packet now... 1283 */ 1284 *sc->sc_rxtailp = NULL; 1285 m = sc->sc_rxhead; 1286 tailm = sc->sc_rxtail; 1287 1288 STGE_RXCHAIN_RESET(sc); 1289 1290 /* 1291 * If the packet had an error, drop it. Note we 1292 * count the error later in the periodic stats update. 1293 */ 1294 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1295 RFD_RxAlignmentError | RFD_RxFCSError | 1296 RFD_RxLengthError)) { 1297 m_freem(m); 1298 continue; 1299 } 1300 1301 /* 1302 * No errors. 1303 * 1304 * Note we have configured the chip to not include 1305 * the CRC at the end of the packet. 1306 */ 1307 len = RFD_RxDMAFrameLen(status); 1308 tailm->m_len = len - sc->sc_rxlen; 1309 1310 /* 1311 * If the packet is small enough to fit in a 1312 * single header mbuf, allocate one and copy 1313 * the data into it. This greatly reduces 1314 * memory consumption when we receive lots 1315 * of small packets. 1316 */ 1317 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1318 struct mbuf *nm; 1319 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1320 if (nm == NULL) { 1321 ifp->if_ierrors++; 1322 m_freem(m); 1323 continue; 1324 } 1325 nm->m_data += 2; 1326 nm->m_pkthdr.len = nm->m_len = len; 1327 m_copydata(m, 0, len, mtod(nm, void *)); 1328 m_freem(m); 1329 m = nm; 1330 } 1331 1332 /* 1333 * Set the incoming checksum information for the packet. 1334 */ 1335 if (status & RFD_IPDetected) { 1336 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1337 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1338 if (status & RFD_IPError) 1339 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1340 if (status & RFD_TCPDetected) { 1341 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1342 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1343 if (status & RFD_TCPError) 1344 m->m_pkthdr.csum_flags |= 1345 M_CSUM_TCP_UDP_BAD; 1346 } else if (status & RFD_UDPDetected) { 1347 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1348 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1349 if (status & RFD_UDPError) 1350 m->m_pkthdr.csum_flags |= 1351 M_CSUM_TCP_UDP_BAD; 1352 } 1353 } 1354 1355 m_set_rcvif(m, ifp); 1356 m->m_pkthdr.len = len; 1357 1358 /* 1359 * Pass this up to any BPF listeners, but only 1360 * pass if up the stack if it's for us. 1361 */ 1362 #ifdef STGE_VLAN_UNTAG 1363 /* 1364 * Check for VLAN tagged packets 1365 */ 1366 if (status & RFD_VLANDetected) 1367 vlan_set_tag(m, RFD_TCI(status)); 1368 1369 #endif 1370 #if 0 1371 if (status & RFD_VLANDetected) { 1372 struct ether_header *eh; 1373 uint16_t etype; 1374 1375 eh = mtod(m, struct ether_header *); 1376 etype = ntohs(eh->ether_type); 1377 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1378 ifp->if_xname, (uint16_t) RFD_TCI(status), 1379 etype); 1380 } 1381 #endif 1382 /* Pass it on. */ 1383 if_percpuq_enqueue(ifp->if_percpuq, m); 1384 } 1385 1386 /* Update the receive pointer. */ 1387 sc->sc_rxptr = i; 1388 } 1389 1390 /* 1391 * stge_tick: 1392 * 1393 * One second timer, used to tick the MII. 1394 */ 1395 static void 1396 stge_tick(void *arg) 1397 { 1398 struct stge_softc *sc = arg; 1399 int s; 1400 1401 s = splnet(); 1402 mii_tick(&sc->sc_mii); 1403 stge_stats_update(sc); 1404 splx(s); 1405 1406 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1407 } 1408 1409 /* 1410 * stge_stats_update: 1411 * 1412 * Read the TC9021 statistics counters. 1413 */ 1414 static void 1415 stge_stats_update(struct stge_softc *sc) 1416 { 1417 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1418 bus_space_tag_t st = sc->sc_st; 1419 bus_space_handle_t sh = sc->sc_sh; 1420 1421 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1422 1423 ifp->if_ipackets += 1424 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1425 1426 ifp->if_ierrors += 1427 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1428 1429 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1430 1431 ifp->if_opackets += 1432 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1433 1434 ifp->if_collisions += 1435 bus_space_read_4(st, sh, STGE_LateCollisions) + 1436 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1437 bus_space_read_4(st, sh, STGE_SingleColFrames); 1438 1439 ifp->if_oerrors += 1440 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1441 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1442 } 1443 1444 /* 1445 * stge_reset: 1446 * 1447 * Perform a soft reset on the TC9021. 1448 */ 1449 static void 1450 stge_reset(struct stge_softc *sc) 1451 { 1452 uint32_t ac; 1453 int i; 1454 1455 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1456 1457 /* 1458 * Only assert RstOut if we're fiber. We need GMII clocks 1459 * to be present in order for the reset to complete on fiber 1460 * cards. 1461 */ 1462 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1463 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1464 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1465 (sc->sc_usefiber ? AC_RstOut : 0)); 1466 1467 delay(50000); 1468 1469 for (i = 0; i < STGE_TIMEOUT; i++) { 1470 delay(5000); 1471 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1472 AC_ResetBusy) == 0) 1473 break; 1474 } 1475 1476 if (i == STGE_TIMEOUT) 1477 printf("%s: reset failed to complete\n", 1478 device_xname(sc->sc_dev)); 1479 1480 delay(1000); 1481 } 1482 1483 /* 1484 * stge_init: [ ifnet interface function ] 1485 * 1486 * Initialize the interface. Must be called at splnet(). 1487 */ 1488 static int 1489 stge_init(struct ifnet *ifp) 1490 { 1491 struct stge_softc *sc = ifp->if_softc; 1492 bus_space_tag_t st = sc->sc_st; 1493 bus_space_handle_t sh = sc->sc_sh; 1494 struct stge_descsoft *ds; 1495 int i, error = 0; 1496 1497 /* 1498 * Cancel any pending I/O. 1499 */ 1500 stge_stop(ifp, 0); 1501 1502 /* 1503 * Reset the chip to a known state. 1504 */ 1505 stge_reset(sc); 1506 1507 /* 1508 * Initialize the transmit descriptor ring. 1509 */ 1510 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1511 for (i = 0; i < STGE_NTXDESC; i++) { 1512 sc->sc_txdescs[i].tfd_next = htole64( 1513 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1514 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1515 } 1516 sc->sc_txpending = 0; 1517 sc->sc_txdirty = 0; 1518 sc->sc_txlast = STGE_NTXDESC - 1; 1519 1520 /* 1521 * Initialize the receive descriptor and receive job 1522 * descriptor rings. 1523 */ 1524 for (i = 0; i < STGE_NRXDESC; i++) { 1525 ds = &sc->sc_rxsoft[i]; 1526 if (ds->ds_mbuf == NULL) { 1527 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1528 printf("%s: unable to allocate or map rx " 1529 "buffer %d, error = %d\n", 1530 device_xname(sc->sc_dev), i, error); 1531 /* 1532 * XXX Should attempt to run with fewer receive 1533 * XXX buffers instead of just failing. 1534 */ 1535 stge_rxdrain(sc); 1536 goto out; 1537 } 1538 } else 1539 STGE_INIT_RXDESC(sc, i); 1540 } 1541 sc->sc_rxptr = 0; 1542 sc->sc_rxdiscard = 0; 1543 STGE_RXCHAIN_RESET(sc); 1544 1545 /* Set the station address. */ 1546 for (i = 0; i < 6; i++) 1547 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1548 CLLADDR(ifp->if_sadl)[i]); 1549 1550 /* 1551 * Set the statistics masks. Disable all the RMON stats, 1552 * and disable selected stats in the non-RMON stats registers. 1553 */ 1554 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1555 bus_space_write_4(st, sh, STGE_StatisticsMask, 1556 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1557 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1558 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1559 (1U << 21)); 1560 1561 /* Set up the receive filter. */ 1562 stge_set_filter(sc); 1563 1564 /* 1565 * Give the transmit and receive ring to the chip. 1566 */ 1567 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1568 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1569 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1570 1571 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1572 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1573 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1574 1575 /* 1576 * Initialize the Tx auto-poll period. It's OK to make this number 1577 * large (255 is the max, but we use 127) -- we explicitly kick the 1578 * transmit engine when there's actually a packet. 1579 */ 1580 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1581 1582 /* ..and the Rx auto-poll period. */ 1583 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1584 1585 /* Initialize the Tx start threshold. */ 1586 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1587 1588 /* RX DMA thresholds, from linux */ 1589 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1590 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1591 1592 /* 1593 * Initialize the Rx DMA interrupt control register. We 1594 * request an interrupt after every incoming packet, but 1595 * defer it for 32us (64 * 512 ns). When the number of 1596 * interrupts pending reaches 8, we stop deferring the 1597 * interrupt, and signal it immediately. 1598 */ 1599 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1600 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1601 1602 /* 1603 * Initialize the interrupt mask. 1604 */ 1605 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1606 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1607 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1608 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1609 1610 /* 1611 * Configure the DMA engine. 1612 * XXX Should auto-tune TxBurstLimit. 1613 */ 1614 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1615 DMAC_TxBurstLimit(3)); 1616 1617 /* 1618 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1619 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1620 * empty again. 1621 */ 1622 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1623 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1624 1625 /* 1626 * Set the maximum frame size. 1627 */ 1628 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1629 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1630 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1631 ETHER_VLAN_ENCAP_LEN : 0)); 1632 1633 /* 1634 * Initialize MacCtrl -- do it before setting the media, 1635 * as setting the media will actually program the register. 1636 * 1637 * Note: We have to poke the IFS value before poking 1638 * anything else. 1639 */ 1640 sc->sc_MACCtrl = MC_IFSSelect(0); 1641 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1642 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1643 #ifdef STGE_VLAN_UNTAG 1644 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1645 #endif 1646 1647 if (sc->sc_rev >= 6) { /* >= B.2 */ 1648 /* Multi-frag frame bug work-around. */ 1649 bus_space_write_2(st, sh, STGE_DebugCtrl, 1650 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1651 1652 /* Tx Poll Now bug work-around. */ 1653 bus_space_write_2(st, sh, STGE_DebugCtrl, 1654 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1655 /* XXX ? from linux */ 1656 bus_space_write_2(st, sh, STGE_DebugCtrl, 1657 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1658 } 1659 1660 /* 1661 * Set the current media. 1662 */ 1663 if ((error = ether_mediachange(ifp)) != 0) 1664 goto out; 1665 1666 /* 1667 * Start the one second MII clock. 1668 */ 1669 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1670 1671 /* 1672 * ...all done! 1673 */ 1674 ifp->if_flags |= IFF_RUNNING; 1675 ifp->if_flags &= ~IFF_OACTIVE; 1676 1677 out: 1678 if (error) 1679 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1680 return (error); 1681 } 1682 1683 /* 1684 * stge_drain: 1685 * 1686 * Drain the receive queue. 1687 */ 1688 static void 1689 stge_rxdrain(struct stge_softc *sc) 1690 { 1691 struct stge_descsoft *ds; 1692 int i; 1693 1694 for (i = 0; i < STGE_NRXDESC; i++) { 1695 ds = &sc->sc_rxsoft[i]; 1696 if (ds->ds_mbuf != NULL) { 1697 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1698 ds->ds_mbuf->m_next = NULL; 1699 m_freem(ds->ds_mbuf); 1700 ds->ds_mbuf = NULL; 1701 } 1702 } 1703 } 1704 1705 /* 1706 * stge_stop: [ ifnet interface function ] 1707 * 1708 * Stop transmission on the interface. 1709 */ 1710 static void 1711 stge_stop(struct ifnet *ifp, int disable) 1712 { 1713 struct stge_softc *sc = ifp->if_softc; 1714 struct stge_descsoft *ds; 1715 int i; 1716 1717 /* 1718 * Stop the one second clock. 1719 */ 1720 callout_stop(&sc->sc_tick_ch); 1721 1722 /* Down the MII. */ 1723 mii_down(&sc->sc_mii); 1724 1725 /* 1726 * Disable interrupts. 1727 */ 1728 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1729 1730 /* 1731 * Stop receiver, transmitter, and stats update. 1732 */ 1733 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1734 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1735 1736 /* 1737 * Stop the transmit and receive DMA. 1738 */ 1739 stge_dma_wait(sc); 1740 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1741 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1742 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1743 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1744 1745 /* 1746 * Release any queued transmit buffers. 1747 */ 1748 for (i = 0; i < STGE_NTXDESC; i++) { 1749 ds = &sc->sc_txsoft[i]; 1750 if (ds->ds_mbuf != NULL) { 1751 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1752 m_freem(ds->ds_mbuf); 1753 ds->ds_mbuf = NULL; 1754 } 1755 } 1756 1757 /* 1758 * Mark the interface down and cancel the watchdog timer. 1759 */ 1760 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1761 ifp->if_timer = 0; 1762 1763 if (disable) 1764 stge_rxdrain(sc); 1765 } 1766 1767 static int 1768 stge_eeprom_wait(struct stge_softc *sc) 1769 { 1770 int i; 1771 1772 for (i = 0; i < STGE_TIMEOUT; i++) { 1773 delay(1000); 1774 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1775 EC_EepromBusy) == 0) 1776 return (0); 1777 } 1778 return (1); 1779 } 1780 1781 /* 1782 * stge_read_eeprom: 1783 * 1784 * Read data from the serial EEPROM. 1785 */ 1786 static void 1787 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1788 { 1789 1790 if (stge_eeprom_wait(sc)) 1791 printf("%s: EEPROM failed to come ready\n", 1792 device_xname(sc->sc_dev)); 1793 1794 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1795 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1796 if (stge_eeprom_wait(sc)) 1797 printf("%s: EEPROM read timed out\n", 1798 device_xname(sc->sc_dev)); 1799 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1800 } 1801 1802 /* 1803 * stge_add_rxbuf: 1804 * 1805 * Add a receive buffer to the indicated descriptor. 1806 */ 1807 static int 1808 stge_add_rxbuf(struct stge_softc *sc, int idx) 1809 { 1810 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1811 struct mbuf *m; 1812 int error; 1813 1814 MGETHDR(m, M_DONTWAIT, MT_DATA); 1815 if (m == NULL) 1816 return (ENOBUFS); 1817 1818 MCLGET(m, M_DONTWAIT); 1819 if ((m->m_flags & M_EXT) == 0) { 1820 m_freem(m); 1821 return (ENOBUFS); 1822 } 1823 1824 m->m_data = m->m_ext.ext_buf + 2; 1825 m->m_len = MCLBYTES - 2; 1826 1827 if (ds->ds_mbuf != NULL) 1828 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1829 1830 ds->ds_mbuf = m; 1831 1832 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1833 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1834 if (error) { 1835 printf("%s: can't load rx DMA map %d, error = %d\n", 1836 device_xname(sc->sc_dev), idx, error); 1837 panic("stge_add_rxbuf"); /* XXX */ 1838 } 1839 1840 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1841 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1842 1843 STGE_INIT_RXDESC(sc, idx); 1844 1845 return (0); 1846 } 1847 1848 /* 1849 * stge_set_filter: 1850 * 1851 * Set up the receive filter. 1852 */ 1853 static void 1854 stge_set_filter(struct stge_softc *sc) 1855 { 1856 struct ethercom *ec = &sc->sc_ethercom; 1857 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1858 struct ether_multi *enm; 1859 struct ether_multistep step; 1860 uint32_t crc; 1861 uint32_t mchash[2]; 1862 1863 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1864 if (ifp->if_flags & IFF_BROADCAST) 1865 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1866 1867 /* XXX: ST1023 only works in promiscuous mode */ 1868 if (sc->sc_stge1023) 1869 ifp->if_flags |= IFF_PROMISC; 1870 1871 if (ifp->if_flags & IFF_PROMISC) { 1872 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1873 goto allmulti; 1874 } 1875 1876 /* 1877 * Set up the multicast address filter by passing all multicast 1878 * addresses through a CRC generator, and then using the low-order 1879 * 6 bits as an index into the 64 bit multicast hash table. The 1880 * high order bits select the register, while the rest of the bits 1881 * select the bit within the register. 1882 */ 1883 1884 memset(mchash, 0, sizeof(mchash)); 1885 1886 ETHER_LOCK(ec); 1887 ETHER_FIRST_MULTI(step, ec, enm); 1888 if (enm == NULL) { 1889 ETHER_UNLOCK(ec); 1890 goto done; 1891 } 1892 1893 while (enm != NULL) { 1894 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1895 /* 1896 * We must listen to a range of multicast addresses. 1897 * For now, just accept all multicasts, rather than 1898 * trying to set only those filter bits needed to match 1899 * the range. (At this time, the only use of address 1900 * ranges is for IP multicast routing, for which the 1901 * range is big enough to require all bits set.) 1902 */ 1903 ETHER_UNLOCK(ec); 1904 goto allmulti; 1905 } 1906 1907 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1908 1909 /* Just want the 6 least significant bits. */ 1910 crc &= 0x3f; 1911 1912 /* Set the corresponding bit in the hash table. */ 1913 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1914 1915 ETHER_NEXT_MULTI(step, enm); 1916 } 1917 ETHER_UNLOCK(ec); 1918 1919 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1920 1921 ifp->if_flags &= ~IFF_ALLMULTI; 1922 goto done; 1923 1924 allmulti: 1925 ifp->if_flags |= IFF_ALLMULTI; 1926 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1927 1928 done: 1929 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1930 /* 1931 * Program the multicast hash table. 1932 */ 1933 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1934 mchash[0]); 1935 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1936 mchash[1]); 1937 } 1938 1939 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1940 sc->sc_ReceiveMode); 1941 } 1942 1943 /* 1944 * stge_mii_readreg: [mii interface function] 1945 * 1946 * Read a PHY register on the MII of the TC9021. 1947 */ 1948 static int 1949 stge_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1950 { 1951 1952 return mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg, val); 1953 } 1954 1955 /* 1956 * stge_mii_writereg: [mii interface function] 1957 * 1958 * Write a PHY register on the MII of the TC9021. 1959 */ 1960 static int 1961 stge_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1962 { 1963 1964 return mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, 1965 val); 1966 } 1967 1968 /* 1969 * stge_mii_statchg: [mii interface function] 1970 * 1971 * Callback from MII layer when media changes. 1972 */ 1973 static void 1974 stge_mii_statchg(struct ifnet *ifp) 1975 { 1976 struct stge_softc *sc = ifp->if_softc; 1977 1978 if (sc->sc_mii.mii_media_active & IFM_FDX) 1979 sc->sc_MACCtrl |= MC_DuplexSelect; 1980 else 1981 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1982 1983 /* XXX 802.1x flow-control? */ 1984 1985 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1986 } 1987 1988 /* 1989 * sste_mii_bitbang_read: [mii bit-bang interface function] 1990 * 1991 * Read the MII serial port for the MII bit-bang module. 1992 */ 1993 static uint32_t 1994 stge_mii_bitbang_read(device_t self) 1995 { 1996 struct stge_softc *sc = device_private(self); 1997 1998 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1999 } 2000 2001 /* 2002 * stge_mii_bitbang_write: [mii big-bang interface function] 2003 * 2004 * Write the MII serial port for the MII bit-bang module. 2005 */ 2006 static void 2007 stge_mii_bitbang_write(device_t self, uint32_t val) 2008 { 2009 struct stge_softc *sc = device_private(self); 2010 2011 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 2012 val | sc->sc_PhyCtrl); 2013 } 2014