1 /* $NetBSD: if_ste.c,v 1.51 2018/06/26 06:48:01 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. ST-201 10/100 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.51 2018/06/26 06:48:01 msaitoh Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stereg.h> 72 73 /* 74 * Transmit descriptor list size. 75 */ 76 #define STE_NTXDESC 256 77 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 78 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 79 80 /* 81 * Receive descriptor list size. 82 */ 83 #define STE_NRXDESC 128 84 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 85 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 86 87 /* 88 * Control structures are DMA'd to the ST-201 chip. We allocate them in 89 * a single clump that maps to a single DMA segment to make several things 90 * easier. 91 */ 92 struct ste_control_data { 93 /* 94 * The transmit descriptors. 95 */ 96 struct ste_tfd scd_txdescs[STE_NTXDESC]; 97 98 /* 99 * The receive descriptors. 100 */ 101 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 102 }; 103 104 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 105 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 106 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 107 108 /* 109 * Software state for transmit and receive jobs. 110 */ 111 struct ste_descsoft { 112 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 113 bus_dmamap_t ds_dmamap; /* our DMA map */ 114 }; 115 116 /* 117 * Software state per device. 118 */ 119 struct ste_softc { 120 device_t sc_dev; /* generic device information */ 121 bus_space_tag_t sc_st; /* bus space tag */ 122 bus_space_handle_t sc_sh; /* bus space handle */ 123 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 124 struct ethercom sc_ethercom; /* ethernet common data */ 125 126 void *sc_ih; /* interrupt cookie */ 127 128 struct mii_data sc_mii; /* MII/media information */ 129 130 callout_t sc_tick_ch; /* tick callout */ 131 132 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 133 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 134 135 /* 136 * Software state for transmit and receive descriptors. 137 */ 138 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 139 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 140 141 /* 142 * Control data structures. 143 */ 144 struct ste_control_data *sc_control_data; 145 #define sc_txdescs sc_control_data->scd_txdescs 146 #define sc_rxdescs sc_control_data->scd_rxdescs 147 148 int sc_txpending; /* number of Tx requests pending */ 149 int sc_txdirty; /* first dirty Tx descriptor */ 150 int sc_txlast; /* last used Tx descriptor */ 151 152 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 153 154 int sc_txthresh; /* Tx threshold */ 155 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 156 uint16_t sc_IntEnable; /* prototype IntEnable register */ 157 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 158 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 159 }; 160 161 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 162 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 163 164 #define STE_CDTXSYNC(sc, x, ops) \ 165 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 166 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 167 168 #define STE_CDRXSYNC(sc, x, ops) \ 169 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 170 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 171 172 #define STE_INIT_RXDESC(sc, x) \ 173 do { \ 174 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 175 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 176 struct mbuf *__m = __ds->ds_mbuf; \ 177 \ 178 /* \ 179 * Note: We scoot the packet forward 2 bytes in the buffer \ 180 * so that the payload after the Ethernet header is aligned \ 181 * to a 4-byte boundary. \ 182 */ \ 183 __m->m_data = __m->m_ext.ext_buf + 2; \ 184 __rfd->rfd_frag.frag_addr = \ 185 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 186 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 187 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 188 __rfd->rfd_status = 0; \ 189 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 190 } while (/*CONSTCOND*/0) 191 192 #define STE_TIMEOUT 1000 193 194 static void ste_start(struct ifnet *); 195 static void ste_watchdog(struct ifnet *); 196 static int ste_ioctl(struct ifnet *, u_long, void *); 197 static int ste_init(struct ifnet *); 198 static void ste_stop(struct ifnet *, int); 199 200 static bool ste_shutdown(device_t, int); 201 202 static void ste_reset(struct ste_softc *, u_int32_t); 203 static void ste_setthresh(struct ste_softc *); 204 static void ste_txrestart(struct ste_softc *, u_int8_t); 205 static void ste_rxdrain(struct ste_softc *); 206 static int ste_add_rxbuf(struct ste_softc *, int); 207 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 208 static void ste_tick(void *); 209 210 static void ste_stats_update(struct ste_softc *); 211 212 static void ste_set_filter(struct ste_softc *); 213 214 static int ste_intr(void *); 215 static void ste_txintr(struct ste_softc *); 216 static void ste_rxintr(struct ste_softc *); 217 218 static int ste_mii_readreg(device_t, int, int); 219 static void ste_mii_writereg(device_t, int, int, int); 220 static void ste_mii_statchg(struct ifnet *); 221 222 static int ste_match(device_t, cfdata_t, void *); 223 static void ste_attach(device_t, device_t, void *); 224 225 int ste_copy_small = 0; 226 227 CFATTACH_DECL_NEW(ste, sizeof(struct ste_softc), 228 ste_match, ste_attach, NULL, NULL); 229 230 static uint32_t ste_mii_bitbang_read(device_t); 231 static void ste_mii_bitbang_write(device_t, uint32_t); 232 233 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 234 ste_mii_bitbang_read, 235 ste_mii_bitbang_write, 236 { 237 PC_MgmtData, /* MII_BIT_MDO */ 238 PC_MgmtData, /* MII_BIT_MDI */ 239 PC_MgmtClk, /* MII_BIT_MDC */ 240 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 241 0, /* MII_BIT_DIR_PHY_HOST */ 242 } 243 }; 244 245 /* 246 * Devices supported by this driver. 247 */ 248 static const struct ste_product { 249 pci_vendor_id_t ste_vendor; 250 pci_product_id_t ste_product; 251 const char *ste_name; 252 } ste_products[] = { 253 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 254 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 255 256 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 257 "Sundance ST-201 10/100 Ethernet" }, 258 259 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 260 "D-Link DL-1002 10/100 Ethernet" }, 261 262 { 0, 0, 263 NULL }, 264 }; 265 266 static const struct ste_product * 267 ste_lookup(const struct pci_attach_args *pa) 268 { 269 const struct ste_product *sp; 270 271 for (sp = ste_products; sp->ste_name != NULL; sp++) { 272 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 273 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 274 return (sp); 275 } 276 return (NULL); 277 } 278 279 static int 280 ste_match(device_t parent, cfdata_t cf, void *aux) 281 { 282 struct pci_attach_args *pa = aux; 283 284 if (ste_lookup(pa) != NULL) 285 return (1); 286 287 return (0); 288 } 289 290 static void 291 ste_attach(device_t parent, device_t self, void *aux) 292 { 293 struct ste_softc *sc = device_private(self); 294 struct pci_attach_args *pa = aux; 295 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 296 pci_chipset_tag_t pc = pa->pa_pc; 297 pci_intr_handle_t ih; 298 const char *intrstr = NULL; 299 bus_space_tag_t iot, memt; 300 bus_space_handle_t ioh, memh; 301 bus_dma_segment_t seg; 302 int ioh_valid, memh_valid; 303 int i, rseg, error; 304 const struct ste_product *sp; 305 uint8_t enaddr[ETHER_ADDR_LEN]; 306 uint16_t myea[ETHER_ADDR_LEN / 2]; 307 char intrbuf[PCI_INTRSTR_LEN]; 308 309 sc->sc_dev = self; 310 311 callout_init(&sc->sc_tick_ch, 0); 312 313 sp = ste_lookup(pa); 314 if (sp == NULL) { 315 printf("\n"); 316 panic("ste_attach: impossible"); 317 } 318 319 printf(": %s\n", sp->ste_name); 320 321 /* 322 * Map the device. 323 */ 324 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 325 PCI_MAPREG_TYPE_IO, 0, 326 &iot, &ioh, NULL, NULL) == 0); 327 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 328 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 329 &memt, &memh, NULL, NULL) == 0); 330 331 if (memh_valid) { 332 sc->sc_st = memt; 333 sc->sc_sh = memh; 334 } else if (ioh_valid) { 335 sc->sc_st = iot; 336 sc->sc_sh = ioh; 337 } else { 338 aprint_error_dev(self, "unable to map device registers\n"); 339 return; 340 } 341 342 sc->sc_dmat = pa->pa_dmat; 343 344 /* Enable bus mastering. */ 345 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 346 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 347 PCI_COMMAND_MASTER_ENABLE); 348 349 /* power up chip */ 350 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 351 NULL)) && error != EOPNOTSUPP) { 352 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 353 return; 354 } 355 356 /* 357 * Map and establish our interrupt. 358 */ 359 if (pci_intr_map(pa, &ih)) { 360 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 361 return; 362 } 363 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 364 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 365 if (sc->sc_ih == NULL) { 366 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 367 if (intrstr != NULL) 368 aprint_error(" at %s", intrstr); 369 aprint_error("\n"); 370 return; 371 } 372 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 373 374 /* 375 * Allocate the control data structures, and create and load the 376 * DMA map for it. 377 */ 378 if ((error = bus_dmamem_alloc(sc->sc_dmat, 379 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 380 0)) != 0) { 381 aprint_error_dev(sc->sc_dev, 382 "unable to allocate control data, error = %d\n", error); 383 goto fail_0; 384 } 385 386 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 387 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 388 BUS_DMA_COHERENT)) != 0) { 389 aprint_error_dev(sc->sc_dev, 390 "unable to map control data, error = %d\n", error); 391 goto fail_1; 392 } 393 394 if ((error = bus_dmamap_create(sc->sc_dmat, 395 sizeof(struct ste_control_data), 1, 396 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 397 aprint_error_dev(sc->sc_dev, 398 "unable to create control data DMA map, error = %d\n", 399 error); 400 goto fail_2; 401 } 402 403 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 404 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 405 0)) != 0) { 406 aprint_error_dev(sc->sc_dev, 407 "unable to load control data DMA map, error = %d\n", 408 error); 409 goto fail_3; 410 } 411 412 /* 413 * Create the transmit buffer DMA maps. 414 */ 415 for (i = 0; i < STE_NTXDESC; i++) { 416 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 417 STE_NTXFRAGS, MCLBYTES, 0, 0, 418 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 419 aprint_error_dev(sc->sc_dev, 420 "unable to create tx DMA map %d, error = %d\n", i, 421 error); 422 goto fail_4; 423 } 424 } 425 426 /* 427 * Create the receive buffer DMA maps. 428 */ 429 for (i = 0; i < STE_NRXDESC; i++) { 430 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 431 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 432 aprint_error_dev(sc->sc_dev, 433 "unable to create rx DMA map %d, error = %d\n", i, 434 error); 435 goto fail_5; 436 } 437 sc->sc_rxsoft[i].ds_mbuf = NULL; 438 } 439 440 /* 441 * Reset the chip to a known state. 442 */ 443 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 444 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 445 446 /* 447 * Read the Ethernet address from the EEPROM. 448 */ 449 for (i = 0; i < 3; i++) { 450 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 451 myea[i] = le16toh(myea[i]); 452 } 453 memcpy(enaddr, myea, sizeof(enaddr)); 454 455 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 456 ether_sprintf(enaddr)); 457 458 /* 459 * Initialize our media structures and probe the MII. 460 */ 461 sc->sc_mii.mii_ifp = ifp; 462 sc->sc_mii.mii_readreg = ste_mii_readreg; 463 sc->sc_mii.mii_writereg = ste_mii_writereg; 464 sc->sc_mii.mii_statchg = ste_mii_statchg; 465 sc->sc_ethercom.ec_mii = &sc->sc_mii; 466 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 467 ether_mediastatus); 468 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 469 MII_OFFSET_ANY, 0); 470 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 471 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0,NULL); 472 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 473 } else 474 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 475 476 ifp = &sc->sc_ethercom.ec_if; 477 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 478 ifp->if_softc = sc; 479 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 480 ifp->if_ioctl = ste_ioctl; 481 ifp->if_start = ste_start; 482 ifp->if_watchdog = ste_watchdog; 483 ifp->if_init = ste_init; 484 ifp->if_stop = ste_stop; 485 IFQ_SET_READY(&ifp->if_snd); 486 487 /* 488 * Default the transmit threshold to 128 bytes. 489 */ 490 sc->sc_txthresh = 128; 491 492 /* 493 * Disable MWI if the PCI layer tells us to. 494 */ 495 sc->sc_DMACtrl = 0; 496 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 497 sc->sc_DMACtrl |= DC_MWIDisable; 498 499 /* 500 * We can support 802.1Q VLAN-sized frames. 501 */ 502 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 503 504 /* 505 * Attach the interface. 506 */ 507 if_attach(ifp); 508 if_deferred_start_init(ifp, NULL); 509 ether_ifattach(ifp, enaddr); 510 511 /* 512 * Make sure the interface is shutdown during reboot. 513 */ 514 if (pmf_device_register1(self, NULL, NULL, ste_shutdown)) 515 pmf_class_network_register(self, ifp); 516 else 517 aprint_error_dev(self, "couldn't establish power handler\n"); 518 519 return; 520 521 /* 522 * Free any resources we've allocated during the failed attach 523 * attempt. Do this in reverse order and fall through. 524 */ 525 fail_5: 526 for (i = 0; i < STE_NRXDESC; i++) { 527 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 528 bus_dmamap_destroy(sc->sc_dmat, 529 sc->sc_rxsoft[i].ds_dmamap); 530 } 531 fail_4: 532 for (i = 0; i < STE_NTXDESC; i++) { 533 if (sc->sc_txsoft[i].ds_dmamap != NULL) 534 bus_dmamap_destroy(sc->sc_dmat, 535 sc->sc_txsoft[i].ds_dmamap); 536 } 537 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 538 fail_3: 539 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 540 fail_2: 541 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 542 sizeof(struct ste_control_data)); 543 fail_1: 544 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 545 fail_0: 546 return; 547 } 548 549 /* 550 * ste_shutdown: 551 * 552 * Make sure the interface is stopped at reboot time. 553 */ 554 static bool 555 ste_shutdown(device_t self, int howto) 556 { 557 struct ste_softc *sc; 558 559 sc = device_private(self); 560 ste_stop(&sc->sc_ethercom.ec_if, 1); 561 562 return true; 563 } 564 565 static void 566 ste_dmahalt_wait(struct ste_softc *sc) 567 { 568 int i; 569 570 for (i = 0; i < STE_TIMEOUT; i++) { 571 delay(2); 572 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 573 DC_DMAHaltBusy) == 0) 574 break; 575 } 576 577 if (i == STE_TIMEOUT) 578 printf("%s: DMA halt timed out\n", device_xname(sc->sc_dev)); 579 } 580 581 /* 582 * ste_start: [ifnet interface function] 583 * 584 * Start packet transmission on the interface. 585 */ 586 static void 587 ste_start(struct ifnet *ifp) 588 { 589 struct ste_softc *sc = ifp->if_softc; 590 struct mbuf *m0, *m; 591 struct ste_descsoft *ds; 592 struct ste_tfd *tfd; 593 bus_dmamap_t dmamap; 594 int error, olasttx, nexttx, opending, seg, totlen; 595 596 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 597 return; 598 599 /* 600 * Remember the previous number of pending transmissions 601 * and the current last descriptor in the list. 602 */ 603 opending = sc->sc_txpending; 604 olasttx = sc->sc_txlast; 605 606 /* 607 * Loop through the send queue, setting up transmit descriptors 608 * until we drain the queue, or use up all available transmit 609 * descriptors. 610 */ 611 while (sc->sc_txpending < STE_NTXDESC) { 612 /* 613 * Grab a packet off the queue. 614 */ 615 IFQ_POLL(&ifp->if_snd, m0); 616 if (m0 == NULL) 617 break; 618 m = NULL; 619 620 /* 621 * Get the last and next available transmit descriptor. 622 */ 623 nexttx = STE_NEXTTX(sc->sc_txlast); 624 tfd = &sc->sc_txdescs[nexttx]; 625 ds = &sc->sc_txsoft[nexttx]; 626 627 dmamap = ds->ds_dmamap; 628 629 /* 630 * Load the DMA map. If this fails, the packet either 631 * didn't fit in the alloted number of segments, or we 632 * were short on resources. In this case, we'll copy 633 * and try again. 634 */ 635 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 636 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 637 MGETHDR(m, M_DONTWAIT, MT_DATA); 638 if (m == NULL) { 639 printf("%s: unable to allocate Tx mbuf\n", 640 device_xname(sc->sc_dev)); 641 break; 642 } 643 if (m0->m_pkthdr.len > MHLEN) { 644 MCLGET(m, M_DONTWAIT); 645 if ((m->m_flags & M_EXT) == 0) { 646 printf("%s: unable to allocate Tx " 647 "cluster\n", 648 device_xname(sc->sc_dev)); 649 m_freem(m); 650 break; 651 } 652 } 653 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 654 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 655 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 656 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 657 if (error) { 658 printf("%s: unable to load Tx buffer, " 659 "error = %d\n", device_xname(sc->sc_dev), 660 error); 661 break; 662 } 663 } 664 665 IFQ_DEQUEUE(&ifp->if_snd, m0); 666 if (m != NULL) { 667 m_freem(m0); 668 m0 = m; 669 } 670 671 /* 672 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 673 */ 674 675 /* Sync the DMA map. */ 676 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 677 BUS_DMASYNC_PREWRITE); 678 679 /* Initialize the fragment list. */ 680 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 681 tfd->tfd_frags[seg].frag_addr = 682 htole32(dmamap->dm_segs[seg].ds_addr); 683 tfd->tfd_frags[seg].frag_len = 684 htole32(dmamap->dm_segs[seg].ds_len); 685 totlen += dmamap->dm_segs[seg].ds_len; 686 } 687 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 688 689 /* Initialize the descriptor. */ 690 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 691 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 692 693 /* Sync the descriptor. */ 694 STE_CDTXSYNC(sc, nexttx, 695 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 696 697 /* 698 * Store a pointer to the packet so we can free it later, 699 * and remember what txdirty will be once the packet is 700 * done. 701 */ 702 ds->ds_mbuf = m0; 703 704 /* Advance the tx pointer. */ 705 sc->sc_txpending++; 706 sc->sc_txlast = nexttx; 707 708 /* 709 * Pass the packet to any BPF listeners. 710 */ 711 bpf_mtap(ifp, m0, BPF_D_OUT); 712 } 713 714 if (sc->sc_txpending == STE_NTXDESC) { 715 /* No more slots left; notify upper layer. */ 716 ifp->if_flags |= IFF_OACTIVE; 717 } 718 719 if (sc->sc_txpending != opending) { 720 /* 721 * We enqueued packets. If the transmitter was idle, 722 * reset the txdirty pointer. 723 */ 724 if (opending == 0) 725 sc->sc_txdirty = STE_NEXTTX(olasttx); 726 727 /* 728 * Cause a descriptor interrupt to happen on the 729 * last packet we enqueued, and also cause the 730 * DMA engine to wait after is has finished processing 731 * it. 732 */ 733 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 734 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 735 htole32(TFD_TxDMAIndicate); 736 STE_CDTXSYNC(sc, sc->sc_txlast, 737 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 738 739 /* 740 * Link up the new chain of descriptors to the 741 * last. 742 */ 743 sc->sc_txdescs[olasttx].tfd_next = 744 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 745 STE_CDTXSYNC(sc, olasttx, 746 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 747 748 /* 749 * Kick the transmit DMA logic. Note that since we're 750 * using auto-polling, reading the Tx desc pointer will 751 * give it the nudge it needs to get going. 752 */ 753 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 754 STE_TxDMAListPtr) == 0) { 755 bus_space_write_4(sc->sc_st, sc->sc_sh, 756 STE_DMACtrl, DC_TxDMAHalt); 757 ste_dmahalt_wait(sc); 758 bus_space_write_4(sc->sc_st, sc->sc_sh, 759 STE_TxDMAListPtr, 760 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 761 bus_space_write_4(sc->sc_st, sc->sc_sh, 762 STE_DMACtrl, DC_TxDMAResume); 763 } 764 765 /* Set a watchdog timer in case the chip flakes out. */ 766 ifp->if_timer = 5; 767 } 768 } 769 770 /* 771 * ste_watchdog: [ifnet interface function] 772 * 773 * Watchdog timer handler. 774 */ 775 static void 776 ste_watchdog(struct ifnet *ifp) 777 { 778 struct ste_softc *sc = ifp->if_softc; 779 780 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 781 ifp->if_oerrors++; 782 783 ste_txintr(sc); 784 ste_rxintr(sc); 785 (void) ste_init(ifp); 786 787 /* Try to get more packets going. */ 788 ste_start(ifp); 789 } 790 791 /* 792 * ste_ioctl: [ifnet interface function] 793 * 794 * Handle control requests from the operator. 795 */ 796 static int 797 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 798 { 799 struct ste_softc *sc = ifp->if_softc; 800 int s, error; 801 802 s = splnet(); 803 804 error = ether_ioctl(ifp, cmd, data); 805 if (error == ENETRESET) { 806 /* 807 * Multicast list has changed; set the hardware filter 808 * accordingly. 809 */ 810 if (ifp->if_flags & IFF_RUNNING) 811 ste_set_filter(sc); 812 error = 0; 813 } 814 815 /* Try to get more packets going. */ 816 ste_start(ifp); 817 818 splx(s); 819 return (error); 820 } 821 822 /* 823 * ste_intr: 824 * 825 * Interrupt service routine. 826 */ 827 static int 828 ste_intr(void *arg) 829 { 830 struct ste_softc *sc = arg; 831 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 832 uint16_t isr; 833 uint8_t txstat; 834 int wantinit; 835 836 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 837 IS_InterruptStatus) == 0) 838 return (0); 839 840 for (wantinit = 0; wantinit == 0;) { 841 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 842 if ((isr & sc->sc_IntEnable) == 0) 843 break; 844 845 /* Receive interrupts. */ 846 if (isr & IE_RxDMAComplete) 847 ste_rxintr(sc); 848 849 /* Transmit interrupts. */ 850 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 851 ste_txintr(sc); 852 853 /* Statistics overflow. */ 854 if (isr & IE_UpdateStats) 855 ste_stats_update(sc); 856 857 /* Transmission errors. */ 858 if (isr & IE_TxComplete) { 859 for (;;) { 860 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 861 STE_TxStatus); 862 if ((txstat & TS_TxComplete) == 0) 863 break; 864 if (txstat & TS_TxUnderrun) { 865 sc->sc_txthresh += 32; 866 if (sc->sc_txthresh > 0x1ffc) 867 sc->sc_txthresh = 0x1ffc; 868 printf("%s: transmit underrun, new " 869 "threshold: %d bytes\n", 870 device_xname(sc->sc_dev), 871 sc->sc_txthresh); 872 ste_reset(sc, AC_TxReset | AC_DMA | 873 AC_FIFO | AC_Network); 874 ste_setthresh(sc); 875 bus_space_write_1(sc->sc_st, sc->sc_sh, 876 STE_TxDMAPollPeriod, 127); 877 ste_txrestart(sc, 878 bus_space_read_1(sc->sc_st, 879 sc->sc_sh, STE_TxFrameId)); 880 } 881 if (txstat & TS_TxReleaseError) { 882 printf("%s: Tx FIFO release error\n", 883 device_xname(sc->sc_dev)); 884 wantinit = 1; 885 } 886 if (txstat & TS_MaxCollisions) { 887 printf("%s: excessive collisions\n", 888 device_xname(sc->sc_dev)); 889 wantinit = 1; 890 } 891 if (txstat & TS_TxStatusOverflow) { 892 printf("%s: status overflow\n", 893 device_xname(sc->sc_dev)); 894 wantinit = 1; 895 } 896 bus_space_write_2(sc->sc_st, sc->sc_sh, 897 STE_TxStatus, 0); 898 } 899 } 900 901 /* Host interface errors. */ 902 if (isr & IE_HostError) { 903 printf("%s: Host interface error\n", 904 device_xname(sc->sc_dev)); 905 wantinit = 1; 906 } 907 } 908 909 if (wantinit) 910 ste_init(ifp); 911 912 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 913 sc->sc_IntEnable); 914 915 /* Try to get more packets going. */ 916 if_schedule_deferred_start(ifp); 917 918 return (1); 919 } 920 921 /* 922 * ste_txintr: 923 * 924 * Helper; handle transmit interrupts. 925 */ 926 static void 927 ste_txintr(struct ste_softc *sc) 928 { 929 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 930 struct ste_descsoft *ds; 931 uint32_t control; 932 int i; 933 934 ifp->if_flags &= ~IFF_OACTIVE; 935 936 /* 937 * Go through our Tx list and free mbufs for those 938 * frames which have been transmitted. 939 */ 940 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 941 i = STE_NEXTTX(i), sc->sc_txpending--) { 942 ds = &sc->sc_txsoft[i]; 943 944 STE_CDTXSYNC(sc, i, 945 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 946 947 control = le32toh(sc->sc_txdescs[i].tfd_control); 948 if ((control & TFD_TxDMAComplete) == 0) 949 break; 950 951 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 952 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 953 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 954 m_freem(ds->ds_mbuf); 955 ds->ds_mbuf = NULL; 956 } 957 958 /* Update the dirty transmit buffer pointer. */ 959 sc->sc_txdirty = i; 960 961 /* 962 * If there are no more pending transmissions, cancel the watchdog 963 * timer. 964 */ 965 if (sc->sc_txpending == 0) 966 ifp->if_timer = 0; 967 } 968 969 /* 970 * ste_rxintr: 971 * 972 * Helper; handle receive interrupts. 973 */ 974 static void 975 ste_rxintr(struct ste_softc *sc) 976 { 977 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 978 struct ste_descsoft *ds; 979 struct mbuf *m; 980 uint32_t status; 981 int i, len; 982 983 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 984 ds = &sc->sc_rxsoft[i]; 985 986 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 987 988 status = le32toh(sc->sc_rxdescs[i].rfd_status); 989 990 if ((status & RFD_RxDMAComplete) == 0) 991 break; 992 993 /* 994 * If the packet had an error, simply recycle the 995 * buffer. Note, we count the error later in the 996 * periodic stats update. 997 */ 998 if (status & RFD_RxFrameError) { 999 STE_INIT_RXDESC(sc, i); 1000 continue; 1001 } 1002 1003 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1004 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1005 1006 /* 1007 * No errors; receive the packet. Note, we have 1008 * configured the chip to not include the CRC at 1009 * the end of the packet. 1010 */ 1011 len = RFD_RxDMAFrameLen(status); 1012 1013 /* 1014 * If the packet is small enough to fit in a 1015 * single header mbuf, allocate one and copy 1016 * the data into it. This greatly reduces 1017 * memory consumption when we receive lots 1018 * of small packets. 1019 * 1020 * Otherwise, we add a new buffer to the receive 1021 * chain. If this fails, we drop the packet and 1022 * recycle the old buffer. 1023 */ 1024 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1025 MGETHDR(m, M_DONTWAIT, MT_DATA); 1026 if (m == NULL) 1027 goto dropit; 1028 m->m_data += 2; 1029 memcpy(mtod(m, void *), 1030 mtod(ds->ds_mbuf, void *), len); 1031 STE_INIT_RXDESC(sc, i); 1032 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1033 ds->ds_dmamap->dm_mapsize, 1034 BUS_DMASYNC_PREREAD); 1035 } else { 1036 m = ds->ds_mbuf; 1037 if (ste_add_rxbuf(sc, i) != 0) { 1038 dropit: 1039 ifp->if_ierrors++; 1040 STE_INIT_RXDESC(sc, i); 1041 bus_dmamap_sync(sc->sc_dmat, 1042 ds->ds_dmamap, 0, 1043 ds->ds_dmamap->dm_mapsize, 1044 BUS_DMASYNC_PREREAD); 1045 continue; 1046 } 1047 } 1048 1049 m_set_rcvif(m, ifp); 1050 m->m_pkthdr.len = m->m_len = len; 1051 1052 /* Pass it on. */ 1053 if_percpuq_enqueue(ifp->if_percpuq, m); 1054 } 1055 1056 /* Update the receive pointer. */ 1057 sc->sc_rxptr = i; 1058 } 1059 1060 /* 1061 * ste_tick: 1062 * 1063 * One second timer, used to tick the MII. 1064 */ 1065 static void 1066 ste_tick(void *arg) 1067 { 1068 struct ste_softc *sc = arg; 1069 int s; 1070 1071 s = splnet(); 1072 mii_tick(&sc->sc_mii); 1073 ste_stats_update(sc); 1074 splx(s); 1075 1076 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1077 } 1078 1079 /* 1080 * ste_stats_update: 1081 * 1082 * Read the ST-201 statistics counters. 1083 */ 1084 static void 1085 ste_stats_update(struct ste_softc *sc) 1086 { 1087 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1088 bus_space_tag_t st = sc->sc_st; 1089 bus_space_handle_t sh = sc->sc_sh; 1090 1091 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1092 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1093 1094 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1095 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1096 1097 ifp->if_opackets += 1098 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1099 ifp->if_ipackets += 1100 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1101 1102 ifp->if_collisions += 1103 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1104 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1105 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1106 1107 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1108 1109 ifp->if_ierrors += 1110 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1111 1112 ifp->if_oerrors += 1113 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1114 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1115 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1116 1117 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1118 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1119 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1120 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1121 } 1122 1123 /* 1124 * ste_reset: 1125 * 1126 * Perform a soft reset on the ST-201. 1127 */ 1128 static void 1129 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1130 { 1131 uint32_t ac; 1132 int i; 1133 1134 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1135 1136 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1137 1138 delay(50000); 1139 1140 for (i = 0; i < STE_TIMEOUT; i++) { 1141 delay(1000); 1142 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1143 AC_ResetBusy) == 0) 1144 break; 1145 } 1146 1147 if (i == STE_TIMEOUT) 1148 printf("%s: reset failed to complete\n", 1149 device_xname(sc->sc_dev)); 1150 1151 delay(1000); 1152 } 1153 1154 /* 1155 * ste_setthresh: 1156 * 1157 * set the various transmit threshold registers 1158 */ 1159 static void 1160 ste_setthresh(struct ste_softc *sc) 1161 { 1162 /* set the TX threhold */ 1163 bus_space_write_2(sc->sc_st, sc->sc_sh, 1164 STE_TxStartThresh, sc->sc_txthresh); 1165 /* Urgent threshold: set to sc_txthresh / 2 */ 1166 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1167 sc->sc_txthresh >> 6); 1168 /* Burst threshold: use default value (256 bytes) */ 1169 } 1170 1171 /* 1172 * restart TX at the given frame ID in the transmitter ring 1173 */ 1174 static void 1175 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1176 { 1177 u_int32_t control; 1178 1179 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1180 control = le32toh(sc->sc_txdescs[id].tfd_control); 1181 control &= ~TFD_TxDMAComplete; 1182 sc->sc_txdescs[id].tfd_control = htole32(control); 1183 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1184 1185 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1186 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1187 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1188 ste_dmahalt_wait(sc); 1189 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1190 STE_CDTXADDR(sc, id)); 1191 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1192 } 1193 1194 /* 1195 * ste_init: [ ifnet interface function ] 1196 * 1197 * Initialize the interface. Must be called at splnet(). 1198 */ 1199 static int 1200 ste_init(struct ifnet *ifp) 1201 { 1202 struct ste_softc *sc = ifp->if_softc; 1203 bus_space_tag_t st = sc->sc_st; 1204 bus_space_handle_t sh = sc->sc_sh; 1205 struct ste_descsoft *ds; 1206 int i, error = 0; 1207 1208 /* 1209 * Cancel any pending I/O. 1210 */ 1211 ste_stop(ifp, 0); 1212 1213 /* 1214 * Reset the chip to a known state. 1215 */ 1216 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1217 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1218 1219 /* 1220 * Initialize the transmit descriptor ring. 1221 */ 1222 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1223 sc->sc_txpending = 0; 1224 sc->sc_txdirty = 0; 1225 sc->sc_txlast = STE_NTXDESC - 1; 1226 1227 /* 1228 * Initialize the receive descriptor and receive job 1229 * descriptor rings. 1230 */ 1231 for (i = 0; i < STE_NRXDESC; i++) { 1232 ds = &sc->sc_rxsoft[i]; 1233 if (ds->ds_mbuf == NULL) { 1234 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1235 printf("%s: unable to allocate or map rx " 1236 "buffer %d, error = %d\n", 1237 device_xname(sc->sc_dev), i, error); 1238 /* 1239 * XXX Should attempt to run with fewer receive 1240 * XXX buffers instead of just failing. 1241 */ 1242 ste_rxdrain(sc); 1243 goto out; 1244 } 1245 } else 1246 STE_INIT_RXDESC(sc, i); 1247 } 1248 sc->sc_rxptr = 0; 1249 1250 /* Set the station address. */ 1251 for (i = 0; i < ETHER_ADDR_LEN; i++) 1252 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1253 CLLADDR(ifp->if_sadl)[i]); 1254 1255 /* Set up the receive filter. */ 1256 ste_set_filter(sc); 1257 1258 /* 1259 * Give the receive ring to the chip. 1260 */ 1261 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1262 STE_CDRXADDR(sc, sc->sc_rxptr)); 1263 1264 /* 1265 * We defer giving the transmit ring to the chip until we 1266 * transmit the first packet. 1267 */ 1268 1269 /* 1270 * Initialize the Tx auto-poll period. It's OK to make this number 1271 * large (127 is the max) -- we explicitly kick the transmit engine 1272 * when there's actually a packet. We are using auto-polling only 1273 * to make the interface to the transmit engine not suck. 1274 */ 1275 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1276 1277 /* ..and the Rx auto-poll period. */ 1278 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1279 1280 /* Initialize the Tx start threshold. */ 1281 ste_setthresh(sc); 1282 1283 /* Set the FIFO release threshold to 512 bytes. */ 1284 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1285 1286 /* Set maximum packet size for VLAN. */ 1287 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1288 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1289 else 1290 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1291 1292 /* 1293 * Initialize the interrupt mask. 1294 */ 1295 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1296 IE_TxDMAComplete | IE_RxDMAComplete; 1297 1298 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1299 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1300 1301 /* 1302 * Start the receive DMA engine. 1303 */ 1304 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1305 1306 /* 1307 * Initialize MacCtrl0 -- do it before setting the media, 1308 * as setting the media will actually program the register. 1309 */ 1310 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1311 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1312 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1313 1314 /* 1315 * Set the current media. 1316 */ 1317 if ((error = ether_mediachange(ifp)) != 0) 1318 goto out; 1319 1320 /* 1321 * Start the MAC. 1322 */ 1323 bus_space_write_2(st, sh, STE_MacCtrl1, 1324 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1325 1326 /* 1327 * Start the one second MII clock. 1328 */ 1329 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1330 1331 /* 1332 * ...all done! 1333 */ 1334 ifp->if_flags |= IFF_RUNNING; 1335 ifp->if_flags &= ~IFF_OACTIVE; 1336 1337 out: 1338 if (error) 1339 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1340 return (error); 1341 } 1342 1343 /* 1344 * ste_drain: 1345 * 1346 * Drain the receive queue. 1347 */ 1348 static void 1349 ste_rxdrain(struct ste_softc *sc) 1350 { 1351 struct ste_descsoft *ds; 1352 int i; 1353 1354 for (i = 0; i < STE_NRXDESC; i++) { 1355 ds = &sc->sc_rxsoft[i]; 1356 if (ds->ds_mbuf != NULL) { 1357 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1358 m_freem(ds->ds_mbuf); 1359 ds->ds_mbuf = NULL; 1360 } 1361 } 1362 } 1363 1364 /* 1365 * ste_stop: [ ifnet interface function ] 1366 * 1367 * Stop transmission on the interface. 1368 */ 1369 static void 1370 ste_stop(struct ifnet *ifp, int disable) 1371 { 1372 struct ste_softc *sc = ifp->if_softc; 1373 struct ste_descsoft *ds; 1374 int i; 1375 1376 /* 1377 * Stop the one second clock. 1378 */ 1379 callout_stop(&sc->sc_tick_ch); 1380 1381 /* Down the MII. */ 1382 mii_down(&sc->sc_mii); 1383 1384 /* 1385 * Disable interrupts. 1386 */ 1387 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1388 1389 /* 1390 * Stop receiver, transmitter, and stats update. 1391 */ 1392 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1393 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1394 1395 /* 1396 * Stop the transmit and receive DMA. 1397 */ 1398 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1399 DC_RxDMAHalt | DC_TxDMAHalt); 1400 ste_dmahalt_wait(sc); 1401 1402 /* 1403 * Release any queued transmit buffers. 1404 */ 1405 for (i = 0; i < STE_NTXDESC; i++) { 1406 ds = &sc->sc_txsoft[i]; 1407 if (ds->ds_mbuf != NULL) { 1408 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1409 m_freem(ds->ds_mbuf); 1410 ds->ds_mbuf = NULL; 1411 } 1412 } 1413 1414 /* 1415 * Mark the interface down and cancel the watchdog timer. 1416 */ 1417 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1418 ifp->if_timer = 0; 1419 1420 if (disable) 1421 ste_rxdrain(sc); 1422 } 1423 1424 static int 1425 ste_eeprom_wait(struct ste_softc *sc) 1426 { 1427 int i; 1428 1429 for (i = 0; i < STE_TIMEOUT; i++) { 1430 delay(1000); 1431 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1432 EC_EepromBusy) == 0) 1433 return (0); 1434 } 1435 return (1); 1436 } 1437 1438 /* 1439 * ste_read_eeprom: 1440 * 1441 * Read data from the serial EEPROM. 1442 */ 1443 static void 1444 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1445 { 1446 1447 if (ste_eeprom_wait(sc)) 1448 printf("%s: EEPROM failed to come ready\n", 1449 device_xname(sc->sc_dev)); 1450 1451 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1452 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1453 if (ste_eeprom_wait(sc)) 1454 printf("%s: EEPROM read timed out\n", 1455 device_xname(sc->sc_dev)); 1456 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1457 } 1458 1459 /* 1460 * ste_add_rxbuf: 1461 * 1462 * Add a receive buffer to the indicated descriptor. 1463 */ 1464 static int 1465 ste_add_rxbuf(struct ste_softc *sc, int idx) 1466 { 1467 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1468 struct mbuf *m; 1469 int error; 1470 1471 MGETHDR(m, M_DONTWAIT, MT_DATA); 1472 if (m == NULL) 1473 return (ENOBUFS); 1474 1475 MCLGET(m, M_DONTWAIT); 1476 if ((m->m_flags & M_EXT) == 0) { 1477 m_freem(m); 1478 return (ENOBUFS); 1479 } 1480 1481 if (ds->ds_mbuf != NULL) 1482 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1483 1484 ds->ds_mbuf = m; 1485 1486 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1487 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1488 BUS_DMA_READ|BUS_DMA_NOWAIT); 1489 if (error) { 1490 printf("%s: can't load rx DMA map %d, error = %d\n", 1491 device_xname(sc->sc_dev), idx, error); 1492 panic("ste_add_rxbuf"); /* XXX */ 1493 } 1494 1495 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1496 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1497 1498 STE_INIT_RXDESC(sc, idx); 1499 1500 return (0); 1501 } 1502 1503 /* 1504 * ste_set_filter: 1505 * 1506 * Set up the receive filter. 1507 */ 1508 static void 1509 ste_set_filter(struct ste_softc *sc) 1510 { 1511 struct ethercom *ec = &sc->sc_ethercom; 1512 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1513 struct ether_multi *enm; 1514 struct ether_multistep step; 1515 uint32_t crc; 1516 uint16_t mchash[4]; 1517 1518 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1519 if (ifp->if_flags & IFF_BROADCAST) 1520 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1521 1522 if (ifp->if_flags & IFF_PROMISC) { 1523 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1524 goto allmulti; 1525 } 1526 1527 /* 1528 * Set up the multicast address filter by passing all multicast 1529 * addresses through a CRC generator, and then using the low-order 1530 * 6 bits as an index into the 64 bit multicast hash table. The 1531 * high order bits select the register, while the rest of the bits 1532 * select the bit within the register. 1533 */ 1534 1535 memset(mchash, 0, sizeof(mchash)); 1536 1537 ETHER_FIRST_MULTI(step, ec, enm); 1538 if (enm == NULL) 1539 goto done; 1540 1541 while (enm != NULL) { 1542 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1543 /* 1544 * We must listen to a range of multicast addresses. 1545 * For now, just accept all multicasts, rather than 1546 * trying to set only those filter bits needed to match 1547 * the range. (At this time, the only use of address 1548 * ranges is for IP multicast routing, for which the 1549 * range is big enough to require all bits set.) 1550 */ 1551 goto allmulti; 1552 } 1553 1554 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1555 1556 /* Just want the 6 least significant bits. */ 1557 crc &= 0x3f; 1558 1559 /* Set the corresponding bit in the hash table. */ 1560 mchash[crc >> 4] |= 1 << (crc & 0xf); 1561 1562 ETHER_NEXT_MULTI(step, enm); 1563 } 1564 1565 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1566 1567 ifp->if_flags &= ~IFF_ALLMULTI; 1568 goto done; 1569 1570 allmulti: 1571 ifp->if_flags |= IFF_ALLMULTI; 1572 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1573 1574 done: 1575 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1576 /* 1577 * Program the multicast hash table. 1578 */ 1579 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1580 mchash[0]); 1581 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1582 mchash[1]); 1583 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1584 mchash[2]); 1585 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1586 mchash[3]); 1587 } 1588 1589 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1590 sc->sc_ReceiveMode); 1591 } 1592 1593 /* 1594 * ste_mii_readreg: [mii interface function] 1595 * 1596 * Read a PHY register on the MII of the ST-201. 1597 */ 1598 static int 1599 ste_mii_readreg(device_t self, int phy, int reg) 1600 { 1601 1602 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1603 } 1604 1605 /* 1606 * ste_mii_writereg: [mii interface function] 1607 * 1608 * Write a PHY register on the MII of the ST-201. 1609 */ 1610 static void 1611 ste_mii_writereg(device_t self, int phy, int reg, int val) 1612 { 1613 1614 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1615 } 1616 1617 /* 1618 * ste_mii_statchg: [mii interface function] 1619 * 1620 * Callback from MII layer when media changes. 1621 */ 1622 static void 1623 ste_mii_statchg(struct ifnet *ifp) 1624 { 1625 struct ste_softc *sc = ifp->if_softc; 1626 1627 if (sc->sc_mii.mii_media_active & IFM_FDX) 1628 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1629 else 1630 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1631 1632 /* XXX 802.1x flow-control? */ 1633 1634 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1635 } 1636 1637 /* 1638 * ste_mii_bitbang_read: [mii bit-bang interface function] 1639 * 1640 * Read the MII serial port for the MII bit-bang module. 1641 */ 1642 static uint32_t 1643 ste_mii_bitbang_read(device_t self) 1644 { 1645 struct ste_softc *sc = device_private(self); 1646 1647 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1648 } 1649 1650 /* 1651 * ste_mii_bitbang_write: [mii big-bang interface function] 1652 * 1653 * Write the MII serial port for the MII bit-bang module. 1654 */ 1655 static void 1656 ste_mii_bitbang_write(device_t self, uint32_t val) 1657 { 1658 struct ste_softc *sc = device_private(self); 1659 1660 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1661 } 1662