1 /* $NetBSD: if_ste.c,v 1.45 2014/03/29 19:28:25 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. ST-201 10/100 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.45 2014/03/29 19:28:25 christos Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stereg.h> 72 73 /* 74 * Transmit descriptor list size. 75 */ 76 #define STE_NTXDESC 256 77 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 78 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 79 80 /* 81 * Receive descriptor list size. 82 */ 83 #define STE_NRXDESC 128 84 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 85 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 86 87 /* 88 * Control structures are DMA'd to the ST-201 chip. We allocate them in 89 * a single clump that maps to a single DMA segment to make several things 90 * easier. 91 */ 92 struct ste_control_data { 93 /* 94 * The transmit descriptors. 95 */ 96 struct ste_tfd scd_txdescs[STE_NTXDESC]; 97 98 /* 99 * The receive descriptors. 100 */ 101 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 102 }; 103 104 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 105 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 106 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 107 108 /* 109 * Software state for transmit and receive jobs. 110 */ 111 struct ste_descsoft { 112 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 113 bus_dmamap_t ds_dmamap; /* our DMA map */ 114 }; 115 116 /* 117 * Software state per device. 118 */ 119 struct ste_softc { 120 device_t sc_dev; /* generic device information */ 121 bus_space_tag_t sc_st; /* bus space tag */ 122 bus_space_handle_t sc_sh; /* bus space handle */ 123 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 124 struct ethercom sc_ethercom; /* ethernet common data */ 125 126 void *sc_ih; /* interrupt cookie */ 127 128 struct mii_data sc_mii; /* MII/media information */ 129 130 callout_t sc_tick_ch; /* tick callout */ 131 132 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 133 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 134 135 /* 136 * Software state for transmit and receive descriptors. 137 */ 138 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 139 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 140 141 /* 142 * Control data structures. 143 */ 144 struct ste_control_data *sc_control_data; 145 #define sc_txdescs sc_control_data->scd_txdescs 146 #define sc_rxdescs sc_control_data->scd_rxdescs 147 148 int sc_txpending; /* number of Tx requests pending */ 149 int sc_txdirty; /* first dirty Tx descriptor */ 150 int sc_txlast; /* last used Tx descriptor */ 151 152 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 153 154 int sc_txthresh; /* Tx threshold */ 155 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 156 uint16_t sc_IntEnable; /* prototype IntEnable register */ 157 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 158 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 159 }; 160 161 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 162 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 163 164 #define STE_CDTXSYNC(sc, x, ops) \ 165 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 166 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 167 168 #define STE_CDRXSYNC(sc, x, ops) \ 169 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 170 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 171 172 #define STE_INIT_RXDESC(sc, x) \ 173 do { \ 174 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 175 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 176 struct mbuf *__m = __ds->ds_mbuf; \ 177 \ 178 /* \ 179 * Note: We scoot the packet forward 2 bytes in the buffer \ 180 * so that the payload after the Ethernet header is aligned \ 181 * to a 4-byte boundary. \ 182 */ \ 183 __m->m_data = __m->m_ext.ext_buf + 2; \ 184 __rfd->rfd_frag.frag_addr = \ 185 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 186 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 187 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 188 __rfd->rfd_status = 0; \ 189 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 190 } while (/*CONSTCOND*/0) 191 192 #define STE_TIMEOUT 1000 193 194 static void ste_start(struct ifnet *); 195 static void ste_watchdog(struct ifnet *); 196 static int ste_ioctl(struct ifnet *, u_long, void *); 197 static int ste_init(struct ifnet *); 198 static void ste_stop(struct ifnet *, int); 199 200 static bool ste_shutdown(device_t, int); 201 202 static void ste_reset(struct ste_softc *, u_int32_t); 203 static void ste_setthresh(struct ste_softc *); 204 static void ste_txrestart(struct ste_softc *, u_int8_t); 205 static void ste_rxdrain(struct ste_softc *); 206 static int ste_add_rxbuf(struct ste_softc *, int); 207 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 208 static void ste_tick(void *); 209 210 static void ste_stats_update(struct ste_softc *); 211 212 static void ste_set_filter(struct ste_softc *); 213 214 static int ste_intr(void *); 215 static void ste_txintr(struct ste_softc *); 216 static void ste_rxintr(struct ste_softc *); 217 218 static int ste_mii_readreg(device_t, int, int); 219 static void ste_mii_writereg(device_t, int, int, int); 220 static void ste_mii_statchg(struct ifnet *); 221 222 static int ste_match(device_t, cfdata_t, void *); 223 static void ste_attach(device_t, device_t, void *); 224 225 int ste_copy_small = 0; 226 227 CFATTACH_DECL_NEW(ste, sizeof(struct ste_softc), 228 ste_match, ste_attach, NULL, NULL); 229 230 static uint32_t ste_mii_bitbang_read(device_t); 231 static void ste_mii_bitbang_write(device_t, uint32_t); 232 233 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 234 ste_mii_bitbang_read, 235 ste_mii_bitbang_write, 236 { 237 PC_MgmtData, /* MII_BIT_MDO */ 238 PC_MgmtData, /* MII_BIT_MDI */ 239 PC_MgmtClk, /* MII_BIT_MDC */ 240 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 241 0, /* MII_BIT_DIR_PHY_HOST */ 242 } 243 }; 244 245 /* 246 * Devices supported by this driver. 247 */ 248 static const struct ste_product { 249 pci_vendor_id_t ste_vendor; 250 pci_product_id_t ste_product; 251 const char *ste_name; 252 } ste_products[] = { 253 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 254 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 255 256 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 257 "Sundance ST-201 10/100 Ethernet" }, 258 259 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 260 "D-Link DL-1002 10/100 Ethernet" }, 261 262 { 0, 0, 263 NULL }, 264 }; 265 266 static const struct ste_product * 267 ste_lookup(const struct pci_attach_args *pa) 268 { 269 const struct ste_product *sp; 270 271 for (sp = ste_products; sp->ste_name != NULL; sp++) { 272 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 273 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 274 return (sp); 275 } 276 return (NULL); 277 } 278 279 static int 280 ste_match(device_t parent, cfdata_t cf, void *aux) 281 { 282 struct pci_attach_args *pa = aux; 283 284 if (ste_lookup(pa) != NULL) 285 return (1); 286 287 return (0); 288 } 289 290 static void 291 ste_attach(device_t parent, device_t self, void *aux) 292 { 293 struct ste_softc *sc = device_private(self); 294 struct pci_attach_args *pa = aux; 295 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 296 pci_chipset_tag_t pc = pa->pa_pc; 297 pci_intr_handle_t ih; 298 const char *intrstr = NULL; 299 bus_space_tag_t iot, memt; 300 bus_space_handle_t ioh, memh; 301 bus_dma_segment_t seg; 302 int ioh_valid, memh_valid; 303 int i, rseg, error; 304 const struct ste_product *sp; 305 uint8_t enaddr[ETHER_ADDR_LEN]; 306 uint16_t myea[ETHER_ADDR_LEN / 2]; 307 char intrbuf[PCI_INTRSTR_LEN]; 308 309 sc->sc_dev = self; 310 311 callout_init(&sc->sc_tick_ch, 0); 312 313 sp = ste_lookup(pa); 314 if (sp == NULL) { 315 printf("\n"); 316 panic("ste_attach: impossible"); 317 } 318 319 printf(": %s\n", sp->ste_name); 320 321 /* 322 * Map the device. 323 */ 324 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 325 PCI_MAPREG_TYPE_IO, 0, 326 &iot, &ioh, NULL, NULL) == 0); 327 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 328 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 329 &memt, &memh, NULL, NULL) == 0); 330 331 if (memh_valid) { 332 sc->sc_st = memt; 333 sc->sc_sh = memh; 334 } else if (ioh_valid) { 335 sc->sc_st = iot; 336 sc->sc_sh = ioh; 337 } else { 338 aprint_error_dev(self, "unable to map device registers\n"); 339 return; 340 } 341 342 sc->sc_dmat = pa->pa_dmat; 343 344 /* Enable bus mastering. */ 345 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 346 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 347 PCI_COMMAND_MASTER_ENABLE); 348 349 /* power up chip */ 350 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 351 NULL)) && error != EOPNOTSUPP) { 352 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", 353 error); 354 return; 355 } 356 357 /* 358 * Map and establish our interrupt. 359 */ 360 if (pci_intr_map(pa, &ih)) { 361 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 362 return; 363 } 364 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 365 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 366 if (sc->sc_ih == NULL) { 367 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 368 if (intrstr != NULL) 369 aprint_error(" at %s", intrstr); 370 aprint_error("\n"); 371 return; 372 } 373 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 374 375 /* 376 * Allocate the control data structures, and create and load the 377 * DMA map for it. 378 */ 379 if ((error = bus_dmamem_alloc(sc->sc_dmat, 380 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 381 0)) != 0) { 382 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", 383 error); 384 goto fail_0; 385 } 386 387 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 388 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 389 BUS_DMA_COHERENT)) != 0) { 390 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 391 error); 392 goto fail_1; 393 } 394 395 if ((error = bus_dmamap_create(sc->sc_dmat, 396 sizeof(struct ste_control_data), 1, 397 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 398 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 399 "error = %d\n", error); 400 goto fail_2; 401 } 402 403 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 404 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 405 0)) != 0) { 406 aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, error = %d\n", 407 error); 408 goto fail_3; 409 } 410 411 /* 412 * Create the transmit buffer DMA maps. 413 */ 414 for (i = 0; i < STE_NTXDESC; i++) { 415 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 416 STE_NTXFRAGS, MCLBYTES, 0, 0, 417 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 418 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 419 "error = %d\n", i, error); 420 goto fail_4; 421 } 422 } 423 424 /* 425 * Create the receive buffer DMA maps. 426 */ 427 for (i = 0; i < STE_NRXDESC; i++) { 428 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 429 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 430 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 431 "error = %d\n", i, error); 432 goto fail_5; 433 } 434 sc->sc_rxsoft[i].ds_mbuf = NULL; 435 } 436 437 /* 438 * Reset the chip to a known state. 439 */ 440 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 441 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 442 443 /* 444 * Read the Ethernet address from the EEPROM. 445 */ 446 for (i = 0; i < 3; i++) { 447 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 448 myea[i] = le16toh(myea[i]); 449 } 450 memcpy(enaddr, myea, sizeof(enaddr)); 451 452 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 453 ether_sprintf(enaddr)); 454 455 /* 456 * Initialize our media structures and probe the MII. 457 */ 458 sc->sc_mii.mii_ifp = ifp; 459 sc->sc_mii.mii_readreg = ste_mii_readreg; 460 sc->sc_mii.mii_writereg = ste_mii_writereg; 461 sc->sc_mii.mii_statchg = ste_mii_statchg; 462 sc->sc_ethercom.ec_mii = &sc->sc_mii; 463 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 464 ether_mediastatus); 465 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 466 MII_OFFSET_ANY, 0); 467 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 468 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 469 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 470 } else 471 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 472 473 ifp = &sc->sc_ethercom.ec_if; 474 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 475 ifp->if_softc = sc; 476 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 477 ifp->if_ioctl = ste_ioctl; 478 ifp->if_start = ste_start; 479 ifp->if_watchdog = ste_watchdog; 480 ifp->if_init = ste_init; 481 ifp->if_stop = ste_stop; 482 IFQ_SET_READY(&ifp->if_snd); 483 484 /* 485 * Default the transmit threshold to 128 bytes. 486 */ 487 sc->sc_txthresh = 128; 488 489 /* 490 * Disable MWI if the PCI layer tells us to. 491 */ 492 sc->sc_DMACtrl = 0; 493 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 494 sc->sc_DMACtrl |= DC_MWIDisable; 495 496 /* 497 * We can support 802.1Q VLAN-sized frames. 498 */ 499 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 500 501 /* 502 * Attach the interface. 503 */ 504 if_attach(ifp); 505 ether_ifattach(ifp, enaddr); 506 507 /* 508 * Make sure the interface is shutdown during reboot. 509 */ 510 if (pmf_device_register1(self, NULL, NULL, ste_shutdown)) 511 pmf_class_network_register(self, ifp); 512 else 513 aprint_error_dev(self, "couldn't establish power handler\n"); 514 515 return; 516 517 /* 518 * Free any resources we've allocated during the failed attach 519 * attempt. Do this in reverse order and fall through. 520 */ 521 fail_5: 522 for (i = 0; i < STE_NRXDESC; i++) { 523 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 524 bus_dmamap_destroy(sc->sc_dmat, 525 sc->sc_rxsoft[i].ds_dmamap); 526 } 527 fail_4: 528 for (i = 0; i < STE_NTXDESC; i++) { 529 if (sc->sc_txsoft[i].ds_dmamap != NULL) 530 bus_dmamap_destroy(sc->sc_dmat, 531 sc->sc_txsoft[i].ds_dmamap); 532 } 533 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 534 fail_3: 535 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 536 fail_2: 537 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 538 sizeof(struct ste_control_data)); 539 fail_1: 540 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 541 fail_0: 542 return; 543 } 544 545 /* 546 * ste_shutdown: 547 * 548 * Make sure the interface is stopped at reboot time. 549 */ 550 static bool 551 ste_shutdown(device_t self, int howto) 552 { 553 struct ste_softc *sc; 554 555 sc = device_private(self); 556 ste_stop(&sc->sc_ethercom.ec_if, 1); 557 558 return true; 559 } 560 561 static void 562 ste_dmahalt_wait(struct ste_softc *sc) 563 { 564 int i; 565 566 for (i = 0; i < STE_TIMEOUT; i++) { 567 delay(2); 568 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 569 DC_DMAHaltBusy) == 0) 570 break; 571 } 572 573 if (i == STE_TIMEOUT) 574 printf("%s: DMA halt timed out\n", device_xname(sc->sc_dev)); 575 } 576 577 /* 578 * ste_start: [ifnet interface function] 579 * 580 * Start packet transmission on the interface. 581 */ 582 static void 583 ste_start(struct ifnet *ifp) 584 { 585 struct ste_softc *sc = ifp->if_softc; 586 struct mbuf *m0, *m; 587 struct ste_descsoft *ds; 588 struct ste_tfd *tfd; 589 bus_dmamap_t dmamap; 590 int error, olasttx, nexttx, opending, seg, totlen; 591 592 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 593 return; 594 595 /* 596 * Remember the previous number of pending transmissions 597 * and the current last descriptor in the list. 598 */ 599 opending = sc->sc_txpending; 600 olasttx = sc->sc_txlast; 601 602 /* 603 * Loop through the send queue, setting up transmit descriptors 604 * until we drain the queue, or use up all available transmit 605 * descriptors. 606 */ 607 while (sc->sc_txpending < STE_NTXDESC) { 608 /* 609 * Grab a packet off the queue. 610 */ 611 IFQ_POLL(&ifp->if_snd, m0); 612 if (m0 == NULL) 613 break; 614 m = NULL; 615 616 /* 617 * Get the last and next available transmit descriptor. 618 */ 619 nexttx = STE_NEXTTX(sc->sc_txlast); 620 tfd = &sc->sc_txdescs[nexttx]; 621 ds = &sc->sc_txsoft[nexttx]; 622 623 dmamap = ds->ds_dmamap; 624 625 /* 626 * Load the DMA map. If this fails, the packet either 627 * didn't fit in the alloted number of segments, or we 628 * were short on resources. In this case, we'll copy 629 * and try again. 630 */ 631 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 632 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 633 MGETHDR(m, M_DONTWAIT, MT_DATA); 634 if (m == NULL) { 635 printf("%s: unable to allocate Tx mbuf\n", 636 device_xname(sc->sc_dev)); 637 break; 638 } 639 if (m0->m_pkthdr.len > MHLEN) { 640 MCLGET(m, M_DONTWAIT); 641 if ((m->m_flags & M_EXT) == 0) { 642 printf("%s: unable to allocate Tx " 643 "cluster\n", device_xname(sc->sc_dev)); 644 m_freem(m); 645 break; 646 } 647 } 648 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 649 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 650 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 651 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 652 if (error) { 653 printf("%s: unable to load Tx buffer, " 654 "error = %d\n", device_xname(sc->sc_dev), error); 655 break; 656 } 657 } 658 659 IFQ_DEQUEUE(&ifp->if_snd, m0); 660 if (m != NULL) { 661 m_freem(m0); 662 m0 = m; 663 } 664 665 /* 666 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 667 */ 668 669 /* Sync the DMA map. */ 670 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 671 BUS_DMASYNC_PREWRITE); 672 673 /* Initialize the fragment list. */ 674 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 675 tfd->tfd_frags[seg].frag_addr = 676 htole32(dmamap->dm_segs[seg].ds_addr); 677 tfd->tfd_frags[seg].frag_len = 678 htole32(dmamap->dm_segs[seg].ds_len); 679 totlen += dmamap->dm_segs[seg].ds_len; 680 } 681 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 682 683 /* Initialize the descriptor. */ 684 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 685 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 686 687 /* Sync the descriptor. */ 688 STE_CDTXSYNC(sc, nexttx, 689 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 690 691 /* 692 * Store a pointer to the packet so we can free it later, 693 * and remember what txdirty will be once the packet is 694 * done. 695 */ 696 ds->ds_mbuf = m0; 697 698 /* Advance the tx pointer. */ 699 sc->sc_txpending++; 700 sc->sc_txlast = nexttx; 701 702 /* 703 * Pass the packet to any BPF listeners. 704 */ 705 bpf_mtap(ifp, m0); 706 } 707 708 if (sc->sc_txpending == STE_NTXDESC) { 709 /* No more slots left; notify upper layer. */ 710 ifp->if_flags |= IFF_OACTIVE; 711 } 712 713 if (sc->sc_txpending != opending) { 714 /* 715 * We enqueued packets. If the transmitter was idle, 716 * reset the txdirty pointer. 717 */ 718 if (opending == 0) 719 sc->sc_txdirty = STE_NEXTTX(olasttx); 720 721 /* 722 * Cause a descriptor interrupt to happen on the 723 * last packet we enqueued, and also cause the 724 * DMA engine to wait after is has finished processing 725 * it. 726 */ 727 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 728 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 729 htole32(TFD_TxDMAIndicate); 730 STE_CDTXSYNC(sc, sc->sc_txlast, 731 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 732 733 /* 734 * Link up the new chain of descriptors to the 735 * last. 736 */ 737 sc->sc_txdescs[olasttx].tfd_next = 738 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 739 STE_CDTXSYNC(sc, olasttx, 740 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 741 742 /* 743 * Kick the transmit DMA logic. Note that since we're 744 * using auto-polling, reading the Tx desc pointer will 745 * give it the nudge it needs to get going. 746 */ 747 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 748 STE_TxDMAListPtr) == 0) { 749 bus_space_write_4(sc->sc_st, sc->sc_sh, 750 STE_DMACtrl, DC_TxDMAHalt); 751 ste_dmahalt_wait(sc); 752 bus_space_write_4(sc->sc_st, sc->sc_sh, 753 STE_TxDMAListPtr, 754 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 755 bus_space_write_4(sc->sc_st, sc->sc_sh, 756 STE_DMACtrl, DC_TxDMAResume); 757 } 758 759 /* Set a watchdog timer in case the chip flakes out. */ 760 ifp->if_timer = 5; 761 } 762 } 763 764 /* 765 * ste_watchdog: [ifnet interface function] 766 * 767 * Watchdog timer handler. 768 */ 769 static void 770 ste_watchdog(struct ifnet *ifp) 771 { 772 struct ste_softc *sc = ifp->if_softc; 773 774 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 775 ifp->if_oerrors++; 776 777 ste_txintr(sc); 778 ste_rxintr(sc); 779 (void) ste_init(ifp); 780 781 /* Try to get more packets going. */ 782 ste_start(ifp); 783 } 784 785 /* 786 * ste_ioctl: [ifnet interface function] 787 * 788 * Handle control requests from the operator. 789 */ 790 static int 791 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 792 { 793 struct ste_softc *sc = ifp->if_softc; 794 int s, error; 795 796 s = splnet(); 797 798 error = ether_ioctl(ifp, cmd, data); 799 if (error == ENETRESET) { 800 /* 801 * Multicast list has changed; set the hardware filter 802 * accordingly. 803 */ 804 if (ifp->if_flags & IFF_RUNNING) 805 ste_set_filter(sc); 806 error = 0; 807 } 808 809 /* Try to get more packets going. */ 810 ste_start(ifp); 811 812 splx(s); 813 return (error); 814 } 815 816 /* 817 * ste_intr: 818 * 819 * Interrupt service routine. 820 */ 821 static int 822 ste_intr(void *arg) 823 { 824 struct ste_softc *sc = arg; 825 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 826 uint16_t isr; 827 uint8_t txstat; 828 int wantinit; 829 830 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 831 IS_InterruptStatus) == 0) 832 return (0); 833 834 for (wantinit = 0; wantinit == 0;) { 835 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 836 if ((isr & sc->sc_IntEnable) == 0) 837 break; 838 839 /* Receive interrupts. */ 840 if (isr & IE_RxDMAComplete) 841 ste_rxintr(sc); 842 843 /* Transmit interrupts. */ 844 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 845 ste_txintr(sc); 846 847 /* Statistics overflow. */ 848 if (isr & IE_UpdateStats) 849 ste_stats_update(sc); 850 851 /* Transmission errors. */ 852 if (isr & IE_TxComplete) { 853 for (;;) { 854 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 855 STE_TxStatus); 856 if ((txstat & TS_TxComplete) == 0) 857 break; 858 if (txstat & TS_TxUnderrun) { 859 sc->sc_txthresh += 32; 860 if (sc->sc_txthresh > 0x1ffc) 861 sc->sc_txthresh = 0x1ffc; 862 printf("%s: transmit underrun, new " 863 "threshold: %d bytes\n", 864 device_xname(sc->sc_dev), 865 sc->sc_txthresh); 866 ste_reset(sc, AC_TxReset | AC_DMA | 867 AC_FIFO | AC_Network); 868 ste_setthresh(sc); 869 bus_space_write_1(sc->sc_st, sc->sc_sh, 870 STE_TxDMAPollPeriod, 127); 871 ste_txrestart(sc, 872 bus_space_read_1(sc->sc_st, 873 sc->sc_sh, STE_TxFrameId)); 874 } 875 if (txstat & TS_TxReleaseError) { 876 printf("%s: Tx FIFO release error\n", 877 device_xname(sc->sc_dev)); 878 wantinit = 1; 879 } 880 if (txstat & TS_MaxCollisions) { 881 printf("%s: excessive collisions\n", 882 device_xname(sc->sc_dev)); 883 wantinit = 1; 884 } 885 if (txstat & TS_TxStatusOverflow) { 886 printf("%s: status overflow\n", 887 device_xname(sc->sc_dev)); 888 wantinit = 1; 889 } 890 bus_space_write_2(sc->sc_st, sc->sc_sh, 891 STE_TxStatus, 0); 892 } 893 } 894 895 /* Host interface errors. */ 896 if (isr & IE_HostError) { 897 printf("%s: Host interface error\n", 898 device_xname(sc->sc_dev)); 899 wantinit = 1; 900 } 901 } 902 903 if (wantinit) 904 ste_init(ifp); 905 906 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 907 sc->sc_IntEnable); 908 909 /* Try to get more packets going. */ 910 ste_start(ifp); 911 912 return (1); 913 } 914 915 /* 916 * ste_txintr: 917 * 918 * Helper; handle transmit interrupts. 919 */ 920 static void 921 ste_txintr(struct ste_softc *sc) 922 { 923 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 924 struct ste_descsoft *ds; 925 uint32_t control; 926 int i; 927 928 ifp->if_flags &= ~IFF_OACTIVE; 929 930 /* 931 * Go through our Tx list and free mbufs for those 932 * frames which have been transmitted. 933 */ 934 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 935 i = STE_NEXTTX(i), sc->sc_txpending--) { 936 ds = &sc->sc_txsoft[i]; 937 938 STE_CDTXSYNC(sc, i, 939 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 940 941 control = le32toh(sc->sc_txdescs[i].tfd_control); 942 if ((control & TFD_TxDMAComplete) == 0) 943 break; 944 945 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 946 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 947 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 948 m_freem(ds->ds_mbuf); 949 ds->ds_mbuf = NULL; 950 } 951 952 /* Update the dirty transmit buffer pointer. */ 953 sc->sc_txdirty = i; 954 955 /* 956 * If there are no more pending transmissions, cancel the watchdog 957 * timer. 958 */ 959 if (sc->sc_txpending == 0) 960 ifp->if_timer = 0; 961 } 962 963 /* 964 * ste_rxintr: 965 * 966 * Helper; handle receive interrupts. 967 */ 968 static void 969 ste_rxintr(struct ste_softc *sc) 970 { 971 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 972 struct ste_descsoft *ds; 973 struct mbuf *m; 974 uint32_t status; 975 int i, len; 976 977 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 978 ds = &sc->sc_rxsoft[i]; 979 980 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 981 982 status = le32toh(sc->sc_rxdescs[i].rfd_status); 983 984 if ((status & RFD_RxDMAComplete) == 0) 985 break; 986 987 /* 988 * If the packet had an error, simply recycle the 989 * buffer. Note, we count the error later in the 990 * periodic stats update. 991 */ 992 if (status & RFD_RxFrameError) { 993 STE_INIT_RXDESC(sc, i); 994 continue; 995 } 996 997 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 998 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 999 1000 /* 1001 * No errors; receive the packet. Note, we have 1002 * configured the chip to not include the CRC at 1003 * the end of the packet. 1004 */ 1005 len = RFD_RxDMAFrameLen(status); 1006 1007 /* 1008 * If the packet is small enough to fit in a 1009 * single header mbuf, allocate one and copy 1010 * the data into it. This greatly reduces 1011 * memory consumption when we receive lots 1012 * of small packets. 1013 * 1014 * Otherwise, we add a new buffer to the receive 1015 * chain. If this fails, we drop the packet and 1016 * recycle the old buffer. 1017 */ 1018 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1019 MGETHDR(m, M_DONTWAIT, MT_DATA); 1020 if (m == NULL) 1021 goto dropit; 1022 m->m_data += 2; 1023 memcpy(mtod(m, void *), 1024 mtod(ds->ds_mbuf, void *), len); 1025 STE_INIT_RXDESC(sc, i); 1026 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1027 ds->ds_dmamap->dm_mapsize, 1028 BUS_DMASYNC_PREREAD); 1029 } else { 1030 m = ds->ds_mbuf; 1031 if (ste_add_rxbuf(sc, i) != 0) { 1032 dropit: 1033 ifp->if_ierrors++; 1034 STE_INIT_RXDESC(sc, i); 1035 bus_dmamap_sync(sc->sc_dmat, 1036 ds->ds_dmamap, 0, 1037 ds->ds_dmamap->dm_mapsize, 1038 BUS_DMASYNC_PREREAD); 1039 continue; 1040 } 1041 } 1042 1043 m->m_pkthdr.rcvif = ifp; 1044 m->m_pkthdr.len = m->m_len = len; 1045 1046 /* 1047 * Pass this up to any BPF listeners, but only 1048 * pass if up the stack if it's for us. 1049 */ 1050 bpf_mtap(ifp, m); 1051 1052 /* Pass it on. */ 1053 (*ifp->if_input)(ifp, m); 1054 } 1055 1056 /* Update the receive pointer. */ 1057 sc->sc_rxptr = i; 1058 } 1059 1060 /* 1061 * ste_tick: 1062 * 1063 * One second timer, used to tick the MII. 1064 */ 1065 static void 1066 ste_tick(void *arg) 1067 { 1068 struct ste_softc *sc = arg; 1069 int s; 1070 1071 s = splnet(); 1072 mii_tick(&sc->sc_mii); 1073 ste_stats_update(sc); 1074 splx(s); 1075 1076 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1077 } 1078 1079 /* 1080 * ste_stats_update: 1081 * 1082 * Read the ST-201 statistics counters. 1083 */ 1084 static void 1085 ste_stats_update(struct ste_softc *sc) 1086 { 1087 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1088 bus_space_tag_t st = sc->sc_st; 1089 bus_space_handle_t sh = sc->sc_sh; 1090 1091 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1092 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1093 1094 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1095 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1096 1097 ifp->if_opackets += 1098 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1099 ifp->if_ipackets += 1100 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1101 1102 ifp->if_collisions += 1103 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1104 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1105 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1106 1107 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1108 1109 ifp->if_ierrors += 1110 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1111 1112 ifp->if_oerrors += 1113 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1114 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1115 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1116 1117 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1118 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1119 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1120 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1121 } 1122 1123 /* 1124 * ste_reset: 1125 * 1126 * Perform a soft reset on the ST-201. 1127 */ 1128 static void 1129 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1130 { 1131 uint32_t ac; 1132 int i; 1133 1134 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1135 1136 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1137 1138 delay(50000); 1139 1140 for (i = 0; i < STE_TIMEOUT; i++) { 1141 delay(1000); 1142 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1143 AC_ResetBusy) == 0) 1144 break; 1145 } 1146 1147 if (i == STE_TIMEOUT) 1148 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 1149 1150 delay(1000); 1151 } 1152 1153 /* 1154 * ste_setthresh: 1155 * 1156 * set the various transmit threshold registers 1157 */ 1158 static void 1159 ste_setthresh(struct ste_softc *sc) 1160 { 1161 /* set the TX threhold */ 1162 bus_space_write_2(sc->sc_st, sc->sc_sh, 1163 STE_TxStartThresh, sc->sc_txthresh); 1164 /* Urgent threshold: set to sc_txthresh / 2 */ 1165 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1166 sc->sc_txthresh >> 6); 1167 /* Burst threshold: use default value (256 bytes) */ 1168 } 1169 1170 /* 1171 * restart TX at the given frame ID in the transmitter ring 1172 */ 1173 static void 1174 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1175 { 1176 u_int32_t control; 1177 1178 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1179 control = le32toh(sc->sc_txdescs[id].tfd_control); 1180 control &= ~TFD_TxDMAComplete; 1181 sc->sc_txdescs[id].tfd_control = htole32(control); 1182 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1183 1184 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1185 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1186 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1187 ste_dmahalt_wait(sc); 1188 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1189 STE_CDTXADDR(sc, id)); 1190 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1191 } 1192 1193 /* 1194 * ste_init: [ ifnet interface function ] 1195 * 1196 * Initialize the interface. Must be called at splnet(). 1197 */ 1198 static int 1199 ste_init(struct ifnet *ifp) 1200 { 1201 struct ste_softc *sc = ifp->if_softc; 1202 bus_space_tag_t st = sc->sc_st; 1203 bus_space_handle_t sh = sc->sc_sh; 1204 struct ste_descsoft *ds; 1205 int i, error = 0; 1206 1207 /* 1208 * Cancel any pending I/O. 1209 */ 1210 ste_stop(ifp, 0); 1211 1212 /* 1213 * Reset the chip to a known state. 1214 */ 1215 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1216 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1217 1218 /* 1219 * Initialize the transmit descriptor ring. 1220 */ 1221 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1222 sc->sc_txpending = 0; 1223 sc->sc_txdirty = 0; 1224 sc->sc_txlast = STE_NTXDESC - 1; 1225 1226 /* 1227 * Initialize the receive descriptor and receive job 1228 * descriptor rings. 1229 */ 1230 for (i = 0; i < STE_NRXDESC; i++) { 1231 ds = &sc->sc_rxsoft[i]; 1232 if (ds->ds_mbuf == NULL) { 1233 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1234 printf("%s: unable to allocate or map rx " 1235 "buffer %d, error = %d\n", 1236 device_xname(sc->sc_dev), i, error); 1237 /* 1238 * XXX Should attempt to run with fewer receive 1239 * XXX buffers instead of just failing. 1240 */ 1241 ste_rxdrain(sc); 1242 goto out; 1243 } 1244 } else 1245 STE_INIT_RXDESC(sc, i); 1246 } 1247 sc->sc_rxptr = 0; 1248 1249 /* Set the station address. */ 1250 for (i = 0; i < ETHER_ADDR_LEN; i++) 1251 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1252 CLLADDR(ifp->if_sadl)[i]); 1253 1254 /* Set up the receive filter. */ 1255 ste_set_filter(sc); 1256 1257 /* 1258 * Give the receive ring to the chip. 1259 */ 1260 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1261 STE_CDRXADDR(sc, sc->sc_rxptr)); 1262 1263 /* 1264 * We defer giving the transmit ring to the chip until we 1265 * transmit the first packet. 1266 */ 1267 1268 /* 1269 * Initialize the Tx auto-poll period. It's OK to make this number 1270 * large (127 is the max) -- we explicitly kick the transmit engine 1271 * when there's actually a packet. We are using auto-polling only 1272 * to make the interface to the transmit engine not suck. 1273 */ 1274 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1275 1276 /* ..and the Rx auto-poll period. */ 1277 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1278 1279 /* Initialize the Tx start threshold. */ 1280 ste_setthresh(sc); 1281 1282 /* Set the FIFO release threshold to 512 bytes. */ 1283 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1284 1285 /* Set maximum packet size for VLAN. */ 1286 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1287 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1288 else 1289 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1290 1291 /* 1292 * Initialize the interrupt mask. 1293 */ 1294 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1295 IE_TxDMAComplete | IE_RxDMAComplete; 1296 1297 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1298 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1299 1300 /* 1301 * Start the receive DMA engine. 1302 */ 1303 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1304 1305 /* 1306 * Initialize MacCtrl0 -- do it before setting the media, 1307 * as setting the media will actually program the register. 1308 */ 1309 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1310 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1311 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1312 1313 /* 1314 * Set the current media. 1315 */ 1316 if ((error = ether_mediachange(ifp)) != 0) 1317 goto out; 1318 1319 /* 1320 * Start the MAC. 1321 */ 1322 bus_space_write_2(st, sh, STE_MacCtrl1, 1323 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1324 1325 /* 1326 * Start the one second MII clock. 1327 */ 1328 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1329 1330 /* 1331 * ...all done! 1332 */ 1333 ifp->if_flags |= IFF_RUNNING; 1334 ifp->if_flags &= ~IFF_OACTIVE; 1335 1336 out: 1337 if (error) 1338 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1339 return (error); 1340 } 1341 1342 /* 1343 * ste_drain: 1344 * 1345 * Drain the receive queue. 1346 */ 1347 static void 1348 ste_rxdrain(struct ste_softc *sc) 1349 { 1350 struct ste_descsoft *ds; 1351 int i; 1352 1353 for (i = 0; i < STE_NRXDESC; i++) { 1354 ds = &sc->sc_rxsoft[i]; 1355 if (ds->ds_mbuf != NULL) { 1356 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1357 m_freem(ds->ds_mbuf); 1358 ds->ds_mbuf = NULL; 1359 } 1360 } 1361 } 1362 1363 /* 1364 * ste_stop: [ ifnet interface function ] 1365 * 1366 * Stop transmission on the interface. 1367 */ 1368 static void 1369 ste_stop(struct ifnet *ifp, int disable) 1370 { 1371 struct ste_softc *sc = ifp->if_softc; 1372 struct ste_descsoft *ds; 1373 int i; 1374 1375 /* 1376 * Stop the one second clock. 1377 */ 1378 callout_stop(&sc->sc_tick_ch); 1379 1380 /* Down the MII. */ 1381 mii_down(&sc->sc_mii); 1382 1383 /* 1384 * Disable interrupts. 1385 */ 1386 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1387 1388 /* 1389 * Stop receiver, transmitter, and stats update. 1390 */ 1391 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1392 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1393 1394 /* 1395 * Stop the transmit and receive DMA. 1396 */ 1397 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1398 DC_RxDMAHalt | DC_TxDMAHalt); 1399 ste_dmahalt_wait(sc); 1400 1401 /* 1402 * Release any queued transmit buffers. 1403 */ 1404 for (i = 0; i < STE_NTXDESC; i++) { 1405 ds = &sc->sc_txsoft[i]; 1406 if (ds->ds_mbuf != NULL) { 1407 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1408 m_freem(ds->ds_mbuf); 1409 ds->ds_mbuf = NULL; 1410 } 1411 } 1412 1413 /* 1414 * Mark the interface down and cancel the watchdog timer. 1415 */ 1416 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1417 ifp->if_timer = 0; 1418 1419 if (disable) 1420 ste_rxdrain(sc); 1421 } 1422 1423 static int 1424 ste_eeprom_wait(struct ste_softc *sc) 1425 { 1426 int i; 1427 1428 for (i = 0; i < STE_TIMEOUT; i++) { 1429 delay(1000); 1430 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1431 EC_EepromBusy) == 0) 1432 return (0); 1433 } 1434 return (1); 1435 } 1436 1437 /* 1438 * ste_read_eeprom: 1439 * 1440 * Read data from the serial EEPROM. 1441 */ 1442 static void 1443 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1444 { 1445 1446 if (ste_eeprom_wait(sc)) 1447 printf("%s: EEPROM failed to come ready\n", 1448 device_xname(sc->sc_dev)); 1449 1450 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1451 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1452 if (ste_eeprom_wait(sc)) 1453 printf("%s: EEPROM read timed out\n", 1454 device_xname(sc->sc_dev)); 1455 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1456 } 1457 1458 /* 1459 * ste_add_rxbuf: 1460 * 1461 * Add a receive buffer to the indicated descriptor. 1462 */ 1463 static int 1464 ste_add_rxbuf(struct ste_softc *sc, int idx) 1465 { 1466 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1467 struct mbuf *m; 1468 int error; 1469 1470 MGETHDR(m, M_DONTWAIT, MT_DATA); 1471 if (m == NULL) 1472 return (ENOBUFS); 1473 1474 MCLGET(m, M_DONTWAIT); 1475 if ((m->m_flags & M_EXT) == 0) { 1476 m_freem(m); 1477 return (ENOBUFS); 1478 } 1479 1480 if (ds->ds_mbuf != NULL) 1481 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1482 1483 ds->ds_mbuf = m; 1484 1485 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1486 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1487 BUS_DMA_READ|BUS_DMA_NOWAIT); 1488 if (error) { 1489 printf("%s: can't load rx DMA map %d, error = %d\n", 1490 device_xname(sc->sc_dev), idx, error); 1491 panic("ste_add_rxbuf"); /* XXX */ 1492 } 1493 1494 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1495 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1496 1497 STE_INIT_RXDESC(sc, idx); 1498 1499 return (0); 1500 } 1501 1502 /* 1503 * ste_set_filter: 1504 * 1505 * Set up the receive filter. 1506 */ 1507 static void 1508 ste_set_filter(struct ste_softc *sc) 1509 { 1510 struct ethercom *ec = &sc->sc_ethercom; 1511 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1512 struct ether_multi *enm; 1513 struct ether_multistep step; 1514 uint32_t crc; 1515 uint16_t mchash[4]; 1516 1517 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1518 if (ifp->if_flags & IFF_BROADCAST) 1519 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1520 1521 if (ifp->if_flags & IFF_PROMISC) { 1522 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1523 goto allmulti; 1524 } 1525 1526 /* 1527 * Set up the multicast address filter by passing all multicast 1528 * addresses through a CRC generator, and then using the low-order 1529 * 6 bits as an index into the 64 bit multicast hash table. The 1530 * high order bits select the register, while the rest of the bits 1531 * select the bit within the register. 1532 */ 1533 1534 memset(mchash, 0, sizeof(mchash)); 1535 1536 ETHER_FIRST_MULTI(step, ec, enm); 1537 if (enm == NULL) 1538 goto done; 1539 1540 while (enm != NULL) { 1541 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1542 /* 1543 * We must listen to a range of multicast addresses. 1544 * For now, just accept all multicasts, rather than 1545 * trying to set only those filter bits needed to match 1546 * the range. (At this time, the only use of address 1547 * ranges is for IP multicast routing, for which the 1548 * range is big enough to require all bits set.) 1549 */ 1550 goto allmulti; 1551 } 1552 1553 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1554 1555 /* Just want the 6 least significant bits. */ 1556 crc &= 0x3f; 1557 1558 /* Set the corresponding bit in the hash table. */ 1559 mchash[crc >> 4] |= 1 << (crc & 0xf); 1560 1561 ETHER_NEXT_MULTI(step, enm); 1562 } 1563 1564 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1565 1566 ifp->if_flags &= ~IFF_ALLMULTI; 1567 goto done; 1568 1569 allmulti: 1570 ifp->if_flags |= IFF_ALLMULTI; 1571 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1572 1573 done: 1574 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1575 /* 1576 * Program the multicast hash table. 1577 */ 1578 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1579 mchash[0]); 1580 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1581 mchash[1]); 1582 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1583 mchash[2]); 1584 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1585 mchash[3]); 1586 } 1587 1588 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1589 sc->sc_ReceiveMode); 1590 } 1591 1592 /* 1593 * ste_mii_readreg: [mii interface function] 1594 * 1595 * Read a PHY register on the MII of the ST-201. 1596 */ 1597 static int 1598 ste_mii_readreg(device_t self, int phy, int reg) 1599 { 1600 1601 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1602 } 1603 1604 /* 1605 * ste_mii_writereg: [mii interface function] 1606 * 1607 * Write a PHY register on the MII of the ST-201. 1608 */ 1609 static void 1610 ste_mii_writereg(device_t self, int phy, int reg, int val) 1611 { 1612 1613 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1614 } 1615 1616 /* 1617 * ste_mii_statchg: [mii interface function] 1618 * 1619 * Callback from MII layer when media changes. 1620 */ 1621 static void 1622 ste_mii_statchg(struct ifnet *ifp) 1623 { 1624 struct ste_softc *sc = ifp->if_softc; 1625 1626 if (sc->sc_mii.mii_media_active & IFM_FDX) 1627 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1628 else 1629 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1630 1631 /* XXX 802.1x flow-control? */ 1632 1633 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1634 } 1635 1636 /* 1637 * ste_mii_bitbang_read: [mii bit-bang interface function] 1638 * 1639 * Read the MII serial port for the MII bit-bang module. 1640 */ 1641 static uint32_t 1642 ste_mii_bitbang_read(device_t self) 1643 { 1644 struct ste_softc *sc = device_private(self); 1645 1646 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1647 } 1648 1649 /* 1650 * ste_mii_bitbang_write: [mii big-bang interface function] 1651 * 1652 * Write the MII serial port for the MII bit-bang module. 1653 */ 1654 static void 1655 ste_mii_bitbang_write(device_t self, uint32_t val) 1656 { 1657 struct ste_softc *sc = device_private(self); 1658 1659 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1660 } 1661