1 /* $NetBSD: if_ste.c,v 1.44 2012/10/27 17:18:33 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. ST-201 10/100 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.44 2012/10/27 17:18:33 chs Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stereg.h> 72 73 /* 74 * Transmit descriptor list size. 75 */ 76 #define STE_NTXDESC 256 77 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 78 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 79 80 /* 81 * Receive descriptor list size. 82 */ 83 #define STE_NRXDESC 128 84 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 85 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 86 87 /* 88 * Control structures are DMA'd to the ST-201 chip. We allocate them in 89 * a single clump that maps to a single DMA segment to make several things 90 * easier. 91 */ 92 struct ste_control_data { 93 /* 94 * The transmit descriptors. 95 */ 96 struct ste_tfd scd_txdescs[STE_NTXDESC]; 97 98 /* 99 * The receive descriptors. 100 */ 101 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 102 }; 103 104 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 105 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 106 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 107 108 /* 109 * Software state for transmit and receive jobs. 110 */ 111 struct ste_descsoft { 112 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 113 bus_dmamap_t ds_dmamap; /* our DMA map */ 114 }; 115 116 /* 117 * Software state per device. 118 */ 119 struct ste_softc { 120 device_t sc_dev; /* generic device information */ 121 bus_space_tag_t sc_st; /* bus space tag */ 122 bus_space_handle_t sc_sh; /* bus space handle */ 123 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 124 struct ethercom sc_ethercom; /* ethernet common data */ 125 126 void *sc_ih; /* interrupt cookie */ 127 128 struct mii_data sc_mii; /* MII/media information */ 129 130 callout_t sc_tick_ch; /* tick callout */ 131 132 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 133 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 134 135 /* 136 * Software state for transmit and receive descriptors. 137 */ 138 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 139 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 140 141 /* 142 * Control data structures. 143 */ 144 struct ste_control_data *sc_control_data; 145 #define sc_txdescs sc_control_data->scd_txdescs 146 #define sc_rxdescs sc_control_data->scd_rxdescs 147 148 int sc_txpending; /* number of Tx requests pending */ 149 int sc_txdirty; /* first dirty Tx descriptor */ 150 int sc_txlast; /* last used Tx descriptor */ 151 152 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 153 154 int sc_txthresh; /* Tx threshold */ 155 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 156 uint16_t sc_IntEnable; /* prototype IntEnable register */ 157 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 158 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 159 }; 160 161 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 162 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 163 164 #define STE_CDTXSYNC(sc, x, ops) \ 165 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 166 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 167 168 #define STE_CDRXSYNC(sc, x, ops) \ 169 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 170 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 171 172 #define STE_INIT_RXDESC(sc, x) \ 173 do { \ 174 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 175 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 176 struct mbuf *__m = __ds->ds_mbuf; \ 177 \ 178 /* \ 179 * Note: We scoot the packet forward 2 bytes in the buffer \ 180 * so that the payload after the Ethernet header is aligned \ 181 * to a 4-byte boundary. \ 182 */ \ 183 __m->m_data = __m->m_ext.ext_buf + 2; \ 184 __rfd->rfd_frag.frag_addr = \ 185 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 186 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 187 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 188 __rfd->rfd_status = 0; \ 189 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 190 } while (/*CONSTCOND*/0) 191 192 #define STE_TIMEOUT 1000 193 194 static void ste_start(struct ifnet *); 195 static void ste_watchdog(struct ifnet *); 196 static int ste_ioctl(struct ifnet *, u_long, void *); 197 static int ste_init(struct ifnet *); 198 static void ste_stop(struct ifnet *, int); 199 200 static bool ste_shutdown(device_t, int); 201 202 static void ste_reset(struct ste_softc *, u_int32_t); 203 static void ste_setthresh(struct ste_softc *); 204 static void ste_txrestart(struct ste_softc *, u_int8_t); 205 static void ste_rxdrain(struct ste_softc *); 206 static int ste_add_rxbuf(struct ste_softc *, int); 207 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 208 static void ste_tick(void *); 209 210 static void ste_stats_update(struct ste_softc *); 211 212 static void ste_set_filter(struct ste_softc *); 213 214 static int ste_intr(void *); 215 static void ste_txintr(struct ste_softc *); 216 static void ste_rxintr(struct ste_softc *); 217 218 static int ste_mii_readreg(device_t, int, int); 219 static void ste_mii_writereg(device_t, int, int, int); 220 static void ste_mii_statchg(struct ifnet *); 221 222 static int ste_match(device_t, cfdata_t, void *); 223 static void ste_attach(device_t, device_t, void *); 224 225 int ste_copy_small = 0; 226 227 CFATTACH_DECL_NEW(ste, sizeof(struct ste_softc), 228 ste_match, ste_attach, NULL, NULL); 229 230 static uint32_t ste_mii_bitbang_read(device_t); 231 static void ste_mii_bitbang_write(device_t, uint32_t); 232 233 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 234 ste_mii_bitbang_read, 235 ste_mii_bitbang_write, 236 { 237 PC_MgmtData, /* MII_BIT_MDO */ 238 PC_MgmtData, /* MII_BIT_MDI */ 239 PC_MgmtClk, /* MII_BIT_MDC */ 240 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 241 0, /* MII_BIT_DIR_PHY_HOST */ 242 } 243 }; 244 245 /* 246 * Devices supported by this driver. 247 */ 248 static const struct ste_product { 249 pci_vendor_id_t ste_vendor; 250 pci_product_id_t ste_product; 251 const char *ste_name; 252 } ste_products[] = { 253 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 254 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 255 256 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 257 "Sundance ST-201 10/100 Ethernet" }, 258 259 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 260 "D-Link DL-1002 10/100 Ethernet" }, 261 262 { 0, 0, 263 NULL }, 264 }; 265 266 static const struct ste_product * 267 ste_lookup(const struct pci_attach_args *pa) 268 { 269 const struct ste_product *sp; 270 271 for (sp = ste_products; sp->ste_name != NULL; sp++) { 272 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 273 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 274 return (sp); 275 } 276 return (NULL); 277 } 278 279 static int 280 ste_match(device_t parent, cfdata_t cf, void *aux) 281 { 282 struct pci_attach_args *pa = aux; 283 284 if (ste_lookup(pa) != NULL) 285 return (1); 286 287 return (0); 288 } 289 290 static void 291 ste_attach(device_t parent, device_t self, void *aux) 292 { 293 struct ste_softc *sc = device_private(self); 294 struct pci_attach_args *pa = aux; 295 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 296 pci_chipset_tag_t pc = pa->pa_pc; 297 pci_intr_handle_t ih; 298 const char *intrstr = NULL; 299 bus_space_tag_t iot, memt; 300 bus_space_handle_t ioh, memh; 301 bus_dma_segment_t seg; 302 int ioh_valid, memh_valid; 303 int i, rseg, error; 304 const struct ste_product *sp; 305 uint8_t enaddr[ETHER_ADDR_LEN]; 306 uint16_t myea[ETHER_ADDR_LEN / 2]; 307 308 sc->sc_dev = self; 309 310 callout_init(&sc->sc_tick_ch, 0); 311 312 sp = ste_lookup(pa); 313 if (sp == NULL) { 314 printf("\n"); 315 panic("ste_attach: impossible"); 316 } 317 318 printf(": %s\n", sp->ste_name); 319 320 /* 321 * Map the device. 322 */ 323 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 324 PCI_MAPREG_TYPE_IO, 0, 325 &iot, &ioh, NULL, NULL) == 0); 326 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 327 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 328 &memt, &memh, NULL, NULL) == 0); 329 330 if (memh_valid) { 331 sc->sc_st = memt; 332 sc->sc_sh = memh; 333 } else if (ioh_valid) { 334 sc->sc_st = iot; 335 sc->sc_sh = ioh; 336 } else { 337 aprint_error_dev(self, "unable to map device registers\n"); 338 return; 339 } 340 341 sc->sc_dmat = pa->pa_dmat; 342 343 /* Enable bus mastering. */ 344 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 345 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 346 PCI_COMMAND_MASTER_ENABLE); 347 348 /* power up chip */ 349 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 350 NULL)) && error != EOPNOTSUPP) { 351 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", 352 error); 353 return; 354 } 355 356 /* 357 * Map and establish our interrupt. 358 */ 359 if (pci_intr_map(pa, &ih)) { 360 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 361 return; 362 } 363 intrstr = pci_intr_string(pc, ih); 364 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 365 if (sc->sc_ih == NULL) { 366 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 367 if (intrstr != NULL) 368 aprint_error(" at %s", intrstr); 369 aprint_error("\n"); 370 return; 371 } 372 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 373 374 /* 375 * Allocate the control data structures, and create and load the 376 * DMA map for it. 377 */ 378 if ((error = bus_dmamem_alloc(sc->sc_dmat, 379 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 380 0)) != 0) { 381 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", 382 error); 383 goto fail_0; 384 } 385 386 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 387 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 388 BUS_DMA_COHERENT)) != 0) { 389 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 390 error); 391 goto fail_1; 392 } 393 394 if ((error = bus_dmamap_create(sc->sc_dmat, 395 sizeof(struct ste_control_data), 1, 396 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 397 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 398 "error = %d\n", error); 399 goto fail_2; 400 } 401 402 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 403 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 404 0)) != 0) { 405 aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, error = %d\n", 406 error); 407 goto fail_3; 408 } 409 410 /* 411 * Create the transmit buffer DMA maps. 412 */ 413 for (i = 0; i < STE_NTXDESC; i++) { 414 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 415 STE_NTXFRAGS, MCLBYTES, 0, 0, 416 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 417 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 418 "error = %d\n", i, error); 419 goto fail_4; 420 } 421 } 422 423 /* 424 * Create the receive buffer DMA maps. 425 */ 426 for (i = 0; i < STE_NRXDESC; i++) { 427 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 428 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 429 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 430 "error = %d\n", i, error); 431 goto fail_5; 432 } 433 sc->sc_rxsoft[i].ds_mbuf = NULL; 434 } 435 436 /* 437 * Reset the chip to a known state. 438 */ 439 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 440 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 441 442 /* 443 * Read the Ethernet address from the EEPROM. 444 */ 445 for (i = 0; i < 3; i++) { 446 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 447 myea[i] = le16toh(myea[i]); 448 } 449 memcpy(enaddr, myea, sizeof(enaddr)); 450 451 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 452 ether_sprintf(enaddr)); 453 454 /* 455 * Initialize our media structures and probe the MII. 456 */ 457 sc->sc_mii.mii_ifp = ifp; 458 sc->sc_mii.mii_readreg = ste_mii_readreg; 459 sc->sc_mii.mii_writereg = ste_mii_writereg; 460 sc->sc_mii.mii_statchg = ste_mii_statchg; 461 sc->sc_ethercom.ec_mii = &sc->sc_mii; 462 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 463 ether_mediastatus); 464 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 465 MII_OFFSET_ANY, 0); 466 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 467 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 468 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 469 } else 470 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 471 472 ifp = &sc->sc_ethercom.ec_if; 473 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 474 ifp->if_softc = sc; 475 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 476 ifp->if_ioctl = ste_ioctl; 477 ifp->if_start = ste_start; 478 ifp->if_watchdog = ste_watchdog; 479 ifp->if_init = ste_init; 480 ifp->if_stop = ste_stop; 481 IFQ_SET_READY(&ifp->if_snd); 482 483 /* 484 * Default the transmit threshold to 128 bytes. 485 */ 486 sc->sc_txthresh = 128; 487 488 /* 489 * Disable MWI if the PCI layer tells us to. 490 */ 491 sc->sc_DMACtrl = 0; 492 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 493 sc->sc_DMACtrl |= DC_MWIDisable; 494 495 /* 496 * We can support 802.1Q VLAN-sized frames. 497 */ 498 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 499 500 /* 501 * Attach the interface. 502 */ 503 if_attach(ifp); 504 ether_ifattach(ifp, enaddr); 505 506 /* 507 * Make sure the interface is shutdown during reboot. 508 */ 509 if (pmf_device_register1(self, NULL, NULL, ste_shutdown)) 510 pmf_class_network_register(self, ifp); 511 else 512 aprint_error_dev(self, "couldn't establish power handler\n"); 513 514 return; 515 516 /* 517 * Free any resources we've allocated during the failed attach 518 * attempt. Do this in reverse order and fall through. 519 */ 520 fail_5: 521 for (i = 0; i < STE_NRXDESC; i++) { 522 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 523 bus_dmamap_destroy(sc->sc_dmat, 524 sc->sc_rxsoft[i].ds_dmamap); 525 } 526 fail_4: 527 for (i = 0; i < STE_NTXDESC; i++) { 528 if (sc->sc_txsoft[i].ds_dmamap != NULL) 529 bus_dmamap_destroy(sc->sc_dmat, 530 sc->sc_txsoft[i].ds_dmamap); 531 } 532 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 533 fail_3: 534 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 535 fail_2: 536 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 537 sizeof(struct ste_control_data)); 538 fail_1: 539 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 540 fail_0: 541 return; 542 } 543 544 /* 545 * ste_shutdown: 546 * 547 * Make sure the interface is stopped at reboot time. 548 */ 549 static bool 550 ste_shutdown(device_t self, int howto) 551 { 552 struct ste_softc *sc; 553 554 sc = device_private(self); 555 ste_stop(&sc->sc_ethercom.ec_if, 1); 556 557 return true; 558 } 559 560 static void 561 ste_dmahalt_wait(struct ste_softc *sc) 562 { 563 int i; 564 565 for (i = 0; i < STE_TIMEOUT; i++) { 566 delay(2); 567 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 568 DC_DMAHaltBusy) == 0) 569 break; 570 } 571 572 if (i == STE_TIMEOUT) 573 printf("%s: DMA halt timed out\n", device_xname(sc->sc_dev)); 574 } 575 576 /* 577 * ste_start: [ifnet interface function] 578 * 579 * Start packet transmission on the interface. 580 */ 581 static void 582 ste_start(struct ifnet *ifp) 583 { 584 struct ste_softc *sc = ifp->if_softc; 585 struct mbuf *m0, *m; 586 struct ste_descsoft *ds; 587 struct ste_tfd *tfd; 588 bus_dmamap_t dmamap; 589 int error, olasttx, nexttx, opending, seg, totlen; 590 591 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 592 return; 593 594 /* 595 * Remember the previous number of pending transmissions 596 * and the current last descriptor in the list. 597 */ 598 opending = sc->sc_txpending; 599 olasttx = sc->sc_txlast; 600 601 /* 602 * Loop through the send queue, setting up transmit descriptors 603 * until we drain the queue, or use up all available transmit 604 * descriptors. 605 */ 606 while (sc->sc_txpending < STE_NTXDESC) { 607 /* 608 * Grab a packet off the queue. 609 */ 610 IFQ_POLL(&ifp->if_snd, m0); 611 if (m0 == NULL) 612 break; 613 m = NULL; 614 615 /* 616 * Get the last and next available transmit descriptor. 617 */ 618 nexttx = STE_NEXTTX(sc->sc_txlast); 619 tfd = &sc->sc_txdescs[nexttx]; 620 ds = &sc->sc_txsoft[nexttx]; 621 622 dmamap = ds->ds_dmamap; 623 624 /* 625 * Load the DMA map. If this fails, the packet either 626 * didn't fit in the alloted number of segments, or we 627 * were short on resources. In this case, we'll copy 628 * and try again. 629 */ 630 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 631 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 632 MGETHDR(m, M_DONTWAIT, MT_DATA); 633 if (m == NULL) { 634 printf("%s: unable to allocate Tx mbuf\n", 635 device_xname(sc->sc_dev)); 636 break; 637 } 638 if (m0->m_pkthdr.len > MHLEN) { 639 MCLGET(m, M_DONTWAIT); 640 if ((m->m_flags & M_EXT) == 0) { 641 printf("%s: unable to allocate Tx " 642 "cluster\n", device_xname(sc->sc_dev)); 643 m_freem(m); 644 break; 645 } 646 } 647 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 648 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 649 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 650 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 651 if (error) { 652 printf("%s: unable to load Tx buffer, " 653 "error = %d\n", device_xname(sc->sc_dev), error); 654 break; 655 } 656 } 657 658 IFQ_DEQUEUE(&ifp->if_snd, m0); 659 if (m != NULL) { 660 m_freem(m0); 661 m0 = m; 662 } 663 664 /* 665 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 666 */ 667 668 /* Sync the DMA map. */ 669 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 670 BUS_DMASYNC_PREWRITE); 671 672 /* Initialize the fragment list. */ 673 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 674 tfd->tfd_frags[seg].frag_addr = 675 htole32(dmamap->dm_segs[seg].ds_addr); 676 tfd->tfd_frags[seg].frag_len = 677 htole32(dmamap->dm_segs[seg].ds_len); 678 totlen += dmamap->dm_segs[seg].ds_len; 679 } 680 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 681 682 /* Initialize the descriptor. */ 683 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 684 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 685 686 /* Sync the descriptor. */ 687 STE_CDTXSYNC(sc, nexttx, 688 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 689 690 /* 691 * Store a pointer to the packet so we can free it later, 692 * and remember what txdirty will be once the packet is 693 * done. 694 */ 695 ds->ds_mbuf = m0; 696 697 /* Advance the tx pointer. */ 698 sc->sc_txpending++; 699 sc->sc_txlast = nexttx; 700 701 /* 702 * Pass the packet to any BPF listeners. 703 */ 704 bpf_mtap(ifp, m0); 705 } 706 707 if (sc->sc_txpending == STE_NTXDESC) { 708 /* No more slots left; notify upper layer. */ 709 ifp->if_flags |= IFF_OACTIVE; 710 } 711 712 if (sc->sc_txpending != opending) { 713 /* 714 * We enqueued packets. If the transmitter was idle, 715 * reset the txdirty pointer. 716 */ 717 if (opending == 0) 718 sc->sc_txdirty = STE_NEXTTX(olasttx); 719 720 /* 721 * Cause a descriptor interrupt to happen on the 722 * last packet we enqueued, and also cause the 723 * DMA engine to wait after is has finished processing 724 * it. 725 */ 726 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 727 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 728 htole32(TFD_TxDMAIndicate); 729 STE_CDTXSYNC(sc, sc->sc_txlast, 730 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 731 732 /* 733 * Link up the new chain of descriptors to the 734 * last. 735 */ 736 sc->sc_txdescs[olasttx].tfd_next = 737 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 738 STE_CDTXSYNC(sc, olasttx, 739 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 740 741 /* 742 * Kick the transmit DMA logic. Note that since we're 743 * using auto-polling, reading the Tx desc pointer will 744 * give it the nudge it needs to get going. 745 */ 746 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 747 STE_TxDMAListPtr) == 0) { 748 bus_space_write_4(sc->sc_st, sc->sc_sh, 749 STE_DMACtrl, DC_TxDMAHalt); 750 ste_dmahalt_wait(sc); 751 bus_space_write_4(sc->sc_st, sc->sc_sh, 752 STE_TxDMAListPtr, 753 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 754 bus_space_write_4(sc->sc_st, sc->sc_sh, 755 STE_DMACtrl, DC_TxDMAResume); 756 } 757 758 /* Set a watchdog timer in case the chip flakes out. */ 759 ifp->if_timer = 5; 760 } 761 } 762 763 /* 764 * ste_watchdog: [ifnet interface function] 765 * 766 * Watchdog timer handler. 767 */ 768 static void 769 ste_watchdog(struct ifnet *ifp) 770 { 771 struct ste_softc *sc = ifp->if_softc; 772 773 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 774 ifp->if_oerrors++; 775 776 ste_txintr(sc); 777 ste_rxintr(sc); 778 (void) ste_init(ifp); 779 780 /* Try to get more packets going. */ 781 ste_start(ifp); 782 } 783 784 /* 785 * ste_ioctl: [ifnet interface function] 786 * 787 * Handle control requests from the operator. 788 */ 789 static int 790 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 791 { 792 struct ste_softc *sc = ifp->if_softc; 793 int s, error; 794 795 s = splnet(); 796 797 error = ether_ioctl(ifp, cmd, data); 798 if (error == ENETRESET) { 799 /* 800 * Multicast list has changed; set the hardware filter 801 * accordingly. 802 */ 803 if (ifp->if_flags & IFF_RUNNING) 804 ste_set_filter(sc); 805 error = 0; 806 } 807 808 /* Try to get more packets going. */ 809 ste_start(ifp); 810 811 splx(s); 812 return (error); 813 } 814 815 /* 816 * ste_intr: 817 * 818 * Interrupt service routine. 819 */ 820 static int 821 ste_intr(void *arg) 822 { 823 struct ste_softc *sc = arg; 824 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 825 uint16_t isr; 826 uint8_t txstat; 827 int wantinit; 828 829 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 830 IS_InterruptStatus) == 0) 831 return (0); 832 833 for (wantinit = 0; wantinit == 0;) { 834 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 835 if ((isr & sc->sc_IntEnable) == 0) 836 break; 837 838 /* Receive interrupts. */ 839 if (isr & IE_RxDMAComplete) 840 ste_rxintr(sc); 841 842 /* Transmit interrupts. */ 843 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 844 ste_txintr(sc); 845 846 /* Statistics overflow. */ 847 if (isr & IE_UpdateStats) 848 ste_stats_update(sc); 849 850 /* Transmission errors. */ 851 if (isr & IE_TxComplete) { 852 for (;;) { 853 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 854 STE_TxStatus); 855 if ((txstat & TS_TxComplete) == 0) 856 break; 857 if (txstat & TS_TxUnderrun) { 858 sc->sc_txthresh += 32; 859 if (sc->sc_txthresh > 0x1ffc) 860 sc->sc_txthresh = 0x1ffc; 861 printf("%s: transmit underrun, new " 862 "threshold: %d bytes\n", 863 device_xname(sc->sc_dev), 864 sc->sc_txthresh); 865 ste_reset(sc, AC_TxReset | AC_DMA | 866 AC_FIFO | AC_Network); 867 ste_setthresh(sc); 868 bus_space_write_1(sc->sc_st, sc->sc_sh, 869 STE_TxDMAPollPeriod, 127); 870 ste_txrestart(sc, 871 bus_space_read_1(sc->sc_st, 872 sc->sc_sh, STE_TxFrameId)); 873 } 874 if (txstat & TS_TxReleaseError) { 875 printf("%s: Tx FIFO release error\n", 876 device_xname(sc->sc_dev)); 877 wantinit = 1; 878 } 879 if (txstat & TS_MaxCollisions) { 880 printf("%s: excessive collisions\n", 881 device_xname(sc->sc_dev)); 882 wantinit = 1; 883 } 884 if (txstat & TS_TxStatusOverflow) { 885 printf("%s: status overflow\n", 886 device_xname(sc->sc_dev)); 887 wantinit = 1; 888 } 889 bus_space_write_2(sc->sc_st, sc->sc_sh, 890 STE_TxStatus, 0); 891 } 892 } 893 894 /* Host interface errors. */ 895 if (isr & IE_HostError) { 896 printf("%s: Host interface error\n", 897 device_xname(sc->sc_dev)); 898 wantinit = 1; 899 } 900 } 901 902 if (wantinit) 903 ste_init(ifp); 904 905 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 906 sc->sc_IntEnable); 907 908 /* Try to get more packets going. */ 909 ste_start(ifp); 910 911 return (1); 912 } 913 914 /* 915 * ste_txintr: 916 * 917 * Helper; handle transmit interrupts. 918 */ 919 static void 920 ste_txintr(struct ste_softc *sc) 921 { 922 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 923 struct ste_descsoft *ds; 924 uint32_t control; 925 int i; 926 927 ifp->if_flags &= ~IFF_OACTIVE; 928 929 /* 930 * Go through our Tx list and free mbufs for those 931 * frames which have been transmitted. 932 */ 933 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 934 i = STE_NEXTTX(i), sc->sc_txpending--) { 935 ds = &sc->sc_txsoft[i]; 936 937 STE_CDTXSYNC(sc, i, 938 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 939 940 control = le32toh(sc->sc_txdescs[i].tfd_control); 941 if ((control & TFD_TxDMAComplete) == 0) 942 break; 943 944 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 945 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 946 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 947 m_freem(ds->ds_mbuf); 948 ds->ds_mbuf = NULL; 949 } 950 951 /* Update the dirty transmit buffer pointer. */ 952 sc->sc_txdirty = i; 953 954 /* 955 * If there are no more pending transmissions, cancel the watchdog 956 * timer. 957 */ 958 if (sc->sc_txpending == 0) 959 ifp->if_timer = 0; 960 } 961 962 /* 963 * ste_rxintr: 964 * 965 * Helper; handle receive interrupts. 966 */ 967 static void 968 ste_rxintr(struct ste_softc *sc) 969 { 970 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 971 struct ste_descsoft *ds; 972 struct mbuf *m; 973 uint32_t status; 974 int i, len; 975 976 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 977 ds = &sc->sc_rxsoft[i]; 978 979 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 980 981 status = le32toh(sc->sc_rxdescs[i].rfd_status); 982 983 if ((status & RFD_RxDMAComplete) == 0) 984 break; 985 986 /* 987 * If the packet had an error, simply recycle the 988 * buffer. Note, we count the error later in the 989 * periodic stats update. 990 */ 991 if (status & RFD_RxFrameError) { 992 STE_INIT_RXDESC(sc, i); 993 continue; 994 } 995 996 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 997 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 998 999 /* 1000 * No errors; receive the packet. Note, we have 1001 * configured the chip to not include the CRC at 1002 * the end of the packet. 1003 */ 1004 len = RFD_RxDMAFrameLen(status); 1005 1006 /* 1007 * If the packet is small enough to fit in a 1008 * single header mbuf, allocate one and copy 1009 * the data into it. This greatly reduces 1010 * memory consumption when we receive lots 1011 * of small packets. 1012 * 1013 * Otherwise, we add a new buffer to the receive 1014 * chain. If this fails, we drop the packet and 1015 * recycle the old buffer. 1016 */ 1017 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1018 MGETHDR(m, M_DONTWAIT, MT_DATA); 1019 if (m == NULL) 1020 goto dropit; 1021 m->m_data += 2; 1022 memcpy(mtod(m, void *), 1023 mtod(ds->ds_mbuf, void *), len); 1024 STE_INIT_RXDESC(sc, i); 1025 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1026 ds->ds_dmamap->dm_mapsize, 1027 BUS_DMASYNC_PREREAD); 1028 } else { 1029 m = ds->ds_mbuf; 1030 if (ste_add_rxbuf(sc, i) != 0) { 1031 dropit: 1032 ifp->if_ierrors++; 1033 STE_INIT_RXDESC(sc, i); 1034 bus_dmamap_sync(sc->sc_dmat, 1035 ds->ds_dmamap, 0, 1036 ds->ds_dmamap->dm_mapsize, 1037 BUS_DMASYNC_PREREAD); 1038 continue; 1039 } 1040 } 1041 1042 m->m_pkthdr.rcvif = ifp; 1043 m->m_pkthdr.len = m->m_len = len; 1044 1045 /* 1046 * Pass this up to any BPF listeners, but only 1047 * pass if up the stack if it's for us. 1048 */ 1049 bpf_mtap(ifp, m); 1050 1051 /* Pass it on. */ 1052 (*ifp->if_input)(ifp, m); 1053 } 1054 1055 /* Update the receive pointer. */ 1056 sc->sc_rxptr = i; 1057 } 1058 1059 /* 1060 * ste_tick: 1061 * 1062 * One second timer, used to tick the MII. 1063 */ 1064 static void 1065 ste_tick(void *arg) 1066 { 1067 struct ste_softc *sc = arg; 1068 int s; 1069 1070 s = splnet(); 1071 mii_tick(&sc->sc_mii); 1072 ste_stats_update(sc); 1073 splx(s); 1074 1075 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1076 } 1077 1078 /* 1079 * ste_stats_update: 1080 * 1081 * Read the ST-201 statistics counters. 1082 */ 1083 static void 1084 ste_stats_update(struct ste_softc *sc) 1085 { 1086 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1087 bus_space_tag_t st = sc->sc_st; 1088 bus_space_handle_t sh = sc->sc_sh; 1089 1090 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1091 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1092 1093 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1094 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1095 1096 ifp->if_opackets += 1097 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1098 ifp->if_ipackets += 1099 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1100 1101 ifp->if_collisions += 1102 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1103 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1104 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1105 1106 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1107 1108 ifp->if_ierrors += 1109 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1110 1111 ifp->if_oerrors += 1112 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1113 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1114 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1115 1116 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1117 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1118 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1119 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1120 } 1121 1122 /* 1123 * ste_reset: 1124 * 1125 * Perform a soft reset on the ST-201. 1126 */ 1127 static void 1128 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1129 { 1130 uint32_t ac; 1131 int i; 1132 1133 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1134 1135 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1136 1137 delay(50000); 1138 1139 for (i = 0; i < STE_TIMEOUT; i++) { 1140 delay(1000); 1141 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1142 AC_ResetBusy) == 0) 1143 break; 1144 } 1145 1146 if (i == STE_TIMEOUT) 1147 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 1148 1149 delay(1000); 1150 } 1151 1152 /* 1153 * ste_setthresh: 1154 * 1155 * set the various transmit threshold registers 1156 */ 1157 static void 1158 ste_setthresh(struct ste_softc *sc) 1159 { 1160 /* set the TX threhold */ 1161 bus_space_write_2(sc->sc_st, sc->sc_sh, 1162 STE_TxStartThresh, sc->sc_txthresh); 1163 /* Urgent threshold: set to sc_txthresh / 2 */ 1164 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1165 sc->sc_txthresh >> 6); 1166 /* Burst threshold: use default value (256 bytes) */ 1167 } 1168 1169 /* 1170 * restart TX at the given frame ID in the transmitter ring 1171 */ 1172 static void 1173 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1174 { 1175 u_int32_t control; 1176 1177 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1178 control = le32toh(sc->sc_txdescs[id].tfd_control); 1179 control &= ~TFD_TxDMAComplete; 1180 sc->sc_txdescs[id].tfd_control = htole32(control); 1181 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1182 1183 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1184 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1185 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1186 ste_dmahalt_wait(sc); 1187 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1188 STE_CDTXADDR(sc, id)); 1189 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1190 } 1191 1192 /* 1193 * ste_init: [ ifnet interface function ] 1194 * 1195 * Initialize the interface. Must be called at splnet(). 1196 */ 1197 static int 1198 ste_init(struct ifnet *ifp) 1199 { 1200 struct ste_softc *sc = ifp->if_softc; 1201 bus_space_tag_t st = sc->sc_st; 1202 bus_space_handle_t sh = sc->sc_sh; 1203 struct ste_descsoft *ds; 1204 int i, error = 0; 1205 1206 /* 1207 * Cancel any pending I/O. 1208 */ 1209 ste_stop(ifp, 0); 1210 1211 /* 1212 * Reset the chip to a known state. 1213 */ 1214 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1215 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1216 1217 /* 1218 * Initialize the transmit descriptor ring. 1219 */ 1220 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1221 sc->sc_txpending = 0; 1222 sc->sc_txdirty = 0; 1223 sc->sc_txlast = STE_NTXDESC - 1; 1224 1225 /* 1226 * Initialize the receive descriptor and receive job 1227 * descriptor rings. 1228 */ 1229 for (i = 0; i < STE_NRXDESC; i++) { 1230 ds = &sc->sc_rxsoft[i]; 1231 if (ds->ds_mbuf == NULL) { 1232 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1233 printf("%s: unable to allocate or map rx " 1234 "buffer %d, error = %d\n", 1235 device_xname(sc->sc_dev), i, error); 1236 /* 1237 * XXX Should attempt to run with fewer receive 1238 * XXX buffers instead of just failing. 1239 */ 1240 ste_rxdrain(sc); 1241 goto out; 1242 } 1243 } else 1244 STE_INIT_RXDESC(sc, i); 1245 } 1246 sc->sc_rxptr = 0; 1247 1248 /* Set the station address. */ 1249 for (i = 0; i < ETHER_ADDR_LEN; i++) 1250 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1251 CLLADDR(ifp->if_sadl)[i]); 1252 1253 /* Set up the receive filter. */ 1254 ste_set_filter(sc); 1255 1256 /* 1257 * Give the receive ring to the chip. 1258 */ 1259 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1260 STE_CDRXADDR(sc, sc->sc_rxptr)); 1261 1262 /* 1263 * We defer giving the transmit ring to the chip until we 1264 * transmit the first packet. 1265 */ 1266 1267 /* 1268 * Initialize the Tx auto-poll period. It's OK to make this number 1269 * large (127 is the max) -- we explicitly kick the transmit engine 1270 * when there's actually a packet. We are using auto-polling only 1271 * to make the interface to the transmit engine not suck. 1272 */ 1273 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1274 1275 /* ..and the Rx auto-poll period. */ 1276 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1277 1278 /* Initialize the Tx start threshold. */ 1279 ste_setthresh(sc); 1280 1281 /* Set the FIFO release threshold to 512 bytes. */ 1282 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1283 1284 /* Set maximum packet size for VLAN. */ 1285 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1286 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1287 else 1288 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1289 1290 /* 1291 * Initialize the interrupt mask. 1292 */ 1293 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1294 IE_TxDMAComplete | IE_RxDMAComplete; 1295 1296 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1297 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1298 1299 /* 1300 * Start the receive DMA engine. 1301 */ 1302 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1303 1304 /* 1305 * Initialize MacCtrl0 -- do it before setting the media, 1306 * as setting the media will actually program the register. 1307 */ 1308 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1309 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1310 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1311 1312 /* 1313 * Set the current media. 1314 */ 1315 if ((error = ether_mediachange(ifp)) != 0) 1316 goto out; 1317 1318 /* 1319 * Start the MAC. 1320 */ 1321 bus_space_write_2(st, sh, STE_MacCtrl1, 1322 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1323 1324 /* 1325 * Start the one second MII clock. 1326 */ 1327 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1328 1329 /* 1330 * ...all done! 1331 */ 1332 ifp->if_flags |= IFF_RUNNING; 1333 ifp->if_flags &= ~IFF_OACTIVE; 1334 1335 out: 1336 if (error) 1337 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1338 return (error); 1339 } 1340 1341 /* 1342 * ste_drain: 1343 * 1344 * Drain the receive queue. 1345 */ 1346 static void 1347 ste_rxdrain(struct ste_softc *sc) 1348 { 1349 struct ste_descsoft *ds; 1350 int i; 1351 1352 for (i = 0; i < STE_NRXDESC; i++) { 1353 ds = &sc->sc_rxsoft[i]; 1354 if (ds->ds_mbuf != NULL) { 1355 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1356 m_freem(ds->ds_mbuf); 1357 ds->ds_mbuf = NULL; 1358 } 1359 } 1360 } 1361 1362 /* 1363 * ste_stop: [ ifnet interface function ] 1364 * 1365 * Stop transmission on the interface. 1366 */ 1367 static void 1368 ste_stop(struct ifnet *ifp, int disable) 1369 { 1370 struct ste_softc *sc = ifp->if_softc; 1371 struct ste_descsoft *ds; 1372 int i; 1373 1374 /* 1375 * Stop the one second clock. 1376 */ 1377 callout_stop(&sc->sc_tick_ch); 1378 1379 /* Down the MII. */ 1380 mii_down(&sc->sc_mii); 1381 1382 /* 1383 * Disable interrupts. 1384 */ 1385 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1386 1387 /* 1388 * Stop receiver, transmitter, and stats update. 1389 */ 1390 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1391 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1392 1393 /* 1394 * Stop the transmit and receive DMA. 1395 */ 1396 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1397 DC_RxDMAHalt | DC_TxDMAHalt); 1398 ste_dmahalt_wait(sc); 1399 1400 /* 1401 * Release any queued transmit buffers. 1402 */ 1403 for (i = 0; i < STE_NTXDESC; i++) { 1404 ds = &sc->sc_txsoft[i]; 1405 if (ds->ds_mbuf != NULL) { 1406 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1407 m_freem(ds->ds_mbuf); 1408 ds->ds_mbuf = NULL; 1409 } 1410 } 1411 1412 /* 1413 * Mark the interface down and cancel the watchdog timer. 1414 */ 1415 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1416 ifp->if_timer = 0; 1417 1418 if (disable) 1419 ste_rxdrain(sc); 1420 } 1421 1422 static int 1423 ste_eeprom_wait(struct ste_softc *sc) 1424 { 1425 int i; 1426 1427 for (i = 0; i < STE_TIMEOUT; i++) { 1428 delay(1000); 1429 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1430 EC_EepromBusy) == 0) 1431 return (0); 1432 } 1433 return (1); 1434 } 1435 1436 /* 1437 * ste_read_eeprom: 1438 * 1439 * Read data from the serial EEPROM. 1440 */ 1441 static void 1442 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1443 { 1444 1445 if (ste_eeprom_wait(sc)) 1446 printf("%s: EEPROM failed to come ready\n", 1447 device_xname(sc->sc_dev)); 1448 1449 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1450 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1451 if (ste_eeprom_wait(sc)) 1452 printf("%s: EEPROM read timed out\n", 1453 device_xname(sc->sc_dev)); 1454 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1455 } 1456 1457 /* 1458 * ste_add_rxbuf: 1459 * 1460 * Add a receive buffer to the indicated descriptor. 1461 */ 1462 static int 1463 ste_add_rxbuf(struct ste_softc *sc, int idx) 1464 { 1465 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1466 struct mbuf *m; 1467 int error; 1468 1469 MGETHDR(m, M_DONTWAIT, MT_DATA); 1470 if (m == NULL) 1471 return (ENOBUFS); 1472 1473 MCLGET(m, M_DONTWAIT); 1474 if ((m->m_flags & M_EXT) == 0) { 1475 m_freem(m); 1476 return (ENOBUFS); 1477 } 1478 1479 if (ds->ds_mbuf != NULL) 1480 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1481 1482 ds->ds_mbuf = m; 1483 1484 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1485 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1486 BUS_DMA_READ|BUS_DMA_NOWAIT); 1487 if (error) { 1488 printf("%s: can't load rx DMA map %d, error = %d\n", 1489 device_xname(sc->sc_dev), idx, error); 1490 panic("ste_add_rxbuf"); /* XXX */ 1491 } 1492 1493 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1494 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1495 1496 STE_INIT_RXDESC(sc, idx); 1497 1498 return (0); 1499 } 1500 1501 /* 1502 * ste_set_filter: 1503 * 1504 * Set up the receive filter. 1505 */ 1506 static void 1507 ste_set_filter(struct ste_softc *sc) 1508 { 1509 struct ethercom *ec = &sc->sc_ethercom; 1510 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1511 struct ether_multi *enm; 1512 struct ether_multistep step; 1513 uint32_t crc; 1514 uint16_t mchash[4]; 1515 1516 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1517 if (ifp->if_flags & IFF_BROADCAST) 1518 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1519 1520 if (ifp->if_flags & IFF_PROMISC) { 1521 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1522 goto allmulti; 1523 } 1524 1525 /* 1526 * Set up the multicast address filter by passing all multicast 1527 * addresses through a CRC generator, and then using the low-order 1528 * 6 bits as an index into the 64 bit multicast hash table. The 1529 * high order bits select the register, while the rest of the bits 1530 * select the bit within the register. 1531 */ 1532 1533 memset(mchash, 0, sizeof(mchash)); 1534 1535 ETHER_FIRST_MULTI(step, ec, enm); 1536 if (enm == NULL) 1537 goto done; 1538 1539 while (enm != NULL) { 1540 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1541 /* 1542 * We must listen to a range of multicast addresses. 1543 * For now, just accept all multicasts, rather than 1544 * trying to set only those filter bits needed to match 1545 * the range. (At this time, the only use of address 1546 * ranges is for IP multicast routing, for which the 1547 * range is big enough to require all bits set.) 1548 */ 1549 goto allmulti; 1550 } 1551 1552 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1553 1554 /* Just want the 6 least significant bits. */ 1555 crc &= 0x3f; 1556 1557 /* Set the corresponding bit in the hash table. */ 1558 mchash[crc >> 4] |= 1 << (crc & 0xf); 1559 1560 ETHER_NEXT_MULTI(step, enm); 1561 } 1562 1563 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1564 1565 ifp->if_flags &= ~IFF_ALLMULTI; 1566 goto done; 1567 1568 allmulti: 1569 ifp->if_flags |= IFF_ALLMULTI; 1570 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1571 1572 done: 1573 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1574 /* 1575 * Program the multicast hash table. 1576 */ 1577 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1578 mchash[0]); 1579 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1580 mchash[1]); 1581 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1582 mchash[2]); 1583 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1584 mchash[3]); 1585 } 1586 1587 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1588 sc->sc_ReceiveMode); 1589 } 1590 1591 /* 1592 * ste_mii_readreg: [mii interface function] 1593 * 1594 * Read a PHY register on the MII of the ST-201. 1595 */ 1596 static int 1597 ste_mii_readreg(device_t self, int phy, int reg) 1598 { 1599 1600 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1601 } 1602 1603 /* 1604 * ste_mii_writereg: [mii interface function] 1605 * 1606 * Write a PHY register on the MII of the ST-201. 1607 */ 1608 static void 1609 ste_mii_writereg(device_t self, int phy, int reg, int val) 1610 { 1611 1612 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1613 } 1614 1615 /* 1616 * ste_mii_statchg: [mii interface function] 1617 * 1618 * Callback from MII layer when media changes. 1619 */ 1620 static void 1621 ste_mii_statchg(struct ifnet *ifp) 1622 { 1623 struct ste_softc *sc = ifp->if_softc; 1624 1625 if (sc->sc_mii.mii_media_active & IFM_FDX) 1626 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1627 else 1628 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1629 1630 /* XXX 802.1x flow-control? */ 1631 1632 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1633 } 1634 1635 /* 1636 * ste_mii_bitbang_read: [mii bit-bang interface function] 1637 * 1638 * Read the MII serial port for the MII bit-bang module. 1639 */ 1640 static uint32_t 1641 ste_mii_bitbang_read(device_t self) 1642 { 1643 struct ste_softc *sc = device_private(self); 1644 1645 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1646 } 1647 1648 /* 1649 * ste_mii_bitbang_write: [mii big-bang interface function] 1650 * 1651 * Write the MII serial port for the MII bit-bang module. 1652 */ 1653 static void 1654 ste_mii_bitbang_write(device_t self, uint32_t val) 1655 { 1656 struct ste_softc *sc = device_private(self); 1657 1658 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1659 } 1660