1 /* $NetBSD: if_jme.c,v 1.45 2019/08/07 15:29:02 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 54 55 /* 56 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 57 * Ethernet Controllers. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.45 2019/08/07 15:29:02 msaitoh Exp $"); 62 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/mbuf.h> 67 #include <sys/protosw.h> 68 #include <sys/socket.h> 69 #include <sys/ioctl.h> 70 #include <sys/errno.h> 71 #include <sys/malloc.h> 72 #include <sys/kernel.h> 73 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 74 #include <sys/device.h> 75 #include <sys/syslog.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #include <net/if_media.h> 80 #include <net/if_types.h> 81 #include <net/if_dl.h> 82 #include <net/route.h> 83 #include <net/netisr.h> 84 #include <net/bpf.h> 85 86 #include <sys/rndsource.h> 87 88 #include <netinet/in.h> 89 #include <netinet/in_systm.h> 90 #include <netinet/ip.h> 91 92 #ifdef INET 93 #include <netinet/in_var.h> 94 #endif 95 96 #include <netinet/tcp.h> 97 98 #include <net/if_ether.h> 99 #if defined(INET) 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/if_jmereg.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 114 struct jme_product_desc { 115 uint32_t jme_product; 116 const char *jme_desc; 117 }; 118 119 /* number of entries in transmit and receive rings */ 120 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 121 122 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 123 124 /* Water mark to kick reclaiming Tx buffers. */ 125 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 126 127 128 struct jme_softc { 129 device_t jme_dev; /* base device */ 130 bus_space_tag_t jme_bt_mac; 131 bus_space_handle_t jme_bh_mac; /* Mac registers */ 132 bus_space_tag_t jme_bt_phy; 133 bus_space_handle_t jme_bh_phy; /* PHY registers */ 134 bus_space_tag_t jme_bt_misc; 135 bus_space_handle_t jme_bh_misc; /* Misc registers */ 136 bus_dma_tag_t jme_dmatag; 137 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 138 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 139 struct jme_desc* jme_txring; /* transmit ring */ 140 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 141 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 142 int jme_tx_cons; /* transmit ring consumer */ 143 int jme_tx_prod; /* transmit ring producer */ 144 int jme_tx_cnt; /* transmit ring active count */ 145 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 146 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 147 struct jme_desc* jme_rxring; /* receive ring */ 148 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 149 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 150 int jme_rx_cons; /* receive ring consumer */ 151 int jme_rx_prod; /* receive ring producer */ 152 void* jme_ih; /* our interrupt */ 153 struct ethercom jme_ec; 154 struct callout jme_tick_ch; /* tick callout */ 155 uint8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 156 uint8_t jme_phyaddr; /* address of integrated phy */ 157 uint8_t jme_chip_rev; /* chip revision */ 158 uint8_t jme_rev; /* PCI revision */ 159 mii_data_t jme_mii; /* mii bus */ 160 uint32_t jme_flags; /* device features, see below */ 161 uint32_t jme_txcsr; /* TX config register */ 162 uint32_t jme_rxcsr; /* RX config register */ 163 krndsource_t rnd_source; 164 /* interrupt coalition parameters */ 165 struct sysctllog *jme_clog; 166 int jme_intrxto; /* interrupt RX timeout */ 167 int jme_intrxct; /* interrupt RX packets counter */ 168 int jme_inttxto; /* interrupt TX timeout */ 169 int jme_inttxct; /* interrupt TX packets counter */ 170 }; 171 172 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 173 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 174 175 176 #define jme_if jme_ec.ec_if 177 #define jme_bpf jme_if.if_bpf 178 179 typedef struct jme_softc jme_softc_t; 180 typedef u_long ioctl_cmd_t; 181 182 static int jme_pci_match(device_t, cfdata_t, void *); 183 static void jme_pci_attach(device_t, device_t, void *); 184 static void jme_intr_rx(jme_softc_t *); 185 static int jme_intr(void *); 186 187 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 188 static int jme_mediachange(struct ifnet *); 189 static void jme_ifwatchdog(struct ifnet *); 190 static bool jme_shutdown(device_t, int); 191 192 static void jme_txeof(struct jme_softc *); 193 static void jme_ifstart(struct ifnet *); 194 static void jme_reset(jme_softc_t *); 195 static int jme_ifinit(struct ifnet *); 196 static int jme_init(struct ifnet *, int); 197 static void jme_stop(struct ifnet *, int); 198 // static void jme_restart(void *); 199 static void jme_ticks(void *); 200 static void jme_mac_config(jme_softc_t *); 201 static void jme_set_filter(jme_softc_t *); 202 203 int jme_mii_read(device_t, int, int, uint16_t *); 204 int jme_mii_write(device_t, int, int, uint16_t); 205 void jme_statchg(struct ifnet *); 206 207 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 208 static int jme_eeprom_macaddr(struct jme_softc *); 209 static int jme_reg_macaddr(struct jme_softc *); 210 211 #define JME_TIMEOUT 1000 212 #define JME_PHY_TIMEOUT 1000 213 #define JME_EEPROM_TIMEOUT 1000 214 215 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 216 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 217 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 218 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 219 static int jme_root_num; 220 221 222 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 223 jme_pci_match, jme_pci_attach, NULL, NULL); 224 225 static const struct jme_product_desc jme_products[] = { 226 { PCI_PRODUCT_JMICRON_JMC250, 227 "JMicron JMC250 Gigabit Ethernet Controller" }, 228 { PCI_PRODUCT_JMICRON_JMC260, 229 "JMicron JMC260 Gigabit Ethernet Controller" }, 230 { 0, NULL }, 231 }; 232 233 static const struct jme_product_desc *jme_lookup_product(uint32_t); 234 235 static const struct jme_product_desc * 236 jme_lookup_product(uint32_t id) 237 { 238 const struct jme_product_desc *jp; 239 240 for (jp = jme_products ; jp->jme_desc != NULL; jp++) 241 if (PCI_PRODUCT(id) == jp->jme_product) 242 return jp; 243 244 return NULL; 245 } 246 247 static int 248 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 249 { 250 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 251 252 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_JMICRON) 253 return 0; 254 255 if (jme_lookup_product(pa->pa_id) != NULL) 256 return 1; 257 258 return 0; 259 } 260 261 static void 262 jme_pci_attach(device_t parent, device_t self, void *aux) 263 { 264 jme_softc_t *sc = device_private(self); 265 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 266 const struct jme_product_desc *jp; 267 struct ifnet * const ifp = &sc->jme_if; 268 struct mii_data * const mii = &sc->jme_mii; 269 bus_space_tag_t iot1, iot2, memt; 270 bus_space_handle_t ioh1, ioh2, memh; 271 bus_size_t size, size2; 272 pci_intr_handle_t intrhandle; 273 const char *intrstr; 274 pcireg_t csr; 275 int nsegs, i; 276 const struct sysctlnode *node; 277 int jme_nodenum; 278 char intrbuf[PCI_INTRSTR_LEN]; 279 280 sc->jme_dev = self; 281 aprint_normal("\n"); 282 callout_init(&sc->jme_tick_ch, 0); 283 284 jp = jme_lookup_product(pa->pa_id); 285 if (jp == NULL) 286 panic("jme_pci_attach: impossible"); 287 288 if (jp->jme_product == PCI_PRODUCT_JMICRON_JMC250) 289 sc->jme_flags = JME_FLAG_GIGA; 290 291 /* 292 * Map the card space. Try Mem first. 293 */ 294 if (pci_mapreg_map(pa, JME_PCI_BAR0, 295 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 296 0, &memt, &memh, NULL, &size) == 0) { 297 sc->jme_bt_mac = memt; 298 sc->jme_bh_mac = memh; 299 sc->jme_bt_phy = memt; 300 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 301 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 302 aprint_error_dev(self, "can't subregion PHY space\n"); 303 bus_space_unmap(memt, memh, size); 304 return; 305 } 306 sc->jme_bt_misc = memt; 307 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 308 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 309 aprint_error_dev(self, "can't subregion misc space\n"); 310 bus_space_unmap(memt, memh, size); 311 return; 312 } 313 } else { 314 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 315 0, &iot1, &ioh1, NULL, &size) != 0) { 316 aprint_error_dev(self, "can't map I/O space 1\n"); 317 return; 318 } 319 sc->jme_bt_mac = iot1; 320 sc->jme_bh_mac = ioh1; 321 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 322 0, &iot2, &ioh2, NULL, &size2) != 0) { 323 aprint_error_dev(self, "can't map I/O space 2\n"); 324 bus_space_unmap(iot1, ioh1, size); 325 return; 326 } 327 sc->jme_bt_phy = iot2; 328 sc->jme_bh_phy = ioh2; 329 sc->jme_bt_misc = iot2; 330 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 331 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 332 aprint_error_dev(self, "can't subregion misc space\n"); 333 bus_space_unmap(iot1, ioh1, size); 334 bus_space_unmap(iot2, ioh2, size2); 335 return; 336 } 337 } 338 339 if (pci_dma64_available(pa)) 340 sc->jme_dmatag = pa->pa_dmat64; 341 else 342 sc->jme_dmatag = pa->pa_dmat; 343 344 /* Enable the device. */ 345 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 346 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 347 csr | PCI_COMMAND_MASTER_ENABLE); 348 349 aprint_normal_dev(self, "%s\n", jp->jme_desc); 350 351 sc->jme_rev = PCI_REVISION(pa->pa_class); 352 353 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 354 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 355 CHIPMODE_NOT_FPGA) 356 sc->jme_flags |= JME_FLAG_FPGA; 357 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 358 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 359 "0x%x", sc->jme_rev, sc->jme_chip_rev); 360 if (sc->jme_flags & JME_FLAG_FPGA) 361 aprint_verbose(" FPGA revision: 0x%x", 362 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 363 aprint_verbose("\n"); 364 365 /* 366 * Save PHY address. 367 * Integrated JR0211 has fixed PHY address whereas FPGA version 368 * requires PHY probing to get correct PHY address. 369 */ 370 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 371 sc->jme_phyaddr = 372 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 373 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 374 } else 375 sc->jme_phyaddr = 0; 376 377 378 jme_reset(sc); 379 380 /* read mac addr */ 381 if (jme_eeprom_macaddr(sc) && jme_reg_macaddr(sc)) { 382 aprint_error_dev(self, "error reading Ethernet address\n"); 383 /* return; */ 384 } 385 aprint_normal_dev(self, "Ethernet address %s\n", 386 ether_sprintf(sc->jme_enaddr)); 387 388 /* Map and establish interrupts */ 389 if (pci_intr_map(pa, &intrhandle)) { 390 aprint_error_dev(self, "couldn't map interrupt\n"); 391 return; 392 } 393 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 394 sc->jme_if.if_softc = sc; 395 sc->jme_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET, 396 jme_intr, sc, device_xname(self)); 397 if (sc->jme_ih == NULL) { 398 aprint_error_dev(self, "couldn't establish interrupt"); 399 if (intrstr != NULL) 400 aprint_error(" at %s", intrstr); 401 aprint_error("\n"); 402 return; 403 } 404 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 405 406 /* allocate and map DMA-safe memory for transmit ring */ 407 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 408 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 409 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 410 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 411 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 412 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 413 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 414 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 415 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 416 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 417 return; 418 } 419 /* allocate and map DMA-safe memory for receive ring */ 420 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 421 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 422 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 423 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 424 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 425 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 426 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 427 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 428 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 429 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 430 return; 431 } 432 for (i = 0; i < JME_NBUFS; i++) { 433 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 434 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 435 JME_NBUFS, JME_MAX_TX_LEN, 0, 436 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 437 &sc->jme_txmbufm[i]) != 0) { 438 aprint_error_dev(self, "can't allocate DMA TX map\n"); 439 return; 440 } 441 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 442 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 443 &sc->jme_rxmbufm[i]) != 0) { 444 aprint_error_dev(self, "can't allocate DMA RX map\n"); 445 return; 446 } 447 } 448 /* 449 * Initialize our media structures and probe the MII. 450 * 451 * Note that we don't care about the media instance. We 452 * are expecting to have multiple PHYs on the 10/100 cards, 453 * and on those cards we exclude the internal PHY from providing 454 * 10baseT. By ignoring the instance, it allows us to not have 455 * to specify it on the command line when switching media. 456 */ 457 mii->mii_ifp = ifp; 458 mii->mii_readreg = jme_mii_read; 459 mii->mii_writereg = jme_mii_write; 460 mii->mii_statchg = jme_statchg; 461 sc->jme_ec.ec_mii = mii; 462 ifmedia_init(&mii->mii_media, IFM_IMASK, jme_mediachange, 463 ether_mediastatus); 464 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 465 if (LIST_FIRST(&mii->mii_phys) == NULL) { 466 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 467 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 468 } else 469 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 470 471 /* 472 * We can support 802.1Q VLAN-sized frames. 473 */ 474 sc->jme_ec.ec_capabilities |= 475 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 476 sc->jme_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 477 478 if (sc->jme_flags & JME_FLAG_GIGA) 479 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 480 481 482 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 483 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 484 ifp->if_ioctl = jme_ifioctl; 485 ifp->if_start = jme_ifstart; 486 ifp->if_watchdog = jme_ifwatchdog; 487 ifp->if_init = jme_ifinit; 488 ifp->if_stop = jme_stop; 489 ifp->if_timer = 0; 490 ifp->if_capabilities |= 491 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 492 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 493 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 494 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 495 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 496 IFCAP_TSOv4 | IFCAP_TSOv6; 497 IFQ_SET_READY(&ifp->if_snd); 498 if_attach(ifp); 499 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 500 501 /* 502 * Add shutdown hook so that DMA is disabled prior to reboot. 503 */ 504 if (pmf_device_register1(self, NULL, NULL, jme_shutdown)) 505 pmf_class_network_register(self, ifp); 506 else 507 aprint_error_dev(self, "couldn't establish power handler\n"); 508 509 rnd_attach_source(&sc->rnd_source, device_xname(self), 510 RND_TYPE_NET, RND_FLAG_DEFAULT); 511 512 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 513 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 514 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 515 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 516 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 517 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 518 SYSCTL_DESCR("jme per-controller controls"), 519 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 520 CTL_EOL) != 0) { 521 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 522 return; 523 } 524 jme_nodenum = node->sysctl_num; 525 526 /* interrupt moderation sysctls */ 527 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 528 CTLFLAG_READWRITE, 529 CTLTYPE_INT, "int_rxto", 530 SYSCTL_DESCR("jme RX interrupt moderation timer"), 531 jme_sysctl_intrxto, 0, (void *)sc, 532 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 533 CTL_EOL) != 0) { 534 aprint_normal_dev(sc->jme_dev, 535 "couldn't create int_rxto sysctl node\n"); 536 } 537 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 538 CTLFLAG_READWRITE, 539 CTLTYPE_INT, "int_rxct", 540 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 541 jme_sysctl_intrxct, 0, (void *)sc, 542 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 543 CTL_EOL) != 0) { 544 aprint_normal_dev(sc->jme_dev, 545 "couldn't create int_rxct sysctl node\n"); 546 } 547 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 548 CTLFLAG_READWRITE, 549 CTLTYPE_INT, "int_txto", 550 SYSCTL_DESCR("jme TX interrupt moderation timer"), 551 jme_sysctl_inttxto, 0, (void *)sc, 552 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 553 CTL_EOL) != 0) { 554 aprint_normal_dev(sc->jme_dev, 555 "couldn't create int_txto sysctl node\n"); 556 } 557 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 558 CTLFLAG_READWRITE, 559 CTLTYPE_INT, "int_txct", 560 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 561 jme_sysctl_inttxct, 0, (void *)sc, 562 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 563 CTL_EOL) != 0) { 564 aprint_normal_dev(sc->jme_dev, 565 "couldn't create int_txct sysctl node\n"); 566 } 567 } 568 569 static void 570 jme_stop_rx(jme_softc_t *sc) 571 { 572 uint32_t reg; 573 int i; 574 575 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 576 if ((reg & RXCSR_RX_ENB) == 0) 577 return; 578 reg &= ~RXCSR_RX_ENB; 579 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 580 for (i = JME_TIMEOUT / 10; i > 0; i--) { 581 DELAY(10); 582 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 583 JME_RXCSR) & RXCSR_RX_ENB) == 0) 584 break; 585 } 586 if (i == 0) 587 aprint_error_dev(sc->jme_dev, "stopping receiver timeout!\n"); 588 589 } 590 591 static void 592 jme_stop_tx(jme_softc_t *sc) 593 { 594 uint32_t reg; 595 int i; 596 597 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 598 if ((reg & TXCSR_TX_ENB) == 0) 599 return; 600 reg &= ~TXCSR_TX_ENB; 601 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 602 for (i = JME_TIMEOUT / 10; i > 0; i--) { 603 DELAY(10); 604 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 605 JME_TXCSR) & TXCSR_TX_ENB) == 0) 606 break; 607 } 608 if (i == 0) 609 aprint_error_dev(sc->jme_dev, 610 "stopping transmitter timeout!\n"); 611 } 612 613 static void 614 jme_reset(jme_softc_t *sc) 615 { 616 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 617 DELAY(10); 618 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 619 } 620 621 static bool 622 jme_shutdown(device_t self, int howto) 623 { 624 jme_softc_t *sc; 625 struct ifnet *ifp; 626 627 sc = device_private(self); 628 ifp = &sc->jme_if; 629 jme_stop(ifp, 1); 630 631 return true; 632 } 633 634 static void 635 jme_stop(struct ifnet *ifp, int disable) 636 { 637 jme_softc_t *sc = ifp->if_softc; 638 int i; 639 /* Stop receiver, transmitter. */ 640 jme_stop_rx(sc); 641 jme_stop_tx(sc); 642 /* free receive mbufs */ 643 for (i = 0; i < JME_NBUFS; i++) { 644 if (sc->jme_rxmbuf[i]) { 645 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 646 m_freem(sc->jme_rxmbuf[i]); 647 } 648 sc->jme_rxmbuf[i] = NULL; 649 } 650 /* process completed transmits */ 651 jme_txeof(sc); 652 /* free abort pending transmits */ 653 for (i = 0; i < JME_NBUFS; i++) { 654 if (sc->jme_txmbuf[i]) { 655 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 656 m_freem(sc->jme_txmbuf[i]); 657 sc->jme_txmbuf[i] = NULL; 658 } 659 } 660 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 661 ifp->if_timer = 0; 662 } 663 664 #if 0 665 static void 666 jme_restart(void *v) 667 { 668 669 jme_init(v); 670 } 671 #endif 672 673 static int 674 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 675 { 676 int error; 677 bus_dmamap_t map; 678 int i = sc->jme_rx_prod; 679 680 if (sc->jme_rxmbuf[i] != NULL) { 681 aprint_error_dev(sc->jme_dev, 682 "mbuf already here: rxprod %d rxcons %d\n", 683 sc->jme_rx_prod, sc->jme_rx_cons); 684 if (m) 685 m_freem(m); 686 return EINVAL; 687 } 688 689 if (m == NULL) { 690 sc->jme_rxmbuf[i] = NULL; 691 MGETHDR(m, M_DONTWAIT, MT_DATA); 692 if (m == NULL) 693 return (ENOBUFS); 694 MCLGET(m, M_DONTWAIT); 695 if ((m->m_flags & M_EXT) == 0) { 696 m_freem(m); 697 return (ENOBUFS); 698 } 699 } 700 map = sc->jme_rxmbufm[i]; 701 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 702 KASSERT(m->m_len == MCLBYTES); 703 704 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 705 BUS_DMA_READ | BUS_DMA_NOWAIT); 706 if (error) { 707 sc->jme_rxmbuf[i] = NULL; 708 aprint_error_dev(sc->jme_dev, 709 "unable to load rx DMA map %d, error = %d\n", 710 i, error); 711 m_freem(m); 712 return (error); 713 } 714 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 715 BUS_DMASYNC_PREREAD); 716 717 sc->jme_rxmbuf[i] = m; 718 719 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 720 sc->jme_rxring[i].addr_lo = 721 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 722 sc->jme_rxring[i].addr_hi = 723 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 724 sc->jme_rxring[i].flags = 725 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 726 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 727 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 728 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 729 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 730 return (0); 731 } 732 733 static int 734 jme_ifinit(struct ifnet *ifp) 735 { 736 return jme_init(ifp, 1); 737 } 738 739 static int 740 jme_init(struct ifnet *ifp, int do_ifinit) 741 { 742 jme_softc_t *sc = ifp->if_softc; 743 int i, s; 744 uint8_t eaddr[ETHER_ADDR_LEN]; 745 uint32_t reg; 746 747 s = splnet(); 748 /* cancel any pending IO */ 749 jme_stop(ifp, 1); 750 jme_reset(sc); 751 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 752 splx(s); 753 return 0; 754 } 755 /* allocate receive ring */ 756 sc->jme_rx_prod = 0; 757 for (i = 0; i < JME_NBUFS; i++) { 758 if (jme_add_rxbuf(sc, NULL) < 0) { 759 aprint_error_dev(sc->jme_dev, 760 "can't allocate rx mbuf\n"); 761 for (i--; i >= 0; i--) { 762 bus_dmamap_unload(sc->jme_dmatag, 763 sc->jme_rxmbufm[i]); 764 m_freem(sc->jme_rxmbuf[i]); 765 sc->jme_rxmbuf[i] = NULL; 766 } 767 splx(s); 768 return ENOMEM; 769 } 770 } 771 /* init TX ring */ 772 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 773 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 774 0, JME_NBUFS * sizeof(struct jme_desc), 775 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 776 for (i = 0; i < JME_NBUFS; i++) 777 sc->jme_txmbuf[i] = NULL; 778 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 779 780 /* Reprogram the station address. */ 781 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 782 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 783 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 784 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 785 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 786 787 /* 788 * Configure Tx queue. 789 * Tx priority queue weight value : 0 790 * Tx FIFO threshold for processing next packet : 16QW 791 * Maximum Tx DMA length : 512 792 * Allow Tx DMA burst. 793 */ 794 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 795 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 796 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 797 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 798 sc->jme_txcsr |= TXCSR_DMA_BURST; 799 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 800 JME_TXCSR, sc->jme_txcsr); 801 802 /* Set Tx descriptor counter. */ 803 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 804 JME_TXQDC, JME_NBUFS); 805 806 /* Set Tx ring address to the hardware. */ 807 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 808 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 809 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 810 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 811 812 /* Configure TxMAC parameters. */ 813 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 814 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 815 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 816 817 /* 818 * Configure Rx queue. 819 * FIFO full threshold for transmitting Tx pause packet : 128T 820 * FIFO threshold for processing next packet : 128QW 821 * Rx queue 0 select 822 * Max Rx DMA length : 128 823 * Rx descriptor retry : 32 824 * Rx descriptor retry time gap : 256ns 825 * Don't receive runt/bad frame. 826 */ 827 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 828 /* 829 * Since Rx FIFO size is 4K bytes, receiving frames larger 830 * than 4K bytes will suffer from Rx FIFO overruns. So 831 * decrease FIFO threshold to reduce the FIFO overruns for 832 * frames larger than 4000 bytes. 833 * For best performance of standard MTU sized frames use 834 * maximum allowable FIFO threshold, 128QW. 835 */ 836 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 837 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 838 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 839 else 840 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 841 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 842 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 843 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 844 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 845 JME_RXCSR, sc->jme_rxcsr); 846 847 /* Set Rx descriptor counter. */ 848 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 849 JME_RXQDC, JME_NBUFS); 850 851 /* Set Rx ring address to the hardware. */ 852 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 853 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 854 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 855 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 856 857 /* Clear receive filter. */ 858 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 859 /* Set up the receive filter. */ 860 jme_set_filter(sc); 861 862 /* 863 * Disable all WOL bits as WOL can interfere normal Rx 864 * operation. Also clear WOL detection status bits. 865 */ 866 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 867 reg &= ~PMCS_WOL_ENB_MASK; 868 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 869 870 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 871 /* 872 * Pad 10bytes right before received frame. This will greatly 873 * help Rx performance on strict-alignment architectures as 874 * it does not need to copy the frame to align the payload. 875 */ 876 reg |= RXMAC_PAD_10BYTES; 877 if ((ifp->if_capenable & 878 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 879 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) != 0) 880 reg |= RXMAC_CSUM_ENB; 881 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 882 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 883 884 /* Configure general purpose reg0 */ 885 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 886 reg &= ~GPREG0_PCC_UNIT_MASK; 887 /* Set PCC timer resolution to micro-seconds unit. */ 888 reg |= GPREG0_PCC_UNIT_US; 889 /* 890 * Disable all shadow register posting as we have to read 891 * JME_INTR_STATUS register in jme_int_task. Also it seems 892 * that it's hard to synchronize interrupt status between 893 * hardware and software with shadow posting due to 894 * requirements of bus_dmamap_sync(9). 895 */ 896 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 897 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 898 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 899 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 900 /* Disable posting of DW0. */ 901 reg &= ~GPREG0_POST_DW0_ENB; 902 /* Clear PME message. */ 903 reg &= ~GPREG0_PME_ENB; 904 /* Set PHY address. */ 905 reg &= ~GPREG0_PHY_ADDR_MASK; 906 reg |= sc->jme_phyaddr; 907 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 908 909 /* Configure Tx queue 0 packet completion coalescing. */ 910 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 911 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 912 reg |= PCCTX_COAL_TXQ0; 913 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 914 915 /* Configure Rx queue 0 packet completion coalescing. */ 916 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 917 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 918 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 919 920 /* Disable Timers */ 921 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); 922 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 923 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 924 925 /* Configure retry transmit period, retry limit value. */ 926 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 927 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 928 TXTRHD_RT_PERIOD_MASK) | 929 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 930 TXTRHD_RT_LIMIT_SHIFT)); 931 932 /* Disable RSS. */ 933 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 934 JME_RSSC, RSSC_DIS_RSS); 935 936 /* Initialize the interrupt mask. */ 937 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 938 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 939 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 940 JME_INTR_STATUS, 0xFFFFFFFF); 941 942 /* set media, if not already handling a media change */ 943 if (do_ifinit) { 944 int error; 945 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 946 error = 0; 947 else if (error != 0) { 948 aprint_error_dev(sc->jme_dev, "could not set media\n"); 949 splx(s); 950 return error; 951 } 952 } 953 954 /* Program MAC with resolved speed/duplex/flow-control. */ 955 jme_mac_config(sc); 956 957 /* Start receiver/transmitter. */ 958 sc->jme_rx_cons = 0; 959 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 960 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 961 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 962 sc->jme_txcsr | TXCSR_TX_ENB); 963 964 /* start ticks calls */ 965 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 966 sc->jme_if.if_flags |= IFF_RUNNING; 967 sc->jme_if.if_flags &= ~IFF_OACTIVE; 968 splx(s); 969 return 0; 970 } 971 972 973 int 974 jme_mii_read(device_t self, int phy, int reg, uint16_t *val) 975 { 976 struct jme_softc *sc = device_private(self); 977 int data, i; 978 979 /* For FPGA version, PHY address 0 should be ignored. */ 980 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 981 if (phy == 0) 982 return -1; 983 } else { 984 if (sc->jme_phyaddr != phy) 985 return -1; 986 } 987 988 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 989 SMI_OP_READ | SMI_OP_EXECUTE | 990 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 991 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 992 delay(10); 993 if (((data = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 994 JME_SMI)) & SMI_OP_EXECUTE) == 0) 995 break; 996 } 997 998 if (i == 0) { 999 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 1000 return ETIMEDOUT; 1001 } 1002 1003 *val = (data & SMI_DATA_MASK) >> SMI_DATA_SHIFT; 1004 return 0; 1005 } 1006 1007 int 1008 jme_mii_write(device_t self, int phy, int reg, uint16_t val) 1009 { 1010 struct jme_softc *sc = device_private(self); 1011 int i; 1012 1013 /* For FPGA version, PHY address 0 should be ignored. */ 1014 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 1015 if (phy == 0) 1016 return -1; 1017 } else { 1018 if (sc->jme_phyaddr != phy) 1019 return -1; 1020 } 1021 1022 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1023 SMI_OP_WRITE | SMI_OP_EXECUTE | 1024 (((uint32_t)val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1025 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1026 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1027 delay(10); 1028 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1029 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1030 break; 1031 } 1032 1033 if (i == 0) { 1034 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1035 return ETIMEDOUT; 1036 } 1037 1038 return 0; 1039 } 1040 1041 void 1042 jme_statchg(struct ifnet *ifp) 1043 { 1044 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1045 jme_init(ifp, 0); 1046 } 1047 1048 static void 1049 jme_intr_rx(jme_softc_t *sc) { 1050 struct mbuf *m, *mhead; 1051 bus_dmamap_t mmap; 1052 struct ifnet *ifp = &sc->jme_if; 1053 uint32_t flags, buflen; 1054 int i, ipackets, nsegs, seg, error; 1055 struct jme_desc *desc; 1056 1057 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1058 sizeof(struct jme_desc) * JME_NBUFS, 1059 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1060 #ifdef JMEDEBUG_RX 1061 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1062 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1063 #endif 1064 ipackets = 0; 1065 while ((le32toh(sc->jme_rxring[sc->jme_rx_cons].flags) & JME_RD_OWN) 1066 == 0) { 1067 i = sc->jme_rx_cons; 1068 desc = &sc->jme_rxring[i]; 1069 #ifdef JMEDEBUG_RX 1070 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1071 i, le32toh(desc->flags), le32toh(desc->buflen)); 1072 #endif 1073 if (sc->jme_rxmbuf[i] == NULL) { 1074 if ((error = jme_add_rxbuf(sc, NULL)) != 0) { 1075 aprint_error_dev(sc->jme_dev, 1076 "can't add new mbuf to empty slot: %d\n", 1077 error); 1078 break; 1079 } 1080 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1081 i = sc->jme_rx_cons; 1082 continue; 1083 } 1084 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1085 break; 1086 1087 buflen = le32toh(desc->buflen); 1088 nsegs = JME_RX_NSEGS(buflen); 1089 flags = le32toh(desc->flags); 1090 if ((buflen & JME_RX_ERR_STAT) != 0 || 1091 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1092 JME_RX_BYTES(buflen) > 1093 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1094 #ifdef JMEDEBUG_RX 1095 printf("rx error flags 0x%x buflen 0x%x\n", 1096 flags, buflen); 1097 #endif 1098 ifp->if_ierrors++; 1099 /* reuse the mbufs */ 1100 for (seg = 0; seg < nsegs; seg++) { 1101 m = sc->jme_rxmbuf[i]; 1102 sc->jme_rxmbuf[i] = NULL; 1103 mmap = sc->jme_rxmbufm[i]; 1104 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1105 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1106 bus_dmamap_unload(sc->jme_dmatag, mmap); 1107 if ((error = jme_add_rxbuf(sc, m)) != 0) 1108 aprint_error_dev(sc->jme_dev, 1109 "can't reuse mbuf: %d\n", error); 1110 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1111 i = sc->jme_rx_cons; 1112 } 1113 continue; 1114 } 1115 /* receive this packet */ 1116 mhead = m = sc->jme_rxmbuf[i]; 1117 sc->jme_rxmbuf[i] = NULL; 1118 mmap = sc->jme_rxmbufm[i]; 1119 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1120 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1121 bus_dmamap_unload(sc->jme_dmatag, mmap); 1122 /* add a new buffer to chain */ 1123 if (jme_add_rxbuf(sc, NULL) != 0) { 1124 if ((error = jme_add_rxbuf(sc, m)) != 0) 1125 aprint_error_dev(sc->jme_dev, 1126 "can't reuse mbuf: %d\n", error); 1127 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1128 i = sc->jme_rx_cons; 1129 for (seg = 1; seg < nsegs; seg++) { 1130 m = sc->jme_rxmbuf[i]; 1131 sc->jme_rxmbuf[i] = NULL; 1132 mmap = sc->jme_rxmbufm[i]; 1133 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1134 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1135 bus_dmamap_unload(sc->jme_dmatag, mmap); 1136 if ((error = jme_add_rxbuf(sc, m)) != 0) 1137 aprint_error_dev(sc->jme_dev, 1138 "can't reuse mbuf: %d\n", error); 1139 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1140 i = sc->jme_rx_cons; 1141 } 1142 ifp->if_ierrors++; 1143 continue; 1144 } 1145 1146 /* build mbuf chain: head, then remaining segments */ 1147 m_set_rcvif(m, ifp); 1148 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1149 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1150 m->m_pkthdr.len; 1151 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1152 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1153 for (seg = 1; seg < nsegs; seg++) { 1154 i = sc->jme_rx_cons; 1155 m = sc->jme_rxmbuf[i]; 1156 sc->jme_rxmbuf[i] = NULL; 1157 mmap = sc->jme_rxmbufm[i]; 1158 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1159 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1160 bus_dmamap_unload(sc->jme_dmatag, mmap); 1161 if ((error = jme_add_rxbuf(sc, NULL)) != 0) 1162 aprint_error_dev(sc->jme_dev, 1163 "can't add new mbuf: %d\n", error); 1164 m->m_flags &= ~M_PKTHDR; 1165 m_cat(mhead, m); 1166 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1167 } 1168 /* and adjust last mbuf's size */ 1169 if (nsegs > 1) { 1170 m->m_len = 1171 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1172 } 1173 ipackets++; 1174 1175 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1176 (flags & JME_RD_IPV4)) { 1177 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1178 if (!(flags & JME_RD_IPCSUM)) 1179 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1180 } 1181 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1182 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1183 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1184 if (!(flags & JME_RD_TCPCSUM)) 1185 mhead->m_pkthdr.csum_flags |= 1186 M_CSUM_TCP_UDP_BAD; 1187 } 1188 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1189 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1190 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1191 if (!(flags & JME_RD_UDPCSUM)) 1192 mhead->m_pkthdr.csum_flags |= 1193 M_CSUM_TCP_UDP_BAD; 1194 } 1195 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1196 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1197 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1198 if (!(flags & JME_RD_TCPCSUM)) 1199 mhead->m_pkthdr.csum_flags |= 1200 M_CSUM_TCP_UDP_BAD; 1201 } 1202 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1203 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1204 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1205 if (!(flags & JME_RD_UDPCSUM)) 1206 mhead->m_pkthdr.csum_flags |= 1207 M_CSUM_TCP_UDP_BAD; 1208 } 1209 if (flags & JME_RD_VLAN_TAG) { 1210 /* pass to vlan_input() */ 1211 vlan_set_tag(mhead, (flags & JME_RD_VLAN_MASK)); 1212 } 1213 if_percpuq_enqueue(ifp->if_percpuq, mhead); 1214 } 1215 if (ipackets) 1216 rnd_add_uint32(&sc->rnd_source, ipackets); 1217 } 1218 1219 static int 1220 jme_intr(void *v) 1221 { 1222 jme_softc_t *sc = v; 1223 uint32_t istatus; 1224 1225 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1226 JME_INTR_STATUS); 1227 if (istatus == 0 || istatus == 0xFFFFFFFF) 1228 return 0; 1229 /* Disable interrupts. */ 1230 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1231 JME_INTR_MASK_CLR, 0xFFFFFFFF); 1232 again: 1233 /* and update istatus */ 1234 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1235 JME_INTR_STATUS); 1236 if ((istatus & JME_INTRS_CHECK) == 0) 1237 goto done; 1238 /* Reset PCC counter/timer and Ack interrupts. */ 1239 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1240 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1241 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1242 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1243 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1244 JME_INTR_STATUS, istatus); 1245 1246 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1247 goto done; 1248 #ifdef JMEDEBUG_RX 1249 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1250 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1251 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1252 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1253 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1254 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1255 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1256 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1257 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1258 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1259 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1260 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1261 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1262 #endif 1263 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1264 jme_intr_rx(sc); 1265 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1266 /* 1267 * Notify hardware availability of new Rx 1268 * buffers. 1269 * Reading RXCSR takes very long time under 1270 * heavy load so cache RXCSR value and writes 1271 * the ORed value with the kick command to 1272 * the RXCSR. This saves one register access 1273 * cycle. 1274 */ 1275 sc->jme_rx_cons = 0; 1276 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1277 JME_RXCSR, 1278 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1279 } 1280 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1281 jme_ifstart(&sc->jme_if); 1282 1283 goto again; 1284 1285 done: 1286 /* enable interrupts. */ 1287 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1288 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 1289 return 1; 1290 } 1291 1292 1293 static int 1294 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1295 { 1296 struct jme_softc *sc = ifp->if_softc; 1297 int s, error; 1298 struct ifreq *ifr; 1299 struct ifcapreq *ifcr; 1300 1301 s = splnet(); 1302 /* 1303 * we can't support at the same time jumbo frames and 1304 * TX checksums offload/TSO 1305 */ 1306 switch (cmd) { 1307 case SIOCSIFMTU: 1308 ifr = data; 1309 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1310 (ifp->if_capenable & ( 1311 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | 1312 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx | 1313 IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) { 1314 splx(s); 1315 return EINVAL; 1316 } 1317 break; 1318 case SIOCSIFCAP: 1319 ifcr = data; 1320 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1321 (ifcr->ifcr_capenable & ( 1322 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | 1323 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx | 1324 IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) { 1325 splx(s); 1326 return EINVAL; 1327 } 1328 break; 1329 } 1330 1331 error = ether_ioctl(ifp, cmd, data); 1332 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1333 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1334 jme_set_filter(sc); 1335 error = 0; 1336 } else { 1337 error = jme_init(ifp, 0); 1338 } 1339 } 1340 splx(s); 1341 return error; 1342 } 1343 1344 static int 1345 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1346 { 1347 struct jme_desc *desc; 1348 struct mbuf *m; 1349 int error, i, prod, headdsc, nsegs; 1350 uint32_t cflags, tso_segsz; 1351 1352 if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) 1353 != 0) { 1354 /* 1355 * Due to the adherence to NDIS specification JMC250 1356 * assumes upper stack computed TCP pseudo checksum 1357 * without including payload length. This breaks 1358 * checksum offload for TSO case so recompute TCP 1359 * pseudo checksum for JMC250. Hopefully this wouldn't 1360 * be much burden on modern CPUs. 1361 */ 1362 bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1363 int iphl = v4 ? 1364 M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) : 1365 M_CSUM_DATA_IPv6_IPHL((*m_head)->m_pkthdr.csum_data); 1366 /* 1367 * note: we support vlan offloading, so we should never have 1368 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1369 * right. 1370 */ 1371 int hlen = ETHER_HDR_LEN + iphl; 1372 1373 if (__predict_false((*m_head)->m_len < 1374 (hlen + sizeof(struct tcphdr)))) { 1375 /* 1376 * TCP/IP headers are not in the first mbuf; we need 1377 * to do this the slow and painful way. Let's just 1378 * hope this doesn't happen very often. 1379 */ 1380 struct tcphdr th; 1381 1382 m_copydata((*m_head), hlen, sizeof(th), &th); 1383 if (v4) { 1384 struct ip ip; 1385 1386 m_copydata((*m_head), ETHER_HDR_LEN, 1387 sizeof(ip), &ip); 1388 ip.ip_len = 0; 1389 m_copyback((*m_head), 1390 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1391 sizeof(ip.ip_len), &ip.ip_len); 1392 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1393 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1394 } else { 1395 #if INET6 1396 struct ip6_hdr ip6; 1397 1398 m_copydata((*m_head), ETHER_HDR_LEN, 1399 sizeof(ip6), &ip6); 1400 ip6.ip6_plen = 0; 1401 m_copyback((*m_head), ETHER_HDR_LEN + 1402 offsetof(struct ip6_hdr, ip6_plen), 1403 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1404 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1405 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1406 #endif /* INET6 */ 1407 } 1408 m_copyback((*m_head), 1409 hlen + offsetof(struct tcphdr, th_sum), 1410 sizeof(th.th_sum), &th.th_sum); 1411 1412 hlen += th.th_off << 2; 1413 } else { 1414 /* 1415 * TCP/IP headers are in the first mbuf; we can do 1416 * this the easy way. 1417 */ 1418 struct tcphdr *th; 1419 1420 if (v4) { 1421 struct ip *ip = 1422 (void *)(mtod((*m_head), char *) + 1423 ETHER_HDR_LEN); 1424 th = (void *)(mtod((*m_head), char *) + hlen); 1425 1426 ip->ip_len = 0; 1427 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1428 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1429 } else { 1430 #if INET6 1431 struct ip6_hdr *ip6 = 1432 (void *)(mtod((*m_head), char *) + 1433 ETHER_HDR_LEN); 1434 th = (void *)(mtod((*m_head), char *) + hlen); 1435 1436 ip6->ip6_plen = 0; 1437 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1438 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1439 #endif /* INET6 */ 1440 } 1441 hlen += th->th_off << 2; 1442 } 1443 1444 } 1445 1446 prod = sc->jme_tx_prod; 1447 1448 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1449 *m_head, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1450 if (error) { 1451 if (error == EFBIG) { 1452 log(LOG_ERR, "%s: Tx packet consumes too many " 1453 "DMA segments, dropping...\n", 1454 device_xname(sc->jme_dev)); 1455 m_freem(*m_head); 1456 m_head = NULL; 1457 } 1458 return (error); 1459 } 1460 /* 1461 * Check descriptor overrun. Leave one free descriptor. 1462 * Since we always use 64bit address mode for transmitting, 1463 * each Tx request requires one more dummy descriptor. 1464 */ 1465 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1466 #ifdef JMEDEBUG_TX 1467 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1468 #endif 1469 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1470 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1471 return (ENOBUFS); 1472 } 1473 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1474 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1475 1476 m = *m_head; 1477 cflags = 0; 1478 tso_segsz = 0; 1479 /* Configure checksum offload and TSO. */ 1480 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 1481 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1482 cflags |= JME_TD_TSO; 1483 } else { 1484 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1485 cflags |= JME_TD_IPCSUM; 1486 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) 1487 != 0) 1488 cflags |= JME_TD_TCPCSUM; 1489 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) 1490 != 0) 1491 cflags |= JME_TD_UDPCSUM; 1492 } 1493 /* Configure VLAN. */ 1494 if (vlan_has_tag(m)) { 1495 cflags |= (vlan_get_tag(m) & JME_TD_VLAN_MASK); 1496 cflags |= JME_TD_VLAN_TAG; 1497 } 1498 1499 desc = &sc->jme_txring[prod]; 1500 desc->flags = htole32(cflags); 1501 desc->buflen = htole32(tso_segsz); 1502 desc->addr_hi = htole32(m->m_pkthdr.len); 1503 desc->addr_lo = 0; 1504 headdsc = prod; 1505 sc->jme_tx_cnt++; 1506 JME_DESC_INC(prod, JME_NBUFS); 1507 for (i = 0; i < nsegs; i++) { 1508 desc = &sc->jme_txring[prod]; 1509 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1510 desc->buflen = 1511 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1512 desc->addr_hi = htole32( 1513 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1514 desc->addr_lo = htole32( 1515 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1516 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1517 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1518 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1519 sc->jme_txmbuf[prod] = NULL; 1520 sc->jme_tx_cnt++; 1521 JME_DESC_INC(prod, JME_NBUFS); 1522 } 1523 1524 /* Update producer index. */ 1525 sc->jme_tx_prod = prod; 1526 #ifdef JMEDEBUG_TX 1527 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1528 #endif 1529 /* 1530 * Finally request interrupt and give the first descriptor 1531 * ownership to hardware. 1532 */ 1533 desc = &sc->jme_txring[headdsc]; 1534 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1535 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1536 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1537 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1538 1539 sc->jme_txmbuf[headdsc] = m; 1540 return (0); 1541 } 1542 1543 static void 1544 jme_txeof(struct jme_softc *sc) 1545 { 1546 struct ifnet *ifp; 1547 struct jme_desc *desc; 1548 uint32_t status; 1549 int cons, cons0, nsegs, seg; 1550 1551 ifp = &sc->jme_if; 1552 1553 #ifdef JMEDEBUG_TX 1554 printf("jme_txeof cons %d prod %d\n", 1555 sc->jme_tx_cons, sc->jme_tx_prod); 1556 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1557 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1558 "JME_TXTRHD 0x%x\n", 1559 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1560 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1561 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1562 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1563 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1564 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1565 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1566 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1567 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1568 desc = &sc->jme_txring[cons]; 1569 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1570 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1571 JME_DESC_INC(cons, JME_NBUFS); 1572 } 1573 #endif 1574 1575 cons = sc->jme_tx_cons; 1576 if (cons == sc->jme_tx_prod) 1577 return; 1578 1579 /* 1580 * Go through our Tx list and free mbufs for those 1581 * frames which have been transmitted. 1582 */ 1583 for (; cons != sc->jme_tx_prod;) { 1584 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1585 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1586 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1587 1588 desc = &sc->jme_txring[cons]; 1589 status = le32toh(desc->flags); 1590 #ifdef JMEDEBUG_TX 1591 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1592 sc->jme_txmbufm[cons]->dm_nsegs); 1593 #endif 1594 if (status & JME_TD_OWN) 1595 break; 1596 1597 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1598 ifp->if_oerrors++; 1599 else { 1600 ifp->if_opackets++; 1601 if ((status & JME_TD_COLLISION) != 0) 1602 ifp->if_collisions += 1603 le32toh(desc->buflen) & 1604 JME_TD_BUF_LEN_MASK; 1605 } 1606 /* 1607 * Only the first descriptor of multi-descriptor 1608 * transmission is updated so driver have to skip entire 1609 * chained buffers for the transmitted frame. In other 1610 * words, JME_TD_OWN bit is valid only at the first 1611 * descriptor of a multi-descriptor transmission. 1612 */ 1613 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1614 cons0 = cons; 1615 JME_DESC_INC(cons, JME_NBUFS); 1616 for (seg = 1; seg < nsegs + 1; seg++) { 1617 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1618 cons * sizeof(struct jme_desc), 1619 sizeof(struct jme_desc), 1620 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1621 sc->jme_txring[cons].flags = 0; 1622 JME_DESC_INC(cons, JME_NBUFS); 1623 } 1624 /* Reclaim transferred mbufs. */ 1625 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1626 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1627 BUS_DMASYNC_POSTWRITE); 1628 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1629 1630 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1631 m_freem(sc->jme_txmbuf[cons0]); 1632 sc->jme_txmbuf[cons0] = NULL; 1633 sc->jme_tx_cnt -= nsegs + 1; 1634 KASSERT(sc->jme_tx_cnt >= 0); 1635 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1636 } 1637 sc->jme_tx_cons = cons; 1638 /* Unarm watchog timer when there is no pending descriptors in queue. */ 1639 if (sc->jme_tx_cnt == 0) 1640 ifp->if_timer = 0; 1641 #ifdef JMEDEBUG_TX 1642 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1643 #endif 1644 } 1645 1646 static void 1647 jme_ifstart(struct ifnet *ifp) 1648 { 1649 jme_softc_t *sc = ifp->if_softc; 1650 struct mbuf *mb_head; 1651 int enq; 1652 1653 /* 1654 * check if we can free some desc. 1655 * Clear TX interrupt status to reset TX coalescing counters. 1656 */ 1657 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1658 JME_INTR_STATUS, INTR_TXQ_COMP); 1659 jme_txeof(sc); 1660 1661 if ((sc->jme_if.if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1662 return; 1663 for (enq = 0;; enq++) { 1664 nexttx: 1665 /* Grab a paquet for output */ 1666 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1667 if (mb_head == NULL) { 1668 #ifdef JMEDEBUG_TX 1669 printf("%s: nothing to send\n", __func__); 1670 #endif 1671 break; 1672 } 1673 /* try to add this mbuf to the TX ring */ 1674 if (jme_encap(sc, &mb_head)) { 1675 if (mb_head == NULL) { 1676 ifp->if_oerrors++; 1677 /* packet dropped, try next one */ 1678 goto nexttx; 1679 } 1680 /* resource shortage, try again later */ 1681 IF_PREPEND(&ifp->if_snd, mb_head); 1682 ifp->if_flags |= IFF_OACTIVE; 1683 break; 1684 } 1685 /* Pass packet to bpf if there is a listener */ 1686 bpf_mtap(ifp, mb_head, BPF_D_OUT); 1687 } 1688 #ifdef JMEDEBUG_TX 1689 printf("jme_ifstart enq %d\n", enq); 1690 #endif 1691 if (enq) { 1692 /* 1693 * Set a 5 second timer just in case we don't hear from 1694 * the card again. 1695 */ 1696 ifp->if_timer = 5; 1697 /* 1698 * Reading TXCSR takes very long time under heavy load 1699 * so cache TXCSR value and writes the ORed value with 1700 * the kick command to the TXCSR. This saves one register 1701 * access cycle. 1702 */ 1703 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1704 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1705 #ifdef JMEDEBUG_TX 1706 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1707 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1708 "JME_TXTRHD 0x%x\n", 1709 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1710 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1711 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1712 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1713 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1714 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1715 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1716 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1717 #endif 1718 } 1719 } 1720 1721 static void 1722 jme_ifwatchdog(struct ifnet *ifp) 1723 { 1724 jme_softc_t *sc = ifp->if_softc; 1725 1726 if ((ifp->if_flags & IFF_RUNNING) == 0) 1727 return; 1728 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1729 ifp->if_oerrors++; 1730 jme_init(ifp, 0); 1731 } 1732 1733 static int 1734 jme_mediachange(struct ifnet *ifp) 1735 { 1736 int error; 1737 jme_softc_t *sc = ifp->if_softc; 1738 1739 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1740 error = 0; 1741 else if (error != 0) { 1742 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1743 return error; 1744 } 1745 return 0; 1746 } 1747 1748 static void 1749 jme_ticks(void *v) 1750 { 1751 jme_softc_t *sc = v; 1752 int s = splnet(); 1753 1754 /* Tick the MII. */ 1755 mii_tick(&sc->jme_mii); 1756 1757 /* every seconds */ 1758 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 1759 splx(s); 1760 } 1761 1762 static void 1763 jme_mac_config(jme_softc_t *sc) 1764 { 1765 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1766 struct mii_data *mii = &sc->jme_mii; 1767 1768 ghc = 0; 1769 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1770 rxmac &= ~RXMAC_FC_ENB; 1771 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1772 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1773 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1774 txpause &= ~TXPFC_PAUSE_ENB; 1775 1776 if (mii->mii_media_active & IFM_FDX) { 1777 ghc |= GHC_FULL_DUPLEX; 1778 rxmac &= ~RXMAC_COLL_DET_ENB; 1779 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1780 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1781 TXMAC_FRAME_BURST); 1782 /* Disable retry transmit timer/retry limit. */ 1783 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1784 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1785 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1786 } else { 1787 rxmac |= RXMAC_COLL_DET_ENB; 1788 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1789 /* Enable retry transmit timer/retry limit. */ 1790 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1791 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1792 } 1793 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1794 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1795 case IFM_10_T: 1796 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; 1797 break; 1798 case IFM_100_TX: 1799 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; 1800 break; 1801 case IFM_1000_T: 1802 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; 1803 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1804 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1805 break; 1806 default: 1807 break; 1808 } 1809 if ((sc->jme_flags & JME_FLAG_GIGA) && 1810 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1811 /* 1812 * Workaround occasional packet loss issue of JMC250 A2 1813 * when it runs on half-duplex media. 1814 */ 1815 #ifdef JMEDEBUG 1816 printf("JME250 A2 workaround\n"); 1817 #endif 1818 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1819 JME_GPREG1); 1820 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1821 gpreg &= ~GPREG1_HDPX_FIX; 1822 else 1823 gpreg |= GPREG1_HDPX_FIX; 1824 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1825 JME_GPREG1, gpreg); 1826 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1827 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1828 /* Extend interface FIFO depth. */ 1829 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1830 0x1B, 0x0000); 1831 } else { 1832 /* Select default interface FIFO depth. */ 1833 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1834 0x1B, 0x0004); 1835 } 1836 } 1837 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1838 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1839 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1840 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1841 } 1842 1843 static void 1844 jme_set_filter(jme_softc_t *sc) 1845 { 1846 struct ethercom *ec = &sc->jme_ec; 1847 struct ifnet *ifp = &sc->jme_if; 1848 struct ether_multistep step; 1849 struct ether_multi *enm; 1850 uint32_t hash[2] = {0, 0}; 1851 int i; 1852 uint32_t rxcfg; 1853 1854 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1855 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1856 RXMAC_ALLMULTI); 1857 /* Always accept frames destined to our station address. */ 1858 rxcfg |= RXMAC_UNICAST; 1859 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1860 rxcfg |= RXMAC_BROADCAST; 1861 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1862 if ((ifp->if_flags & IFF_PROMISC) != 0) 1863 rxcfg |= RXMAC_PROMISC; 1864 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1865 rxcfg |= RXMAC_ALLMULTI; 1866 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1867 JME_MAR0, 0xFFFFFFFF); 1868 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1869 JME_MAR1, 0xFFFFFFFF); 1870 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1871 JME_RXMAC, rxcfg); 1872 return; 1873 } 1874 /* 1875 * Set up the multicast address filter by passing all multicast 1876 * addresses through a CRC generator, and then using the low-order 1877 * 6 bits as an index into the 64 bit multicast hash table. The 1878 * high order bits select the register, while the rest of the bits 1879 * select the bit within the register. 1880 */ 1881 rxcfg |= RXMAC_MULTICAST; 1882 memset(hash, 0, sizeof(hash)); 1883 1884 ETHER_LOCK(ec); 1885 ETHER_FIRST_MULTI(step, ec, enm); 1886 while (enm != NULL) { 1887 #ifdef JEMDBUG 1888 printf("%s: addrs %s %s\n", __func__, 1889 ether_sprintf(enm->enm_addrlo), 1890 ether_sprintf(enm->enm_addrhi)); 1891 #endif 1892 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1893 i = ether_crc32_be(enm->enm_addrlo, 6); 1894 /* Just want the 6 least significant bits. */ 1895 i &= 0x3f; 1896 hash[i / 32] |= 1 << (i%32); 1897 } else { 1898 hash[0] = hash[1] = 0xffffffff; 1899 sc->jme_if.if_flags |= IFF_ALLMULTI; 1900 break; 1901 } 1902 ETHER_NEXT_MULTI(step, enm); 1903 } 1904 ETHER_UNLOCK(ec); 1905 #ifdef JMEDEBUG 1906 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1907 #endif 1908 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1909 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1910 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1911 } 1912 1913 #if 0 1914 static int 1915 jme_multicast_hash(uint8_t *a) 1916 { 1917 int hash; 1918 1919 #define DA(addr, bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1920 #define xor8(a,b,c,d,e,f,g,h) \ 1921 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1922 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1923 1924 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1925 DA(a,36), DA(a,42)); 1926 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1927 DA(a,37), DA(a,43)) << 1; 1928 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1929 DA(a,38), DA(a,44)) << 2; 1930 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1931 DA(a,39), DA(a,45)) << 3; 1932 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1933 DA(a,40), DA(a,46)) << 4; 1934 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1935 DA(a,41), DA(a,47)) << 5; 1936 1937 return hash; 1938 } 1939 #endif 1940 1941 static int 1942 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1943 { 1944 uint32_t reg; 1945 int i; 1946 1947 *val = 0; 1948 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1949 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1950 JME_SMBCSR); 1951 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1952 break; 1953 delay(10); 1954 } 1955 1956 if (i == 0) { 1957 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1958 return (ETIMEDOUT); 1959 } 1960 1961 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1962 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1963 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1964 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1965 delay(10); 1966 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1967 JME_SMBINTF); 1968 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1969 break; 1970 } 1971 1972 if (i == 0) { 1973 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1974 return (ETIMEDOUT); 1975 } 1976 1977 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1978 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1979 return (0); 1980 } 1981 1982 1983 static int 1984 jme_eeprom_macaddr(struct jme_softc *sc) 1985 { 1986 uint8_t eaddr[ETHER_ADDR_LEN]; 1987 uint8_t fup, reg, val; 1988 uint32_t offset; 1989 int match; 1990 1991 offset = 0; 1992 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1993 fup != JME_EEPROM_SIG0) 1994 return (ENOENT); 1995 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1996 fup != JME_EEPROM_SIG1) 1997 return (ENOENT); 1998 match = 0; 1999 do { 2000 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 2001 break; 2002 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 2003 == (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 2004 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 2005 break; 2006 if (reg >= JME_PAR0 && 2007 reg < JME_PAR0 + ETHER_ADDR_LEN) { 2008 if (jme_eeprom_read_byte(sc, offset + 2, 2009 &val) != 0) 2010 break; 2011 eaddr[reg - JME_PAR0] = val; 2012 match++; 2013 } 2014 } 2015 if (fup & JME_EEPROM_DESC_END) 2016 break; 2017 2018 /* Try next eeprom descriptor. */ 2019 offset += JME_EEPROM_DESC_BYTES; 2020 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 2021 2022 if (match == ETHER_ADDR_LEN) { 2023 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); 2024 return (0); 2025 } 2026 2027 return (ENOENT); 2028 } 2029 2030 static int 2031 jme_reg_macaddr(struct jme_softc *sc) 2032 { 2033 uint32_t par0, par1; 2034 2035 par0 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0); 2036 par1 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1); 2037 par1 &= 0xffff; 2038 if ((par0 == 0 && par1 == 0) || 2039 (par0 == 0xffffffff && par1 == 0xffff)) { 2040 return (ENOENT); 2041 } else { 2042 sc->jme_enaddr[0] = (par0 >> 0) & 0xff; 2043 sc->jme_enaddr[1] = (par0 >> 8) & 0xff; 2044 sc->jme_enaddr[2] = (par0 >> 16) & 0xff; 2045 sc->jme_enaddr[3] = (par0 >> 24) & 0xff; 2046 sc->jme_enaddr[4] = (par1 >> 0) & 0xff; 2047 sc->jme_enaddr[5] = (par1 >> 8) & 0xff; 2048 } 2049 return (0); 2050 } 2051 2052 /* 2053 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 2054 * set up in jme_pci_attach() 2055 */ 2056 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2057 { 2058 int rc; 2059 const struct sysctlnode *node; 2060 2061 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2062 0, CTLTYPE_NODE, "jme", 2063 SYSCTL_DESCR("jme interface controls"), 2064 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2065 goto err; 2066 } 2067 2068 jme_root_num = node->sysctl_num; 2069 return; 2070 2071 err: 2072 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2073 } 2074 2075 static int 2076 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2077 { 2078 int error, t; 2079 struct sysctlnode node; 2080 struct jme_softc *sc; 2081 uint32_t reg; 2082 2083 node = *rnode; 2084 sc = node.sysctl_data; 2085 t = sc->jme_intrxto; 2086 node.sysctl_data = &t; 2087 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2088 if (error || newp == NULL) 2089 return error; 2090 2091 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2092 return EINVAL; 2093 2094 /* 2095 * update the softc with sysctl-changed value, and mark 2096 * for hardware update 2097 */ 2098 sc->jme_intrxto = t; 2099 /* Configure Rx queue 0 packet completion coalescing. */ 2100 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2101 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2102 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2103 return 0; 2104 } 2105 2106 static int 2107 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2108 { 2109 int error, t; 2110 struct sysctlnode node; 2111 struct jme_softc *sc; 2112 uint32_t reg; 2113 2114 node = *rnode; 2115 sc = node.sysctl_data; 2116 t = sc->jme_intrxct; 2117 node.sysctl_data = &t; 2118 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2119 if (error || newp == NULL) 2120 return error; 2121 2122 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2123 return EINVAL; 2124 2125 /* 2126 * update the softc with sysctl-changed value, and mark 2127 * for hardware update 2128 */ 2129 sc->jme_intrxct = t; 2130 /* Configure Rx queue 0 packet completion coalescing. */ 2131 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2132 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2133 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2134 return 0; 2135 } 2136 2137 static int 2138 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2139 { 2140 int error, t; 2141 struct sysctlnode node; 2142 struct jme_softc *sc; 2143 uint32_t reg; 2144 2145 node = *rnode; 2146 sc = node.sysctl_data; 2147 t = sc->jme_inttxto; 2148 node.sysctl_data = &t; 2149 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2150 if (error || newp == NULL) 2151 return error; 2152 2153 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2154 return EINVAL; 2155 2156 /* 2157 * update the softc with sysctl-changed value, and mark 2158 * for hardware update 2159 */ 2160 sc->jme_inttxto = t; 2161 /* Configure Tx queue 0 packet completion coalescing. */ 2162 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2163 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2164 reg |= PCCTX_COAL_TXQ0; 2165 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2166 return 0; 2167 } 2168 2169 static int 2170 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2171 { 2172 int error, t; 2173 struct sysctlnode node; 2174 struct jme_softc *sc; 2175 uint32_t reg; 2176 2177 node = *rnode; 2178 sc = node.sysctl_data; 2179 t = sc->jme_inttxct; 2180 node.sysctl_data = &t; 2181 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2182 if (error || newp == NULL) 2183 return error; 2184 2185 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2186 return EINVAL; 2187 2188 /* 2189 * update the softc with sysctl-changed value, and mark 2190 * for hardware update 2191 */ 2192 sc->jme_inttxct = t; 2193 /* Configure Tx queue 0 packet completion coalescing. */ 2194 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2195 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2196 reg |= PCCTX_COAL_TXQ0; 2197 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2198 return 0; 2199 } 2200