1 /* $NetBSD: if_fxp_pci.c,v 1.16 2001/05/22 16:05:01 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include "opt_inet.h" 46 #include "opt_ns.h" 47 #include "bpfilter.h" 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #ifdef INET 76 #include <netinet/in.h> 77 #include <netinet/if_inarp.h> 78 #endif 79 80 #ifdef NS 81 #include <netns/ns.h> 82 #include <netns/ns_if.h> 83 #endif 84 85 #include <machine/bus.h> 86 #include <machine/intr.h> 87 88 #include <dev/mii/miivar.h> 89 90 #include <dev/ic/i82557reg.h> 91 #include <dev/ic/i82557var.h> 92 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcidevs.h> 96 97 struct fxp_pci_softc { 98 struct fxp_softc psc_fxp; 99 100 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 101 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 102 pcitag_t psc_tag; /* pci register tag */ 103 void *psc_powerhook; /* power hook */ 104 }; 105 106 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 107 void fxp_pci_attach __P((struct device *, struct device *, void *)); 108 109 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 110 static void fxp_pci_power __P((int why, void *arg)); 111 112 struct cfattach fxp_pci_ca = { 113 sizeof(struct fxp_pci_softc), fxp_pci_match, fxp_pci_attach 114 }; 115 116 const struct fxp_pci_product { 117 u_int32_t fpp_prodid; /* PCI product ID */ 118 const char *fpp_name; /* device name */ 119 } fxp_pci_products[] = { 120 { PCI_PRODUCT_INTEL_82557, 121 "Intel i82557 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82559ER, 123 "Intel i82559ER Ethernet" }, 124 { PCI_PRODUCT_INTEL_IN_BUSINESS, 125 "Intel InBusiness Ethernet" }, 126 { PCI_PRODUCT_INTEL_82801BA_LAN, 127 "Intel i82562 Ethernet" }, 128 { 0, 129 NULL }, 130 }; 131 132 static const struct fxp_pci_product * 133 fxp_pci_lookup(const struct pci_attach_args *pa) 134 { 135 const struct fxp_pci_product *fpp; 136 137 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 138 return (NULL); 139 140 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 141 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 142 return (fpp); 143 144 return (NULL); 145 } 146 147 int 148 fxp_pci_match(parent, match, aux) 149 struct device *parent; 150 struct cfdata *match; 151 void *aux; 152 { 153 struct pci_attach_args *pa = aux; 154 155 if (fxp_pci_lookup(pa) != NULL) 156 return (1); 157 158 return (0); 159 } 160 161 /* 162 * Restore PCI configuration registers that may have been clobbered. 163 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 164 * ethernet, after an APM suspend/resume, as well as after an ACPI 165 * D3->D0 transition. We call this function from a power hook after 166 * APM resume events, as well as after the ACPI D3->D0 transition. 167 */ 168 static void 169 fxp_pci_confreg_restore(psc) 170 struct fxp_pci_softc *psc; 171 { 172 pcireg_t reg; 173 174 #if 0 175 /* 176 * Check to see if the command register is blank -- if so, then 177 * we'll assume that all the clobberable-registers have been 178 * clobbered. 179 */ 180 181 /* 182 * In general, the above metric is accurate. Unfortunately, 183 * it is inaccurate across a hibernation. Ideally APM/ACPI 184 * code should take note of hibernation events and execute 185 * a hibernation wakeup hook, but at present a hibernation wake 186 * is indistinguishable from a suspend wake. 187 */ 188 189 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 190 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 191 return; 192 #else 193 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 194 #endif 195 196 pci_conf_write(psc->psc_pc, psc->psc_tag, 197 PCI_COMMAND_STATUS_REG, 198 (reg & 0xffff0000) | 199 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 200 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 201 psc->psc_regs[PCI_BHLC_REG>>2]); 202 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 203 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 204 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 205 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 206 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 207 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 208 } 209 210 211 /* 212 * Power handler routine. Called when the system is transitioning into/out 213 * of power save modes. We restore the (bashed) PCI configuration registers 214 * on a resume. 215 */ 216 static void 217 fxp_pci_power(why, arg) 218 int why; 219 void *arg; 220 { 221 struct fxp_pci_softc *psc = arg; 222 223 if (why == PWR_RESUME) 224 fxp_pci_confreg_restore(psc); 225 } 226 227 void 228 fxp_pci_attach(parent, self, aux) 229 struct device *parent, *self; 230 void *aux; 231 { 232 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 233 struct fxp_softc *sc = (struct fxp_softc *)self; 234 struct pci_attach_args *pa = aux; 235 pci_chipset_tag_t pc = pa->pa_pc; 236 pci_intr_handle_t ih; 237 const struct fxp_pci_product *fpp; 238 const char *intrstr = NULL; 239 bus_space_tag_t iot, memt; 240 bus_space_handle_t ioh, memh; 241 int ioh_valid, memh_valid; 242 bus_addr_t addr; 243 bus_size_t size; 244 int flags; 245 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 246 247 sc->sc_enabled = 1; 248 sc->sc_enable = NULL; 249 sc->sc_disable = NULL; 250 251 /* 252 * Map control/status registers. 253 */ 254 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 255 PCI_MAPREG_TYPE_IO, 0, 256 &iot, &ioh, NULL, NULL) == 0); 257 258 /* 259 * Version 2.1 of the PCI spec, page 196, "Address Maps": 260 * 261 * Prefetchable 262 * 263 * Set to one if there are no side effects on reads, the 264 * device returns all bytes regardless of the byte enables, 265 * and host bridges can merge processor writes into this 266 * range without causing errors. Bit must be set to zero 267 * otherwise. 268 * 269 * The 82557 incorrectly sets the "prefetchable" bit, resulting 270 * in errors on systems which will do merged reads and writes. 271 * These errors manifest themselves as all-bits-set when reading 272 * from the EEPROM or other < 4 byte registers. 273 * 274 * We must work around this problem by always forcing the mapping 275 * for memory space to be uncacheable. On systems which cannot 276 * create an uncacheable mapping (because the firmware mapped it 277 * into only cacheable/prefetchable space due to the "prefetchable" 278 * bit), we can fall back onto i/o mapped access. 279 */ 280 memh_valid = 0; 281 memt = pa->pa_memt; 282 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 283 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 284 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 285 &addr, &size, &flags) == 0) { 286 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 287 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 288 memh_valid = 1; 289 } 290 291 if (memh_valid) { 292 sc->sc_st = memt; 293 sc->sc_sh = memh; 294 } else if (ioh_valid) { 295 sc->sc_st = iot; 296 sc->sc_sh = ioh; 297 } else { 298 printf(": unable to map device registers\n"); 299 return; 300 } 301 302 sc->sc_dmat = pa->pa_dmat; 303 304 fpp = fxp_pci_lookup(pa); 305 if (fpp == NULL) { 306 printf("\n"); 307 panic("fxp_pci_attach: impossible"); 308 } 309 310 sc->sc_rev = PCI_REVISION(pa->pa_class); 311 312 switch (fpp->fpp_prodid) { 313 case PCI_PRODUCT_INTEL_82557: 314 case PCI_PRODUCT_INTEL_82559ER: 315 case PCI_PRODUCT_INTEL_IN_BUSINESS: 316 { 317 const char *chipname = NULL; 318 319 if (sc->sc_rev >= FXP_REV_82558_A4) { 320 chipname = "i82558 Ethernet"; 321 /* 322 * Enable the MWI command for memory writes. 323 */ 324 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 325 sc->sc_flags |= FXPF_MWI; 326 } 327 if (sc->sc_rev >= FXP_REV_82559_A0) 328 chipname = "i82559 Ethernet"; 329 if (sc->sc_rev >= FXP_REV_82559S_A) 330 chipname = "i82559S Ethernet"; 331 if (sc->sc_rev >= FXP_REV_82550) 332 chipname = "i82550 Ethernet"; 333 334 printf(": %s, rev %d\n", chipname != NULL ? chipname : 335 fpp->fpp_name, sc->sc_rev); 336 break; 337 } 338 339 case PCI_PRODUCT_INTEL_82801BA_LAN: 340 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 341 342 /* 343 * The 82801BA Ethernet has a bug which requires us to send a 344 * NOP before a CU_RESUME if we're in 10baseT mode. 345 */ 346 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 347 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 348 break; 349 350 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 351 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 352 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 353 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 354 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 355 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 356 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 357 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 358 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 359 360 /* 361 * ICH3 chips apparently have problems with the enhanced 362 * features, so just treat them as an i82557. It also 363 * has the resume bug that the ICH2 has. 364 */ 365 sc->sc_rev = 1; 366 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 367 break; 368 } 369 370 /* Make sure bus-mastering is enabled. */ 371 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 372 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 373 PCI_COMMAND_MASTER_ENABLE); 374 375 /* 376 * Under some circumstances (such as APM suspend/resume 377 * cycles, and across ACPI power state changes), the 378 * i82257-family can lose the contents of critical PCI 379 * configuration registers, causing the card to be 380 * non-responsive and useless. This occurs on the Sony VAIO 381 * Z505-series, among others. Preserve them here so they can 382 * be later restored (by fxp_pci_confreg_restore()). 383 */ 384 psc->psc_pc = pc; 385 psc->psc_tag = pa->pa_tag; 386 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 387 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 388 psc->psc_regs[PCI_BHLC_REG>>2] = 389 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 390 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 391 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 392 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 393 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 394 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 395 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 396 397 /* 398 * Work around BIOS ACPI bugs where the chip is inadvertantly 399 * left in ACPI D3 (lowest power state). First confirm the device 400 * supports ACPI power management, then move it to the D0 (fully 401 * functional) state if it is not already there. 402 */ 403 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 404 &pci_pwrmgmt_cap_reg, 0)) { 405 pcireg_t reg; 406 407 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 408 reg = pci_conf_read(pc, pa->pa_tag, pci_pwrmgmt_csr_reg); 409 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 410 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 411 (reg & ~PCI_PMCSR_STATE_MASK) | 412 PCI_PMCSR_STATE_D0); 413 } 414 } 415 /* Restore PCI configuration registers. */ 416 fxp_pci_confreg_restore(psc); 417 418 /* 419 * Map and establish our interrupt. 420 */ 421 if (pci_intr_map(pa, &ih)) { 422 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 423 return; 424 } 425 intrstr = pci_intr_string(pc, ih); 426 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 427 if (sc->sc_ih == NULL) { 428 printf("%s: couldn't establish interrupt", 429 sc->sc_dev.dv_xname); 430 if (intrstr != NULL) 431 printf(" at %s", intrstr); 432 printf("\n"); 433 return; 434 } 435 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 436 437 /* Finish off the attach. */ 438 fxp_attach(sc); 439 440 /* Add a suspend hook to restore PCI config state */ 441 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 442 if (psc->psc_powerhook == NULL) 443 printf ("%s: WARNING: unable to establish pci power hook\n", 444 sc->sc_dev.dv_xname); 445 446 } 447