1 /* $NetBSD: if_ath_pci.c,v 1.46 2012/08/04 04:05:36 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 /* 39 * Copyright (c) 2003 40 * Ichiro FUKUHARA <ichiro@ichiro.org>. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 52 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 56 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 #include <sys/cdefs.h> 66 __KERNEL_RCSID(0, "$NetBSD: if_ath_pci.c,v 1.46 2012/08/04 04:05:36 riastradh Exp $"); 67 68 /* 69 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/errno.h> 76 #include <sys/device.h> 77 #include <sys/module.h> 78 79 #include <external/isc/atheros_hal/dist/ah.h> 80 81 #include <dev/ic/ath_netbsd.h> 82 #include <dev/ic/athvar.h> 83 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcidevs.h> 87 88 /* 89 * PCI configuration space registers 90 */ 91 #define ATH_PCI_MMBA PCI_BAR(0) /* memory mapped base */ 92 93 struct ath_pci_softc { 94 struct ath_softc sc_sc; 95 pci_chipset_tag_t sc_pc; 96 pcitag_t sc_tag; 97 pci_intr_handle_t sc_pih; 98 void *sc_ih; 99 bus_space_tag_t sc_iot; 100 bus_space_handle_t sc_ioh; 101 bus_size_t sc_mapsz; 102 }; 103 104 static void ath_pci_attach(device_t, device_t, void *); 105 static int ath_pci_detach(device_t, int); 106 static int ath_pci_match(device_t, cfdata_t, void *); 107 static bool ath_pci_setup(struct ath_pci_softc *); 108 109 CFATTACH_DECL_NEW(ath_pci, sizeof(struct ath_pci_softc), 110 ath_pci_match, ath_pci_attach, ath_pci_detach, NULL); 111 112 static int 113 ath_pci_match(device_t parent, cfdata_t match, void *aux) 114 { 115 const char *devname; 116 struct pci_attach_args *pa = aux; 117 118 devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); 119 return (devname != NULL) ? 1 : 0; 120 } 121 122 static bool 123 ath_pci_suspend(device_t self, const pmf_qual_t *qual) 124 { 125 struct ath_pci_softc *sc = device_private(self); 126 127 ath_suspend(&sc->sc_sc); 128 if (sc->sc_ih != NULL) { 129 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 130 sc->sc_ih = NULL; 131 } 132 return true; 133 } 134 135 static bool 136 ath_pci_resume(device_t self, const pmf_qual_t *qual) 137 { 138 struct ath_pci_softc *sc = device_private(self); 139 140 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pih, IPL_NET, ath_intr, 141 &sc->sc_sc); 142 if (sc->sc_ih == NULL) { 143 aprint_error_dev(self, "couldn't map interrupt\n"); 144 return false; 145 } 146 return ath_resume(&sc->sc_sc); 147 } 148 149 static void 150 ath_pci_attach(device_t parent, device_t self, void *aux) 151 { 152 struct ath_pci_softc *psc = device_private(self); 153 struct ath_softc *sc = &psc->sc_sc; 154 struct pci_attach_args *pa = aux; 155 pci_chipset_tag_t pc = pa->pa_pc; 156 const char *intrstr = NULL; 157 const char *devname; 158 pcireg_t mem_type; 159 160 sc->sc_dev = self; 161 sc->sc_dmat = pa->pa_dmat; 162 psc->sc_pc = pc; 163 psc->sc_tag = pa->pa_tag; 164 165 devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); 166 aprint_normal(": %s\n", devname); 167 168 if (!ath_pci_setup(psc)) 169 goto bad; 170 171 /* 172 * Setup memory-mapping of PCI registers. 173 */ 174 mem_type = pci_mapreg_type(pc, pa->pa_tag, ATH_PCI_MMBA); 175 if (mem_type != PCI_MAPREG_TYPE_MEM && 176 mem_type != PCI_MAPREG_MEM_TYPE_64BIT) { 177 aprint_error_dev(self, "bad pci register type %d\n", 178 (int)mem_type); 179 goto bad; 180 } 181 if (pci_mapreg_map(pa, ATH_PCI_MMBA, mem_type, 0, &psc->sc_iot, 182 &psc->sc_ioh, NULL, &psc->sc_mapsz) != 0) { 183 aprint_error_dev(self, "cannot map register space\n"); 184 goto bad; 185 } 186 187 sc->sc_st = HALTAG(psc->sc_iot); 188 sc->sc_sh = HALHANDLE(psc->sc_ioh); 189 190 /* 191 * Arrange interrupt line. 192 */ 193 if (pci_intr_map(pa, &psc->sc_pih)) { 194 aprint_error("couldn't map interrupt\n"); 195 goto bad1; 196 } 197 198 intrstr = pci_intr_string(pc, psc->sc_pih); 199 psc->sc_ih = pci_intr_establish(pc, psc->sc_pih, IPL_NET, ath_intr, sc); 200 if (psc->sc_ih == NULL) { 201 aprint_error("couldn't map interrupt\n"); 202 goto bad1; 203 } 204 205 aprint_verbose_dev(self, "interrupting at %s\n", intrstr); 206 207 if (ath_attach(PCI_PRODUCT(pa->pa_id), sc) != 0) 208 goto bad3; 209 210 if (pmf_device_register(self, ath_pci_suspend, ath_pci_resume)) { 211 pmf_class_network_register(self, &sc->sc_if); 212 pmf_device_suspend(self, &sc->sc_qual); 213 } else 214 aprint_error_dev(self, "couldn't establish power handler\n"); 215 return; 216 bad3: 217 pci_intr_disestablish(pc, psc->sc_ih); 218 psc->sc_ih = NULL; 219 bad1: 220 bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); 221 psc->sc_mapsz = 0; 222 bad: 223 return; 224 } 225 226 static int 227 ath_pci_detach(device_t self, int flags) 228 { 229 struct ath_pci_softc *psc = device_private(self); 230 int rv; 231 232 if ((rv = ath_detach(&psc->sc_sc)) != 0) 233 return rv; 234 235 pmf_device_deregister(self); 236 237 if (psc->sc_ih != NULL) { 238 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 239 psc->sc_ih = NULL; 240 } 241 242 if (psc->sc_mapsz != 0) { 243 bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); 244 psc->sc_mapsz = 0; 245 } 246 247 return 0; 248 } 249 250 static bool 251 ath_pci_setup(struct ath_pci_softc *sc) 252 { 253 int rc; 254 pcireg_t bhlc, csr, icr, lattimer; 255 256 if ((rc = pci_set_powerstate(sc->sc_pc, sc->sc_tag, PCI_PWR_D0)) != 0) 257 aprint_debug("%s: pci_set_powerstate %d\n", __func__, rc); 258 /* 259 * Enable memory mapping and bus mastering. 260 */ 261 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 262 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 263 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr); 264 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 265 266 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 267 aprint_error_dev(sc->sc_sc.sc_dev, 268 "couldn't enable memory mapping\n"); 269 return false; 270 } 271 if ((csr & PCI_COMMAND_MASTER_ENABLE) == 0) { 272 aprint_error_dev(sc->sc_sc.sc_dev, 273 "couldn't enable bus mastering\n"); 274 return false; 275 } 276 277 /* 278 * XXX Both this comment and code are replicated in 279 * XXX cardbus_rescan(). 280 * 281 * Make sure the latency timer is set to some reasonable 282 * value. 283 * 284 * I will set the initial value of the Latency Timer here. 285 * 286 * While a PCI device owns the bus, its Latency Timer counts 287 * down bus cycles from its initial value to 0. Minimum 288 * Grant tells for how long the device wants to own the 289 * bus once it gets access, in units of 250ns. 290 * 291 * On a 33 MHz bus, there are 8 cycles per 250ns. So I 292 * multiply the Minimum Grant by 8 to find out the initial 293 * value of the Latency Timer. 294 * 295 * I never set a Latency Timer less than 0x10, since that 296 * is what the old code did. 297 */ 298 bhlc = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG); 299 icr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_INTERRUPT_REG); 300 lattimer = MAX(0x10, MIN(0xf8, 8 * PCI_MIN_GNT(icr))); 301 if (PCI_LATTIMER(bhlc) < lattimer) { 302 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 303 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 304 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG, bhlc); 305 } 306 return true; 307 } 308 309 MODULE(MODULE_CLASS_DRIVER, if_ath_pci, "ath,pci"); 310 311 #ifdef _MODULE 312 #include "ioconf.c" 313 #endif 314 315 static int 316 if_ath_pci_modcmd(modcmd_t cmd, void *opaque) 317 { 318 int error = 0; 319 320 switch (cmd) { 321 case MODULE_CMD_INIT: 322 #ifdef _MODULE 323 error = config_init_component(cfdriver_ioconf_if_ath_pci, 324 cfattach_ioconf_if_ath_pci, cfdata_ioconf_if_ath_pci); 325 #endif 326 return error; 327 case MODULE_CMD_FINI: 328 #ifdef _MODULE 329 error = config_fini_component(cfdriver_ioconf_if_ath_pci, 330 cfattach_ioconf_if_ath_pci, cfdata_ioconf_if_ath_pci); 331 #endif 332 return error; 333 default: 334 return ENOTTY; 335 } 336 } 337