1 /* $NetBSD: ahd_pci.c,v 1.37 2018/06/23 06:45:51 maxv Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 49 * - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.37 2018/06/23 06:45:51 maxv Exp $"); 54 55 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 56 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 57 58 #include <dev/ic/aic79xx_osm.h> 59 #include <dev/ic/aic79xx_inline.h> 60 61 static inline uint64_t 62 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 63 { 64 uint64_t id; 65 66 id = subvendor 67 | (subdevice << 16) 68 | ((uint64_t)vendor << 32) 69 | ((uint64_t)device << 48); 70 71 return (id); 72 } 73 74 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 75 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 76 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 77 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 78 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 79 80 #define ID_AIC7901 0x800F9005FFFF9005ull 81 #define ID_AHA_29320A 0x8000900500609005ull 82 #define ID_AHA_29320ALP 0x8017900500449005ull 83 #define ID_AHA_29320LPE 0x8017900500459005ull 84 85 #define ID_AIC7901A 0x801E9005FFFF9005ull 86 #define ID_AHA_29320LP 0x8014900500449005ull 87 88 #define ID_AIC7902 0x801F9005FFFF9005ull 89 #define ID_AIC7902_B 0x801D9005FFFF9005ull 90 #define ID_AHA_39320 0x8010900500409005ull 91 #define ID_AHA_29320 0x8012900500429005ull 92 #define ID_AHA_29320B 0x8013900500439005ull 93 #define ID_AHA_39320_B 0x8015900500409005ull 94 #define ID_AHA_39320A 0x8016900500409005ull 95 #define ID_AHA_39320D 0x8011900500419005ull 96 #define ID_AHA_39320D_B 0x801C900500419005ull 97 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 98 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 99 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 100 #define ID_AIC7902_PCI_REV_A4 0x3 101 #define ID_AIC7902_PCI_REV_B0 0x10 102 #define SUBID_HP 0x0E11 103 104 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 105 106 #define DEVID_9005_TYPE(id) ((id) & 0xF) 107 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 108 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 109 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 110 111 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 112 113 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 114 115 #define SUBID_9005_TYPE(id) ((id) & 0xF) 116 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 117 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 118 119 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 120 121 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 122 123 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 124 #define SUBID_9005_SEEPTYPE_NONE 0x0 125 #define SUBID_9005_SEEPTYPE_4K 0x1 126 127 static ahd_device_setup_t ahd_aic7901_setup; 128 static ahd_device_setup_t ahd_aic7901A_setup; 129 static ahd_device_setup_t ahd_aic7902_setup; 130 static ahd_device_setup_t ahd_aic790X_setup; 131 132 static const struct ahd_pci_identity ahd_pci_ident_table[] = 133 { 134 /* aic7901 based controllers */ 135 { 136 ID_AHA_29320A, 137 ID_ALL_MASK, 138 "Adaptec 29320A Ultra320 SCSI adapter", 139 ahd_aic7901_setup 140 }, 141 { 142 ID_AHA_29320ALP, 143 ID_ALL_MASK, 144 "Adaptec 29320ALP Ultra320 SCSI adapter", 145 ahd_aic7901_setup 146 }, 147 { 148 ID_AHA_29320LPE, 149 ID_ALL_MASK, 150 "Adaptec 29320LPE Ultra320 SCSI adapter", 151 ahd_aic7901_setup 152 }, 153 /* aic7901A based controllers */ 154 { 155 ID_AHA_29320LP, 156 ID_ALL_MASK, 157 "Adaptec 29320LP Ultra320 SCSI adapter", 158 ahd_aic7901A_setup 159 }, 160 /* aic7902 based controllers */ 161 { 162 ID_AHA_39320, 163 ID_ALL_MASK, 164 "Adaptec 39320 Ultra320 SCSI adapter", 165 ahd_aic7902_setup 166 }, 167 { 168 ID_AHA_39320_B, 169 ID_ALL_MASK, 170 "Adaptec 39320 Ultra320 SCSI adapter", 171 ahd_aic7902_setup 172 }, 173 { 174 ID_AHA_39320_B_DELL, 175 ID_ALL_IROC_MASK, 176 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 177 ahd_aic7902_setup 178 }, 179 { 180 ID_AHA_39320A, 181 ID_ALL_MASK, 182 "Adaptec 39320A Ultra320 SCSI adapter", 183 ahd_aic7902_setup 184 }, 185 { 186 ID_AHA_39320D, 187 ID_ALL_MASK, 188 "Adaptec 39320D Ultra320 SCSI adapter", 189 ahd_aic7902_setup 190 }, 191 { 192 ID_AHA_39320D_HP, 193 ID_ALL_MASK, 194 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 195 ahd_aic7902_setup 196 }, 197 { 198 ID_AHA_39320D_B, 199 ID_ALL_MASK, 200 "Adaptec 39320D Ultra320 SCSI adapter", 201 ahd_aic7902_setup 202 }, 203 { 204 ID_AHA_39320D_B_HP, 205 ID_ALL_MASK, 206 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 207 ahd_aic7902_setup 208 }, 209 /* Generic chip probes for devices we don't know 'exactly' */ 210 { 211 ID_AIC7901 & ID_9005_GENERIC_MASK, 212 ID_9005_GENERIC_MASK, 213 "Adaptec AIC7901 Ultra320 SCSI adapter", 214 ahd_aic7901_setup 215 }, 216 { 217 ID_AIC7901A & ID_DEV_VENDOR_MASK, 218 ID_DEV_VENDOR_MASK, 219 "Adaptec AIC7901A Ultra320 SCSI adapter", 220 ahd_aic7901A_setup 221 }, 222 { 223 ID_AIC7902 & ID_9005_GENERIC_MASK, 224 ID_9005_GENERIC_MASK, 225 "Adaptec AIC7902 Ultra320 SCSI adapter", 226 ahd_aic7902_setup 227 } 228 }; 229 230 static const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 231 232 #define DEVCONFIG 0x40 233 #define PCIXINITPAT 0x0000E000ul 234 #define PCIXINIT_PCI33_66 0x0000E000ul 235 #define PCIXINIT_PCIX50_66 0x0000C000ul 236 #define PCIXINIT_PCIX66_100 0x0000A000ul 237 #define PCIXINIT_PCIX100_133 0x00008000ul 238 #define PCI_BUS_MODES_INDEX(devconfig) \ 239 (((devconfig) & PCIXINITPAT) >> 13) 240 241 static const char *pci_bus_modes[] = 242 { 243 "PCI bus mode unknown", 244 "PCI bus mode unknown", 245 "PCI bus mode unknown", 246 "PCI bus mode unknown", 247 "PCI-X 101-133 MHz", 248 "PCI-X 67-100 MHz", 249 "PCI-X 50-66 MHz", 250 "PCI 33 or 66 MHz" 251 }; 252 253 #define TESTMODE 0x00000800ul 254 #define IRDY_RST 0x00000200ul 255 #define FRAME_RST 0x00000100ul 256 #define PCI64BIT 0x00000080ul 257 #define MRDCEN 0x00000040ul 258 #define ENDIANSEL 0x00000020ul 259 #define MIXQWENDIANEN 0x00000008ul 260 #define DACEN 0x00000004ul 261 #define STPWLEVEL 0x00000002ul 262 #define QWENDIANSEL 0x00000001ul 263 264 #define DEVCONFIG1 0x44 265 #define PREQDIS 0x01 266 267 #define LATTIME 0x0000ff00ul 268 269 static int ahd_check_extport(struct ahd_softc *ahd); 270 static void ahd_configure_termination(struct ahd_softc *ahd, 271 u_int adapter_control); 272 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 273 274 static int ahd_pci_test_register_access(struct ahd_softc *); 275 276 static int ahd_pci_intr(struct ahd_softc *); 277 278 static const struct ahd_pci_identity * 279 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 280 { 281 u_int64_t full_id; 282 const struct ahd_pci_identity *entry; 283 u_int i; 284 285 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 286 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 287 288 for (i = 0; i < ahd_num_pci_devs; i++) { 289 entry = &ahd_pci_ident_table[i]; 290 if (entry->full_id == (full_id & entry->id_mask)) 291 return (entry); 292 } 293 return (NULL); 294 } 295 296 static int 297 ahd_pci_probe(device_t parent, cfdata_t match, void *aux) 298 { 299 struct pci_attach_args *pa = aux; 300 const struct ahd_pci_identity *entry; 301 pcireg_t subid; 302 303 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 304 entry = ahd_find_pci_device(pa->pa_id, subid); 305 return entry != NULL ? 1 : 0; 306 } 307 308 static void 309 ahd_pci_attach(device_t parent, device_t self, void *aux) 310 { 311 struct pci_attach_args *pa = aux; 312 struct ahd_softc *ahd = device_private(self); 313 314 const struct ahd_pci_identity *entry; 315 316 uint32_t devconfig; 317 pcireg_t command; 318 int error; 319 pcireg_t subid; 320 uint16_t subvendor; 321 pcireg_t reg; 322 int ioh_valid, ioh2_valid, memh_valid; 323 pcireg_t memtype; 324 pci_intr_handle_t ih; 325 const char *intrstr; 326 struct ahd_pci_busdata *bd; 327 char intrbuf[PCI_INTRSTR_LEN]; 328 329 ahd->sc_dev = self; 330 ahd_set_name(ahd, device_xname(self)); 331 ahd->parent_dmat = pa->pa_dmat; 332 333 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 334 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 335 entry = ahd_find_pci_device(pa->pa_id, subid); 336 if (entry == NULL) 337 return; 338 339 /* Keep information about the PCI bus */ 340 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT|M_ZERO); 341 if (bd == NULL) { 342 aprint_error("%s: unable to allocate bus-specific data\n", 343 ahd_name(ahd)); 344 return; 345 } 346 347 bd->pc = pa->pa_pc; 348 bd->tag = pa->pa_tag; 349 bd->func = pa->pa_function; 350 bd->dev = pa->pa_device; 351 352 ahd->bus_data = bd; 353 354 ahd->description = entry->name; 355 356 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 357 M_DEVBUF, M_NOWAIT|M_ZERO); 358 if (ahd->seep_config == NULL) { 359 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 360 return; 361 } 362 363 LIST_INIT(&ahd->pending_scbs); 364 ahd_timer_init(&ahd->reset_timer); 365 ahd_timer_init(&ahd->stat_timer); 366 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 367 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 368 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 369 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 370 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 371 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 372 ahd->int_coalescing_stop_threshold = 373 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 374 375 if (ahd_platform_alloc(ahd, NULL) != 0) { 376 ahd_free(ahd); 377 return; 378 } 379 380 /* 381 * Record if this is an HP board. 382 */ 383 subvendor = PCI_VENDOR(subid); 384 if (subvendor == SUBID_HP) 385 ahd->flags |= AHD_HP_BOARD; 386 387 error = entry->setup(ahd, pa); 388 if (error != 0) 389 return; 390 391 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 392 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 393 ahd->chip |= AHD_PCI; 394 /* Disable PCIX workarounds when running in PCI mode. */ 395 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 396 } else { 397 ahd->chip |= AHD_PCIX; 398 } 399 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 400 401 memh_valid = ioh_valid = ioh2_valid = 0; 402 403 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 404 &bd->pcix_off, NULL)) { 405 if (ahd->chip & AHD_PCIX) 406 aprint_error_dev(self, 407 "warning: can't find PCI-X capability\n"); 408 ahd->chip &= ~AHD_PCIX; 409 ahd->chip |= AHD_PCI; 410 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 411 } 412 413 /* 414 * Map PCI Registers 415 */ 416 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 417 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 418 AHD_PCI_MEMADDR); 419 switch (memtype) { 420 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 421 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 422 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 423 memtype, 0, &ahd->tags[0], 424 &ahd->bshs[0], 425 NULL, NULL) == 0); 426 if (memh_valid) { 427 ahd->tags[1] = ahd->tags[0]; 428 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 429 /*offset*/0x100, 430 /*size*/0x100, 431 &ahd->bshs[1]); 432 if (ahd_pci_test_register_access(ahd) != 0) 433 memh_valid = 0; 434 } 435 break; 436 default: 437 memh_valid = 0; 438 aprint_error("%s: unknown memory type: 0x%x\n", 439 ahd_name(ahd), memtype); 440 break; 441 } 442 443 if (memh_valid) { 444 command &= ~PCI_COMMAND_IO_ENABLE; 445 pci_conf_write(pa->pa_pc, pa->pa_tag, 446 PCI_COMMAND_STATUS_REG, command); 447 } 448 #ifdef AHD_DEBUG 449 printf("%s: doing memory mapping shs0 0x%lx, shs1 0x%lx\n", 450 ahd_name(ahd), ahd->bshs[0], ahd->bshs[1]); 451 #endif 452 } 453 454 if (command & PCI_COMMAND_IO_ENABLE) { 455 /* First BAR */ 456 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 457 PCI_MAPREG_TYPE_IO, 0, 458 &ahd->tags[0], &ahd->bshs[0], 459 NULL, NULL) == 0); 460 461 /* 2nd BAR */ 462 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 463 PCI_MAPREG_TYPE_IO, 0, 464 &ahd->tags[1], &ahd->bshs[1], 465 NULL, NULL) == 0); 466 467 if (ioh_valid && ioh2_valid) { 468 KASSERT(memh_valid == 0); 469 command &= ~PCI_COMMAND_MEM_ENABLE; 470 pci_conf_write(pa->pa_pc, pa->pa_tag, 471 PCI_COMMAND_STATUS_REG, command); 472 } 473 #ifdef AHD_DEBUG 474 printf("%s: doing io mapping shs0 0x%lx, shs1 0x%lx\n", 475 ahd_name(ahd), ahd->bshs[0], ahd->bshs[1]); 476 #endif 477 478 } 479 480 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 481 aprint_error("%s: unable to map registers\n", ahd_name(ahd)); 482 return; 483 } 484 485 aprint_normal("\n"); 486 aprint_naive("\n"); 487 488 /* power up chip */ 489 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 490 pci_activate_null)) && error != EOPNOTSUPP) { 491 aprint_error_dev(self, "cannot activate %d\n", error); 492 return; 493 } 494 /* 495 * Should we bother disabling 39Bit addressing 496 * based on installed memory? 497 */ 498 if (sizeof(bus_addr_t) > 4) 499 ahd->flags |= AHD_39BIT_ADDRESSING; 500 501 /* 502 * If we need to support high memory, enable dual 503 * address cycles. This bit must be set to enable 504 * high address bit generation even if we are on a 505 * 64bit bus (PCI64BIT set in devconfig). 506 */ 507 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 508 uint32_t dvconfig; 509 510 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 511 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 512 dvconfig |= DACEN; 513 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, dvconfig); 514 } 515 516 /* Ensure busmastering is enabled */ 517 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 518 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 519 reg | PCI_COMMAND_MASTER_ENABLE); 520 521 ahd_softc_init(ahd); 522 523 /* 524 * Map the interrupt routines 525 */ 526 ahd->bus_intr = ahd_pci_intr; 527 528 error = ahd_reset(ahd, /*reinit*/FALSE); 529 if (error != 0) { 530 ahd_free(ahd); 531 return; 532 } 533 534 if (pci_intr_map(pa, &ih)) { 535 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd)); 536 ahd_free(ahd); 537 return; 538 } 539 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 540 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 541 if (ahd->ih == NULL) { 542 aprint_error("%s: couldn't establish interrupt", 543 ahd_name(ahd)); 544 if (intrstr != NULL) 545 aprint_error(" at %s", intrstr); 546 aprint_error("\n"); 547 ahd_free(ahd); 548 return; 549 } 550 if (intrstr != NULL) 551 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd), 552 intrstr); 553 554 /* Get the size of the cache */ 555 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 556 ahd->pci_cachesize *= 4; 557 558 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 559 /* See if we have a SEEPROM and perform auto-term */ 560 error = ahd_check_extport(ahd); 561 if (error != 0) 562 return; 563 564 /* Core initialization */ 565 error = ahd_init(ahd); 566 if (error != 0) 567 return; 568 569 /* 570 * Link this softc in with all other ahd instances. 571 */ 572 ahd_attach(ahd); 573 } 574 575 CFATTACH_DECL_NEW(ahd_pci, sizeof(struct ahd_softc), 576 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 577 578 /* 579 * Perform some simple tests that should catch situations where 580 * our registers are invalidly mapped. 581 */ 582 static int 583 ahd_pci_test_register_access(struct ahd_softc *ahd) 584 { 585 uint32_t cmd; 586 struct ahd_pci_busdata *bd = ahd->bus_data; 587 u_int targpcistat; 588 uint32_t pci_status1; 589 int error; 590 uint8_t hcntrl; 591 592 error = EIO; 593 594 /* 595 * Enable PCI error interrupt status, but suppress NMIs 596 * generated by SERR raised due to target aborts. 597 */ 598 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 599 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 600 cmd & ~PCI_COMMAND_SERR_ENABLE); 601 602 /* 603 * First a simple test to see if any 604 * registers can be read. Reading 605 * HCNTRL has no side effects and has 606 * at least one bit that is guaranteed to 607 * be zero so it is a good register to 608 * use for this test. 609 */ 610 hcntrl = ahd_inb(ahd, HCNTRL); 611 if (hcntrl == 0xFF) 612 goto fail; 613 614 /* 615 * Next create a situation where write combining 616 * or read prefetching could be initiated by the 617 * CPU or host bridge. Our device does not support 618 * either, so look for data corruption and/or flaged 619 * PCI errors. First pause without causing another 620 * chip reset. 621 */ 622 hcntrl &= ~CHIPRST; 623 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 624 while (ahd_is_paused(ahd) == 0) 625 ; 626 627 /* Clear any PCI errors that occurred before our driver attached. */ 628 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 629 targpcistat = ahd_inb(ahd, TARGPCISTAT); 630 ahd_outb(ahd, TARGPCISTAT, targpcistat); 631 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 632 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 633 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 634 ahd_outb(ahd, CLRINT, CLRPCIINT); 635 636 ahd_outb(ahd, SEQCTL0, PERRORDIS); 637 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 638 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 639 goto fail; 640 641 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 642 u_int trgpcistat; 643 644 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 645 trgpcistat = ahd_inb(ahd, TARGPCISTAT); 646 if ((trgpcistat & STA) != 0) 647 goto fail; 648 } 649 650 error = 0; 651 652 fail: 653 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 654 655 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 656 targpcistat = ahd_inb(ahd, TARGPCISTAT); 657 658 /* Silently clear any latched errors. */ 659 ahd_outb(ahd, TARGPCISTAT, targpcistat); 660 pci_status1 = pci_conf_read(bd->pc, bd->tag, 661 PCI_COMMAND_STATUS_REG); 662 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 663 pci_status1); 664 ahd_outb(ahd, CLRINT, CLRPCIINT); 665 } 666 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 667 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 668 return (error); 669 } 670 671 /* 672 * Check the external port logic for a serial eeprom 673 * and termination/cable detection contrls. 674 */ 675 static int 676 ahd_check_extport(struct ahd_softc *ahd) 677 { 678 struct vpd_config vpd; 679 struct seeprom_config *sc; 680 u_int adapter_control; 681 int have_seeprom; 682 int error; 683 684 sc = ahd->seep_config; 685 have_seeprom = ahd_acquire_seeprom(ahd); 686 if (have_seeprom) { 687 u_int start_addr; 688 689 /* 690 * Fetch VPD for this function and parse it. 691 */ 692 #ifdef AHD_DEBUG 693 printf("%s: Reading VPD from SEEPROM...", 694 ahd_name(ahd)); 695 #endif 696 /* Address is always in units of 16bit words */ 697 start_addr = ((2 * sizeof(*sc)) 698 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 699 700 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 701 start_addr, sizeof(vpd)/2, 702 /*bytestream*/TRUE); 703 if (error == 0) 704 error = ahd_parse_vpddata(ahd, &vpd); 705 #ifdef AHD_DEBUG 706 printf("%s: VPD parsing %s\n", 707 ahd_name(ahd), 708 error == 0 ? "successful" : "failed"); 709 #endif 710 711 #ifdef AHD_DEBUG 712 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 713 #endif 714 715 /* Address is always in units of 16bit words */ 716 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 717 718 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 719 start_addr, sizeof(*sc)/2, 720 /*bytestream*/FALSE); 721 722 if (error != 0) { 723 #ifdef AHD_DEBUG 724 printf("Unable to read SEEPROM\n"); 725 #endif 726 have_seeprom = 0; 727 } else { 728 have_seeprom = ahd_verify_cksum(sc); 729 #ifdef AHD_DEBUG 730 if (have_seeprom == 0) 731 printf ("checksum error\n"); 732 else 733 printf ("done.\n"); 734 #endif 735 } 736 ahd_release_seeprom(ahd); 737 } 738 739 if (!have_seeprom) { 740 u_int nvram_scb; 741 742 /* 743 * Pull scratch ram settings and treat them as 744 * if they are the contents of an seeprom if 745 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 746 * in SCB 0xFF. We manually compose the data as 16bit 747 * values to avoid endian issues. 748 */ 749 ahd_set_scbptr(ahd, 0xFF); 750 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 751 if (nvram_scb != 0xFF 752 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 753 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 754 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 755 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 756 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 757 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 758 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 759 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 760 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 761 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 762 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 763 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 764 uint16_t *sc_data; 765 int i; 766 767 ahd_set_scbptr(ahd, nvram_scb); 768 sc_data = (uint16_t *)sc; 769 for (i = 0; i < 64; i += 2) 770 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 771 have_seeprom = ahd_verify_cksum(sc); 772 if (have_seeprom) 773 ahd->flags |= AHD_SCB_CONFIG_USED; 774 } 775 } 776 777 #ifdef AHD_DEBUG 778 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 779 uint16_t *sc_data; 780 int i; 781 782 printf("%s: Seeprom Contents:", ahd_name(ahd)); 783 sc_data = (uint16_t *)sc; 784 for (i = 0; i < (sizeof(*sc)); i += 2) 785 printf("\n\t0x%.4x", sc_data[i]); 786 printf("\n"); 787 } 788 #endif 789 790 if (!have_seeprom) { 791 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd)); 792 ahd->flags |= AHD_USEDEFAULTS; 793 error = ahd_default_config(ahd); 794 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 795 free(ahd->seep_config, M_DEVBUF); 796 ahd->seep_config = NULL; 797 } else { 798 error = ahd_parse_cfgdata(ahd, sc); 799 adapter_control = sc->adapter_control; 800 } 801 if (error != 0) 802 return (error); 803 804 ahd_configure_termination(ahd, adapter_control); 805 806 return (0); 807 } 808 809 static void 810 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 811 { 812 int error; 813 u_int sxfrctl1; 814 uint8_t termctl; 815 uint32_t devconfig; 816 struct ahd_pci_busdata *bd = ahd->bus_data; 817 818 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 819 devconfig &= ~STPWLEVEL; 820 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 821 devconfig |= STPWLEVEL; 822 #ifdef AHD_DEBUG 823 printf("%s: STPWLEVEL is %s\n", 824 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 825 #endif 826 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 827 828 /* Make sure current sensing is off. */ 829 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 830 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 831 } 832 833 /* 834 * Read to sense. Write to set. 835 */ 836 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 837 if ((adapter_control & CFAUTOTERM) == 0) { 838 if (bootverbose) 839 printf("%s: Manual Primary Termination\n", 840 ahd_name(ahd)); 841 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 842 if ((adapter_control & CFSTERM) != 0) 843 termctl |= FLX_TERMCTL_ENPRILOW; 844 if ((adapter_control & CFWSTERM) != 0) 845 termctl |= FLX_TERMCTL_ENPRIHIGH; 846 } else if (error != 0) { 847 if (bootverbose) 848 printf("%s: Primary Auto-Term Sensing failed! " 849 "Using Defaults.\n", ahd_name(ahd)); 850 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 851 } 852 853 if ((adapter_control & CFSEAUTOTERM) == 0) { 854 if (bootverbose) 855 printf("%s: Manual Secondary Termination\n", 856 ahd_name(ahd)); 857 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 858 if ((adapter_control & CFSELOWTERM) != 0) 859 termctl |= FLX_TERMCTL_ENSECLOW; 860 if ((adapter_control & CFSEHIGHTERM) != 0) 861 termctl |= FLX_TERMCTL_ENSECHIGH; 862 } else if (error != 0) { 863 if (bootverbose) 864 printf("%s: Secondary Auto-Term Sensing failed! " 865 "Using Defaults.\n", ahd_name(ahd)); 866 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 867 } 868 869 /* 870 * Now set the termination based on what we found. 871 */ 872 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 873 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 874 ahd->flags |= AHD_TERM_ENB_A; 875 sxfrctl1 |= STPWEN; 876 } 877 /* Must set the latch once in order to be effective. */ 878 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 879 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 880 881 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 882 if (error != 0) { 883 aprint_error("%s: Unable to set termination settings!\n", 884 ahd_name(ahd)); 885 } else { 886 if (bootverbose) { 887 printf("%s: Primary High byte termination %sabled\n", 888 ahd_name(ahd), 889 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 890 891 printf("%s: Primary Low byte termination %sabled\n", 892 ahd_name(ahd), 893 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 894 895 printf("%s: Secondary High byte termination %sabled\n", 896 ahd_name(ahd), 897 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 898 899 printf("%s: Secondary Low byte termination %sabled\n", 900 ahd_name(ahd), 901 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 902 } 903 } 904 return; 905 } 906 907 #define DPE 0x80 908 #define SSE 0x40 909 #define RMA 0x20 910 #define RTA 0x10 911 #define STA 0x08 912 #define DPR 0x01 913 914 static const char *split_status_source[] = 915 { 916 "DFF0", 917 "DFF1", 918 "OVLY", 919 "CMC", 920 }; 921 922 static const char *pci_status_source[] = 923 { 924 "DFF0", 925 "DFF1", 926 "SG", 927 "CMC", 928 "OVLY", 929 "NONE", 930 "MSI", 931 "TARG" 932 }; 933 934 static const char *split_status_strings[] = 935 { 936 "%s: Received split response in %s.\n", 937 "%s: Received split completion error message in %s\n", 938 "%s: Receive overrun in %s\n", 939 "%s: Count not complete in %s\n", 940 "%s: Split completion data bucket in %s\n", 941 "%s: Split completion address error in %s\n", 942 "%s: Split completion byte count error in %s\n", 943 "%s: Signaled Target-abort to early terminate a split in %s\n" 944 }; 945 946 static const char *pci_status_strings[] = 947 { 948 "%s: Data Parity Error has been reported via PERR# in %s\n", 949 "%s: Target initial wait state error in %s\n", 950 "%s: Split completion read data parity error in %s\n", 951 "%s: Split completion address attribute parity error in %s\n", 952 "%s: Received a Target Abort in %s\n", 953 "%s: Received a Master Abort in %s\n", 954 "%s: Signal System Error Detected in %s\n", 955 "%s: Address or Write Phase Parity Error Detected in %s.\n" 956 }; 957 958 static int 959 ahd_pci_intr(struct ahd_softc *ahd) 960 { 961 uint8_t pci_status[8]; 962 ahd_mode_state saved_modes; 963 u_int pci_status1; 964 u_int intstat; 965 u_int i; 966 u_int reg; 967 struct ahd_pci_busdata *bd = ahd->bus_data; 968 969 intstat = ahd_inb(ahd, INTSTAT); 970 971 if ((intstat & SPLTINT) != 0) 972 ahd_pci_split_intr(ahd, intstat); 973 974 if ((intstat & PCIINT) == 0) 975 return 0; 976 977 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 978 saved_modes = ahd_save_modes(ahd); 979 ahd_dump_card_state(ahd); 980 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 981 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 982 983 if (i == 5) 984 continue; 985 pci_status[i] = ahd_inb(ahd, reg); 986 /* Clear latched errors. So our interrupt deasserts. */ 987 ahd_outb(ahd, reg, pci_status[i]); 988 } 989 990 for (i = 0; i < 8; i++) { 991 u_int bit; 992 993 if (i == 5) 994 continue; 995 996 for (bit = 0; bit < 8; bit++) { 997 998 if ((pci_status[i] & (0x1 << bit)) != 0) { 999 static const char *s; 1000 1001 s = pci_status_strings[bit]; 1002 if (i == 7/*TARG*/ && bit == 3) 1003 s = "%s: Signaled Target Abort\n"; 1004 printf(s, ahd_name(ahd), pci_status_source[i]); 1005 } 1006 } 1007 } 1008 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1009 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1010 1011 ahd_restore_modes(ahd, saved_modes); 1012 ahd_outb(ahd, CLRINT, CLRPCIINT); 1013 ahd_unpause(ahd); 1014 1015 return 1; 1016 } 1017 1018 static void 1019 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 1020 { 1021 uint8_t split_status[4]; 1022 uint8_t split_status1[4]; 1023 uint8_t sg_split_status[2]; 1024 uint8_t sg_split_status1[2]; 1025 ahd_mode_state saved_modes; 1026 u_int i; 1027 pcireg_t pcix_status; 1028 struct ahd_pci_busdata *bd = ahd->bus_data; 1029 1030 /* 1031 * Check for splits in all modes. Modes 0 and 1 1032 * additionally have SG engine splits to look at. 1033 */ 1034 pcix_status = pci_conf_read(bd->pc, bd->tag, 1035 bd->pcix_off + PCIX_STATUS); 1036 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1037 ahd_name(ahd), pcix_status); 1038 1039 saved_modes = ahd_save_modes(ahd); 1040 for (i = 0; i < 4; i++) { 1041 ahd_set_modes(ahd, i, i); 1042 1043 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1044 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1045 /* Clear latched errors. So our interrupt deasserts. */ 1046 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1047 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1048 if (i > 1) 1049 continue; 1050 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1051 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1052 /* Clear latched errors. So our interrupt deasserts. */ 1053 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1054 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1055 } 1056 1057 for (i = 0; i < 4; i++) { 1058 u_int bit; 1059 1060 for (bit = 0; bit < 8; bit++) { 1061 1062 if ((split_status[i] & (0x1 << bit)) != 0) { 1063 static const char *s; 1064 1065 s = split_status_strings[bit]; 1066 printf(s, ahd_name(ahd), 1067 split_status_source[i]); 1068 } 1069 1070 if (i > 0) 1071 continue; 1072 1073 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1074 static const char *s; 1075 1076 s = split_status_strings[bit]; 1077 printf(s, ahd_name(ahd), "SG"); 1078 } 1079 } 1080 } 1081 /* 1082 * Clear PCI-X status bits. 1083 */ 1084 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCIX_STATUS, 1085 pcix_status); 1086 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1087 ahd_restore_modes(ahd, saved_modes); 1088 } 1089 1090 static int 1091 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1092 { 1093 1094 ahd->chip = AHD_AIC7901; 1095 ahd->features = AHD_AIC7901_FE; 1096 return (ahd_aic790X_setup(ahd, pa)); 1097 } 1098 1099 static int 1100 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1101 { 1102 1103 ahd->chip = AHD_AIC7901A; 1104 ahd->features = AHD_AIC7901A_FE; 1105 return (ahd_aic790X_setup(ahd, pa)); 1106 } 1107 1108 static int 1109 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1110 { 1111 1112 ahd->chip = AHD_AIC7902; 1113 ahd->features = AHD_AIC7902_FE; 1114 return (ahd_aic790X_setup(ahd, pa)); 1115 } 1116 1117 static int 1118 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1119 { 1120 u_int rev; 1121 1122 rev = PCI_REVISION(pa->pa_class); 1123 #ifdef AHD_DEBUG 1124 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1125 #endif 1126 if (rev < ID_AIC7902_PCI_REV_A4) { 1127 aprint_error("%s: Unable to attach to " 1128 "unsupported chip revision %d\n", ahd_name(ahd), rev); 1129 pci_conf_write(pa->pa_pc, pa->pa_tag, 1130 PCI_COMMAND_STATUS_REG, 0); 1131 return (ENXIO); 1132 } 1133 1134 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1135 if (rev < ID_AIC7902_PCI_REV_B0) { 1136 /* 1137 * Enable A series workarounds. 1138 */ 1139 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1140 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1141 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1142 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1143 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1144 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1145 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1146 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1147 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1148 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1149 | AHD_FAINT_LED_BUG; 1150 1151 1152 /* 1153 * IO Cell parameter setup. 1154 */ 1155 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1156 1157 if ((ahd->flags & AHD_HP_BOARD) == 0) 1158 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1159 } else { 1160 u_int devconfig1; 1161 1162 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1163 | AHD_NEW_DFCNTRL_OPTS; 1164 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1165 1166 /* 1167 * Some issues have been resolved in the 7901B. 1168 */ 1169 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1170 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1171 1172 /* 1173 * IO Cell parameter setup. 1174 */ 1175 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1176 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1177 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1178 1179 /* 1180 * Set the PREQDIS bit for H2B which disables some workaround 1181 * that doesn't work on regular PCI busses. 1182 * XXX - Find out exactly what this does from the hardware 1183 * folks! 1184 */ 1185 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1186 pci_conf_write(pa->pa_pc, pa->pa_tag, 1187 DEVCONFIG1, devconfig1|PREQDIS); 1188 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1189 } 1190 1191 return (0); 1192 } 1193