1 /* $NetBSD: ahd_pci.c,v 1.33 2011/12/30 18:20:46 christos Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 49 * - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.33 2011/12/30 18:20:46 christos Exp $"); 54 55 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 56 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 57 58 #include <dev/ic/aic79xx_osm.h> 59 #include <dev/ic/aic79xx_inline.h> 60 61 static inline uint64_t 62 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 63 { 64 uint64_t id; 65 66 id = subvendor 67 | (subdevice << 16) 68 | ((uint64_t)vendor << 32) 69 | ((uint64_t)device << 48); 70 71 return (id); 72 } 73 74 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 75 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 76 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 77 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 78 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 79 80 #define ID_AIC7901 0x800F9005FFFF9005ull 81 #define ID_AHA_29320A 0x8000900500609005ull 82 #define ID_AHA_29320ALP 0x8017900500449005ull 83 #define ID_AHA_29320LPE 0x8017900500459005ull 84 85 #define ID_AIC7901A 0x801E9005FFFF9005ull 86 #define ID_AHA_29320LP 0x8014900500449005ull 87 88 #define ID_AIC7902 0x801F9005FFFF9005ull 89 #define ID_AIC7902_B 0x801D9005FFFF9005ull 90 #define ID_AHA_39320 0x8010900500409005ull 91 #define ID_AHA_29320 0x8012900500429005ull 92 #define ID_AHA_29320B 0x8013900500439005ull 93 #define ID_AHA_39320_B 0x8015900500409005ull 94 #define ID_AHA_39320A 0x8016900500409005ull 95 #define ID_AHA_39320D 0x8011900500419005ull 96 #define ID_AHA_39320D_B 0x801C900500419005ull 97 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 98 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 99 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 100 #define ID_AIC7902_PCI_REV_A4 0x3 101 #define ID_AIC7902_PCI_REV_B0 0x10 102 #define SUBID_HP 0x0E11 103 104 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 105 106 #define DEVID_9005_TYPE(id) ((id) & 0xF) 107 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 108 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 109 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 110 111 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 112 113 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 114 115 #define SUBID_9005_TYPE(id) ((id) & 0xF) 116 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 117 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 118 119 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 120 121 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 122 123 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 124 #define SUBID_9005_SEEPTYPE_NONE 0x0 125 #define SUBID_9005_SEEPTYPE_4K 0x1 126 127 static ahd_device_setup_t ahd_aic7901_setup; 128 static ahd_device_setup_t ahd_aic7901A_setup; 129 static ahd_device_setup_t ahd_aic7902_setup; 130 static ahd_device_setup_t ahd_aic790X_setup; 131 132 static struct ahd_pci_identity ahd_pci_ident_table [] = 133 { 134 /* aic7901 based controllers */ 135 { 136 ID_AHA_29320A, 137 ID_ALL_MASK, 138 "Adaptec 29320A Ultra320 SCSI adapter", 139 ahd_aic7901_setup 140 }, 141 { 142 ID_AHA_29320ALP, 143 ID_ALL_MASK, 144 "Adaptec 29320ALP Ultra320 SCSI adapter", 145 ahd_aic7901_setup 146 }, 147 { 148 ID_AHA_29320LPE, 149 ID_ALL_MASK, 150 "Adaptec 29320LPE Ultra320 SCSI adapter", 151 ahd_aic7901_setup 152 }, 153 /* aic7901A based controllers */ 154 { 155 ID_AHA_29320LP, 156 ID_ALL_MASK, 157 "Adaptec 29320LP Ultra320 SCSI adapter", 158 ahd_aic7901A_setup 159 }, 160 /* aic7902 based controllers */ 161 { 162 ID_AHA_39320, 163 ID_ALL_MASK, 164 "Adaptec 39320 Ultra320 SCSI adapter", 165 ahd_aic7902_setup 166 }, 167 { 168 ID_AHA_39320_B, 169 ID_ALL_MASK, 170 "Adaptec 39320 Ultra320 SCSI adapter", 171 ahd_aic7902_setup 172 }, 173 { 174 ID_AHA_39320_B_DELL, 175 ID_ALL_IROC_MASK, 176 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 177 ahd_aic7902_setup 178 }, 179 { 180 ID_AHA_39320A, 181 ID_ALL_MASK, 182 "Adaptec 39320A Ultra320 SCSI adapter", 183 ahd_aic7902_setup 184 }, 185 { 186 ID_AHA_39320D, 187 ID_ALL_MASK, 188 "Adaptec 39320D Ultra320 SCSI adapter", 189 ahd_aic7902_setup 190 }, 191 { 192 ID_AHA_39320D_HP, 193 ID_ALL_MASK, 194 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 195 ahd_aic7902_setup 196 }, 197 { 198 ID_AHA_39320D_B, 199 ID_ALL_MASK, 200 "Adaptec 39320D Ultra320 SCSI adapter", 201 ahd_aic7902_setup 202 }, 203 { 204 ID_AHA_39320D_B_HP, 205 ID_ALL_MASK, 206 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 207 ahd_aic7902_setup 208 }, 209 /* Generic chip probes for devices we don't know 'exactly' */ 210 { 211 ID_AIC7901 & ID_9005_GENERIC_MASK, 212 ID_9005_GENERIC_MASK, 213 "Adaptec AIC7901 Ultra320 SCSI adapter", 214 ahd_aic7901_setup 215 }, 216 { 217 ID_AIC7901A & ID_DEV_VENDOR_MASK, 218 ID_DEV_VENDOR_MASK, 219 "Adaptec AIC7901A Ultra320 SCSI adapter", 220 ahd_aic7901A_setup 221 }, 222 { 223 ID_AIC7902 & ID_9005_GENERIC_MASK, 224 ID_9005_GENERIC_MASK, 225 "Adaptec AIC7902 Ultra320 SCSI adapter", 226 ahd_aic7902_setup 227 } 228 }; 229 230 static const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 231 232 #define DEVCONFIG 0x40 233 #define PCIXINITPAT 0x0000E000ul 234 #define PCIXINIT_PCI33_66 0x0000E000ul 235 #define PCIXINIT_PCIX50_66 0x0000C000ul 236 #define PCIXINIT_PCIX66_100 0x0000A000ul 237 #define PCIXINIT_PCIX100_133 0x00008000ul 238 #define PCI_BUS_MODES_INDEX(devconfig) \ 239 (((devconfig) & PCIXINITPAT) >> 13) 240 241 static const char *pci_bus_modes[] = 242 { 243 "PCI bus mode unknown", 244 "PCI bus mode unknown", 245 "PCI bus mode unknown", 246 "PCI bus mode unknown", 247 "PCI-X 101-133 MHz", 248 "PCI-X 67-100 MHz", 249 "PCI-X 50-66 MHz", 250 "PCI 33 or 66 MHz" 251 }; 252 253 #define TESTMODE 0x00000800ul 254 #define IRDY_RST 0x00000200ul 255 #define FRAME_RST 0x00000100ul 256 #define PCI64BIT 0x00000080ul 257 #define MRDCEN 0x00000040ul 258 #define ENDIANSEL 0x00000020ul 259 #define MIXQWENDIANEN 0x00000008ul 260 #define DACEN 0x00000004ul 261 #define STPWLEVEL 0x00000002ul 262 #define QWENDIANSEL 0x00000001ul 263 264 #define DEVCONFIG1 0x44 265 #define PREQDIS 0x01 266 267 #define LATTIME 0x0000ff00ul 268 269 static int ahd_check_extport(struct ahd_softc *ahd); 270 static void ahd_configure_termination(struct ahd_softc *ahd, 271 u_int adapter_control); 272 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 273 274 static int ahd_pci_test_register_access(struct ahd_softc *); 275 276 static int ahd_pci_intr(struct ahd_softc *); 277 278 static const struct ahd_pci_identity * 279 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 280 { 281 u_int64_t full_id; 282 const struct ahd_pci_identity *entry; 283 u_int i; 284 285 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 286 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 287 288 for (i = 0; i < ahd_num_pci_devs; i++) { 289 entry = &ahd_pci_ident_table[i]; 290 if (entry->full_id == (full_id & entry->id_mask)) 291 return (entry); 292 } 293 return (NULL); 294 } 295 296 static int 297 ahd_pci_probe(device_t parent, cfdata_t match, void *aux) 298 { 299 struct pci_attach_args *pa = aux; 300 const struct ahd_pci_identity *entry; 301 pcireg_t subid; 302 303 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 304 entry = ahd_find_pci_device(pa->pa_id, subid); 305 return entry != NULL ? 1 : 0; 306 } 307 308 static void 309 ahd_pci_attach(device_t parent, device_t self, void *aux) 310 { 311 struct pci_attach_args *pa = aux; 312 struct ahd_softc *ahd = device_private(self); 313 314 const struct ahd_pci_identity *entry; 315 316 uint32_t devconfig; 317 pcireg_t command; 318 int error; 319 pcireg_t subid; 320 uint16_t subvendor; 321 pcireg_t reg; 322 int ioh_valid, ioh2_valid, memh_valid; 323 pcireg_t memtype; 324 pci_intr_handle_t ih; 325 const char *intrstr; 326 struct ahd_pci_busdata *bd; 327 328 ahd->sc_dev = self; 329 ahd_set_name(ahd, device_xname(self)); 330 ahd->parent_dmat = pa->pa_dmat; 331 332 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 333 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 334 entry = ahd_find_pci_device(pa->pa_id, subid); 335 if (entry == NULL) 336 return; 337 338 /* Keep information about the PCI bus */ 339 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 340 if (bd == NULL) { 341 aprint_error("%s: unable to allocate bus-specific data\n", 342 ahd_name(ahd)); 343 return; 344 } 345 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 346 347 bd->pc = pa->pa_pc; 348 bd->tag = pa->pa_tag; 349 bd->func = pa->pa_function; 350 bd->dev = pa->pa_device; 351 352 ahd->bus_data = bd; 353 354 ahd->description = entry->name; 355 356 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 357 M_DEVBUF, M_NOWAIT); 358 if (ahd->seep_config == NULL) { 359 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 360 return; 361 } 362 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 363 364 LIST_INIT(&ahd->pending_scbs); 365 ahd_timer_init(&ahd->reset_timer); 366 ahd_timer_init(&ahd->stat_timer); 367 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 368 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 369 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 370 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 371 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 372 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 373 ahd->int_coalescing_stop_threshold = 374 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 375 376 if (ahd_platform_alloc(ahd, NULL) != 0) { 377 ahd_free(ahd); 378 return; 379 } 380 381 /* 382 * Record if this is an HP board. 383 */ 384 subvendor = PCI_VENDOR(subid); 385 if (subvendor == SUBID_HP) 386 ahd->flags |= AHD_HP_BOARD; 387 388 error = entry->setup(ahd, pa); 389 if (error != 0) 390 return; 391 392 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 393 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 394 ahd->chip |= AHD_PCI; 395 /* Disable PCIX workarounds when running in PCI mode. */ 396 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 397 } else { 398 ahd->chip |= AHD_PCIX; 399 } 400 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 401 402 memh_valid = ioh_valid = ioh2_valid = 0; 403 404 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 405 &bd->pcix_off, NULL)) { 406 if (ahd->chip & AHD_PCIX) 407 aprint_error_dev(self, 408 "warning: can't find PCI-X capability\n"); 409 ahd->chip &= ~AHD_PCIX; 410 ahd->chip |= AHD_PCI; 411 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 412 } 413 414 /* 415 * Map PCI Registers 416 */ 417 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 418 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 419 AHD_PCI_MEMADDR); 420 switch (memtype) { 421 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 422 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 423 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 424 memtype, 0, &ahd->tags[0], 425 &ahd->bshs[0], 426 NULL, NULL) == 0); 427 if (memh_valid) { 428 ahd->tags[1] = ahd->tags[0]; 429 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 430 /*offset*/0x100, 431 /*size*/0x100, 432 &ahd->bshs[1]); 433 if (ahd_pci_test_register_access(ahd) != 0) 434 memh_valid = 0; 435 } 436 break; 437 default: 438 memh_valid = 0; 439 aprint_error("%s: unknown memory type: 0x%x\n", 440 ahd_name(ahd), memtype); 441 break; 442 } 443 444 if (memh_valid) { 445 command &= ~PCI_COMMAND_IO_ENABLE; 446 pci_conf_write(pa->pa_pc, pa->pa_tag, 447 PCI_COMMAND_STATUS_REG, command); 448 } 449 #ifdef AHD_DEBUG 450 printf("%s: doing memory mapping shs0 0x%lx, shs1 0x%lx\n", 451 ahd_name(ahd), ahd->bshs[0], ahd->bshs[1]); 452 #endif 453 } 454 455 if (command & PCI_COMMAND_IO_ENABLE) { 456 /* First BAR */ 457 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 458 PCI_MAPREG_TYPE_IO, 0, 459 &ahd->tags[0], &ahd->bshs[0], 460 NULL, NULL) == 0); 461 462 /* 2nd BAR */ 463 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 464 PCI_MAPREG_TYPE_IO, 0, 465 &ahd->tags[1], &ahd->bshs[1], 466 NULL, NULL) == 0); 467 468 if (ioh_valid && ioh2_valid) { 469 KASSERT(memh_valid == 0); 470 command &= ~PCI_COMMAND_MEM_ENABLE; 471 pci_conf_write(pa->pa_pc, pa->pa_tag, 472 PCI_COMMAND_STATUS_REG, command); 473 } 474 #ifdef AHD_DEBUG 475 printf("%s: doing io mapping shs0 0x%lx, shs1 0x%lx\n", 476 ahd_name(ahd), ahd->bshs[0], ahd->bshs[1]); 477 #endif 478 479 } 480 481 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 482 aprint_error("%s: unable to map registers\n", ahd_name(ahd)); 483 return; 484 } 485 486 aprint_normal("\n"); 487 aprint_naive("\n"); 488 489 /* power up chip */ 490 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 491 pci_activate_null)) && error != EOPNOTSUPP) { 492 aprint_error_dev(self, "cannot activate %d\n", error); 493 return; 494 } 495 /* 496 * Should we bother disabling 39Bit addressing 497 * based on installed memory? 498 */ 499 if (sizeof(bus_addr_t) > 4) 500 ahd->flags |= AHD_39BIT_ADDRESSING; 501 502 /* 503 * If we need to support high memory, enable dual 504 * address cycles. This bit must be set to enable 505 * high address bit generation even if we are on a 506 * 64bit bus (PCI64BIT set in devconfig). 507 */ 508 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 509 uint32_t dvconfig; 510 511 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 512 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 513 dvconfig |= DACEN; 514 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, dvconfig); 515 } 516 517 /* Ensure busmastering is enabled */ 518 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 519 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 520 reg | PCI_COMMAND_MASTER_ENABLE); 521 522 ahd_softc_init(ahd); 523 524 /* 525 * Map the interrupt routines 526 */ 527 ahd->bus_intr = ahd_pci_intr; 528 529 error = ahd_reset(ahd, /*reinit*/FALSE); 530 if (error != 0) { 531 ahd_free(ahd); 532 return; 533 } 534 535 if (pci_intr_map(pa, &ih)) { 536 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd)); 537 ahd_free(ahd); 538 return; 539 } 540 intrstr = pci_intr_string(pa->pa_pc, ih); 541 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 542 if (ahd->ih == NULL) { 543 aprint_error("%s: couldn't establish interrupt", 544 ahd_name(ahd)); 545 if (intrstr != NULL) 546 aprint_error(" at %s", intrstr); 547 aprint_error("\n"); 548 ahd_free(ahd); 549 return; 550 } 551 if (intrstr != NULL) 552 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd), 553 intrstr); 554 555 /* Get the size of the cache */ 556 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 557 ahd->pci_cachesize *= 4; 558 559 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 560 /* See if we have a SEEPROM and perform auto-term */ 561 error = ahd_check_extport(ahd); 562 if (error != 0) 563 return; 564 565 /* Core initialization */ 566 error = ahd_init(ahd); 567 if (error != 0) 568 return; 569 570 /* 571 * Link this softc in with all other ahd instances. 572 */ 573 ahd_attach(ahd); 574 } 575 576 CFATTACH_DECL_NEW(ahd_pci, sizeof(struct ahd_softc), 577 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 578 579 /* 580 * Perform some simple tests that should catch situations where 581 * our registers are invalidly mapped. 582 */ 583 static int 584 ahd_pci_test_register_access(struct ahd_softc *ahd) 585 { 586 uint32_t cmd; 587 struct ahd_pci_busdata *bd = ahd->bus_data; 588 u_int targpcistat; 589 uint32_t pci_status1; 590 int error; 591 uint8_t hcntrl; 592 593 error = EIO; 594 595 /* 596 * Enable PCI error interrupt status, but suppress NMIs 597 * generated by SERR raised due to target aborts. 598 */ 599 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 600 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 601 cmd & ~PCI_COMMAND_SERR_ENABLE); 602 603 /* 604 * First a simple test to see if any 605 * registers can be read. Reading 606 * HCNTRL has no side effects and has 607 * at least one bit that is guaranteed to 608 * be zero so it is a good register to 609 * use for this test. 610 */ 611 hcntrl = ahd_inb(ahd, HCNTRL); 612 if (hcntrl == 0xFF) 613 goto fail; 614 615 /* 616 * Next create a situation where write combining 617 * or read prefetching could be initiated by the 618 * CPU or host bridge. Our device does not support 619 * either, so look for data corruption and/or flaged 620 * PCI errors. First pause without causing another 621 * chip reset. 622 */ 623 hcntrl &= ~CHIPRST; 624 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 625 while (ahd_is_paused(ahd) == 0) 626 ; 627 628 /* Clear any PCI errors that occurred before our driver attached. */ 629 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 630 targpcistat = ahd_inb(ahd, TARGPCISTAT); 631 ahd_outb(ahd, TARGPCISTAT, targpcistat); 632 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 633 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 634 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 635 ahd_outb(ahd, CLRINT, CLRPCIINT); 636 637 ahd_outb(ahd, SEQCTL0, PERRORDIS); 638 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 639 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 640 goto fail; 641 642 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 643 u_int trgpcistat; 644 645 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 646 trgpcistat = ahd_inb(ahd, TARGPCISTAT); 647 if ((trgpcistat & STA) != 0) 648 goto fail; 649 } 650 651 error = 0; 652 653 fail: 654 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 655 656 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 657 targpcistat = ahd_inb(ahd, TARGPCISTAT); 658 659 /* Silently clear any latched errors. */ 660 ahd_outb(ahd, TARGPCISTAT, targpcistat); 661 pci_status1 = pci_conf_read(bd->pc, bd->tag, 662 PCI_COMMAND_STATUS_REG); 663 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 664 pci_status1); 665 ahd_outb(ahd, CLRINT, CLRPCIINT); 666 } 667 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 668 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 669 return (error); 670 } 671 672 /* 673 * Check the external port logic for a serial eeprom 674 * and termination/cable detection contrls. 675 */ 676 static int 677 ahd_check_extport(struct ahd_softc *ahd) 678 { 679 struct vpd_config vpd; 680 struct seeprom_config *sc; 681 u_int adapter_control; 682 int have_seeprom; 683 int error; 684 685 sc = ahd->seep_config; 686 have_seeprom = ahd_acquire_seeprom(ahd); 687 if (have_seeprom) { 688 u_int start_addr; 689 690 /* 691 * Fetch VPD for this function and parse it. 692 */ 693 #ifdef AHD_DEBUG 694 printf("%s: Reading VPD from SEEPROM...", 695 ahd_name(ahd)); 696 #endif 697 /* Address is always in units of 16bit words */ 698 start_addr = ((2 * sizeof(*sc)) 699 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 700 701 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 702 start_addr, sizeof(vpd)/2, 703 /*bytestream*/TRUE); 704 if (error == 0) 705 error = ahd_parse_vpddata(ahd, &vpd); 706 #ifdef AHD_DEBUG 707 printf("%s: VPD parsing %s\n", 708 ahd_name(ahd), 709 error == 0 ? "successful" : "failed"); 710 #endif 711 712 #ifdef AHD_DEBUG 713 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 714 #endif 715 716 /* Address is always in units of 16bit words */ 717 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 718 719 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 720 start_addr, sizeof(*sc)/2, 721 /*bytestream*/FALSE); 722 723 if (error != 0) { 724 #ifdef AHD_DEBUG 725 printf("Unable to read SEEPROM\n"); 726 #endif 727 have_seeprom = 0; 728 } else { 729 have_seeprom = ahd_verify_cksum(sc); 730 #ifdef AHD_DEBUG 731 if (have_seeprom == 0) 732 printf ("checksum error\n"); 733 else 734 printf ("done.\n"); 735 #endif 736 } 737 ahd_release_seeprom(ahd); 738 } 739 740 if (!have_seeprom) { 741 u_int nvram_scb; 742 743 /* 744 * Pull scratch ram settings and treat them as 745 * if they are the contents of an seeprom if 746 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 747 * in SCB 0xFF. We manually compose the data as 16bit 748 * values to avoid endian issues. 749 */ 750 ahd_set_scbptr(ahd, 0xFF); 751 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 752 if (nvram_scb != 0xFF 753 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 754 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 755 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 756 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 757 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 758 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 759 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 760 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 761 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 762 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 763 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 764 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 765 uint16_t *sc_data; 766 int i; 767 768 ahd_set_scbptr(ahd, nvram_scb); 769 sc_data = (uint16_t *)sc; 770 for (i = 0; i < 64; i += 2) 771 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 772 have_seeprom = ahd_verify_cksum(sc); 773 if (have_seeprom) 774 ahd->flags |= AHD_SCB_CONFIG_USED; 775 } 776 } 777 778 #ifdef AHD_DEBUG 779 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 780 uint16_t *sc_data; 781 int i; 782 783 printf("%s: Seeprom Contents:", ahd_name(ahd)); 784 sc_data = (uint16_t *)sc; 785 for (i = 0; i < (sizeof(*sc)); i += 2) 786 printf("\n\t0x%.4x", sc_data[i]); 787 printf("\n"); 788 } 789 #endif 790 791 if (!have_seeprom) { 792 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd)); 793 ahd->flags |= AHD_USEDEFAULTS; 794 error = ahd_default_config(ahd); 795 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 796 free(ahd->seep_config, M_DEVBUF); 797 ahd->seep_config = NULL; 798 } else { 799 error = ahd_parse_cfgdata(ahd, sc); 800 adapter_control = sc->adapter_control; 801 } 802 if (error != 0) 803 return (error); 804 805 ahd_configure_termination(ahd, adapter_control); 806 807 return (0); 808 } 809 810 static void 811 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 812 { 813 int error; 814 u_int sxfrctl1; 815 uint8_t termctl; 816 uint32_t devconfig; 817 struct ahd_pci_busdata *bd = ahd->bus_data; 818 819 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 820 devconfig &= ~STPWLEVEL; 821 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 822 devconfig |= STPWLEVEL; 823 #ifdef AHD_DEBUG 824 printf("%s: STPWLEVEL is %s\n", 825 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 826 #endif 827 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 828 829 /* Make sure current sensing is off. */ 830 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 831 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 832 } 833 834 /* 835 * Read to sense. Write to set. 836 */ 837 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 838 if ((adapter_control & CFAUTOTERM) == 0) { 839 if (bootverbose) 840 printf("%s: Manual Primary Termination\n", 841 ahd_name(ahd)); 842 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 843 if ((adapter_control & CFSTERM) != 0) 844 termctl |= FLX_TERMCTL_ENPRILOW; 845 if ((adapter_control & CFWSTERM) != 0) 846 termctl |= FLX_TERMCTL_ENPRIHIGH; 847 } else if (error != 0) { 848 if (bootverbose) 849 printf("%s: Primary Auto-Term Sensing failed! " 850 "Using Defaults.\n", ahd_name(ahd)); 851 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 852 } 853 854 if ((adapter_control & CFSEAUTOTERM) == 0) { 855 if (bootverbose) 856 printf("%s: Manual Secondary Termination\n", 857 ahd_name(ahd)); 858 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 859 if ((adapter_control & CFSELOWTERM) != 0) 860 termctl |= FLX_TERMCTL_ENSECLOW; 861 if ((adapter_control & CFSEHIGHTERM) != 0) 862 termctl |= FLX_TERMCTL_ENSECHIGH; 863 } else if (error != 0) { 864 if (bootverbose) 865 printf("%s: Secondary Auto-Term Sensing failed! " 866 "Using Defaults.\n", ahd_name(ahd)); 867 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 868 } 869 870 /* 871 * Now set the termination based on what we found. 872 */ 873 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 874 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 875 ahd->flags |= AHD_TERM_ENB_A; 876 sxfrctl1 |= STPWEN; 877 } 878 /* Must set the latch once in order to be effective. */ 879 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 880 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 881 882 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 883 if (error != 0) { 884 aprint_error("%s: Unable to set termination settings!\n", 885 ahd_name(ahd)); 886 } else { 887 if (bootverbose) { 888 printf("%s: Primary High byte termination %sabled\n", 889 ahd_name(ahd), 890 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 891 892 printf("%s: Primary Low byte termination %sabled\n", 893 ahd_name(ahd), 894 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 895 896 printf("%s: Secondary High byte termination %sabled\n", 897 ahd_name(ahd), 898 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 899 900 printf("%s: Secondary Low byte termination %sabled\n", 901 ahd_name(ahd), 902 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 903 } 904 } 905 return; 906 } 907 908 #define DPE 0x80 909 #define SSE 0x40 910 #define RMA 0x20 911 #define RTA 0x10 912 #define STA 0x08 913 #define DPR 0x01 914 915 static const char *split_status_source[] = 916 { 917 "DFF0", 918 "DFF1", 919 "OVLY", 920 "CMC", 921 }; 922 923 static const char *pci_status_source[] = 924 { 925 "DFF0", 926 "DFF1", 927 "SG", 928 "CMC", 929 "OVLY", 930 "NONE", 931 "MSI", 932 "TARG" 933 }; 934 935 static const char *split_status_strings[] = 936 { 937 "%s: Received split response in %s.\n", 938 "%s: Received split completion error message in %s\n", 939 "%s: Receive overrun in %s\n", 940 "%s: Count not complete in %s\n", 941 "%s: Split completion data bucket in %s\n", 942 "%s: Split completion address error in %s\n", 943 "%s: Split completion byte count error in %s\n", 944 "%s: Signaled Target-abort to early terminate a split in %s\n" 945 }; 946 947 static const char *pci_status_strings[] = 948 { 949 "%s: Data Parity Error has been reported via PERR# in %s\n", 950 "%s: Target initial wait state error in %s\n", 951 "%s: Split completion read data parity error in %s\n", 952 "%s: Split completion address attribute parity error in %s\n", 953 "%s: Received a Target Abort in %s\n", 954 "%s: Received a Master Abort in %s\n", 955 "%s: Signal System Error Detected in %s\n", 956 "%s: Address or Write Phase Parity Error Detected in %s.\n" 957 }; 958 959 static int 960 ahd_pci_intr(struct ahd_softc *ahd) 961 { 962 uint8_t pci_status[8]; 963 ahd_mode_state saved_modes; 964 u_int pci_status1; 965 u_int intstat; 966 u_int i; 967 u_int reg; 968 struct ahd_pci_busdata *bd = ahd->bus_data; 969 970 intstat = ahd_inb(ahd, INTSTAT); 971 972 if ((intstat & SPLTINT) != 0) 973 ahd_pci_split_intr(ahd, intstat); 974 975 if ((intstat & PCIINT) == 0) 976 return 0; 977 978 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 979 saved_modes = ahd_save_modes(ahd); 980 ahd_dump_card_state(ahd); 981 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 982 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 983 984 if (i == 5) 985 continue; 986 pci_status[i] = ahd_inb(ahd, reg); 987 /* Clear latched errors. So our interrupt deasserts. */ 988 ahd_outb(ahd, reg, pci_status[i]); 989 } 990 991 for (i = 0; i < 8; i++) { 992 u_int bit; 993 994 if (i == 5) 995 continue; 996 997 for (bit = 0; bit < 8; bit++) { 998 999 if ((pci_status[i] & (0x1 << bit)) != 0) { 1000 static const char *s; 1001 1002 s = pci_status_strings[bit]; 1003 if (i == 7/*TARG*/ && bit == 3) 1004 s = "%s: Signaled Target Abort\n"; 1005 printf(s, ahd_name(ahd), pci_status_source[i]); 1006 } 1007 } 1008 } 1009 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1010 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1011 1012 ahd_restore_modes(ahd, saved_modes); 1013 ahd_outb(ahd, CLRINT, CLRPCIINT); 1014 ahd_unpause(ahd); 1015 1016 return 1; 1017 } 1018 1019 static void 1020 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 1021 { 1022 uint8_t split_status[4]; 1023 uint8_t split_status1[4]; 1024 uint8_t sg_split_status[2]; 1025 uint8_t sg_split_status1[2]; 1026 ahd_mode_state saved_modes; 1027 u_int i; 1028 pcireg_t pcix_status; 1029 struct ahd_pci_busdata *bd = ahd->bus_data; 1030 1031 /* 1032 * Check for splits in all modes. Modes 0 and 1 1033 * additionally have SG engine splits to look at. 1034 */ 1035 pcix_status = pci_conf_read(bd->pc, bd->tag, 1036 bd->pcix_off + PCI_PCIX_STATUS); 1037 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1038 ahd_name(ahd), pcix_status); 1039 1040 saved_modes = ahd_save_modes(ahd); 1041 for (i = 0; i < 4; i++) { 1042 ahd_set_modes(ahd, i, i); 1043 1044 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1045 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1046 /* Clear latched errors. So our interrupt deasserts. */ 1047 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1048 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1049 if (i > 1) 1050 continue; 1051 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1052 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1053 /* Clear latched errors. So our interrupt deasserts. */ 1054 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1055 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1056 } 1057 1058 for (i = 0; i < 4; i++) { 1059 u_int bit; 1060 1061 for (bit = 0; bit < 8; bit++) { 1062 1063 if ((split_status[i] & (0x1 << bit)) != 0) { 1064 static const char *s; 1065 1066 s = split_status_strings[bit]; 1067 printf(s, ahd_name(ahd), 1068 split_status_source[i]); 1069 } 1070 1071 if (i > 0) 1072 continue; 1073 1074 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1075 static const char *s; 1076 1077 s = split_status_strings[bit]; 1078 printf(s, ahd_name(ahd), "SG"); 1079 } 1080 } 1081 } 1082 /* 1083 * Clear PCI-X status bits. 1084 */ 1085 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 1086 pcix_status); 1087 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1088 ahd_restore_modes(ahd, saved_modes); 1089 } 1090 1091 static int 1092 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1093 { 1094 1095 ahd->chip = AHD_AIC7901; 1096 ahd->features = AHD_AIC7901_FE; 1097 return (ahd_aic790X_setup(ahd, pa)); 1098 } 1099 1100 static int 1101 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1102 { 1103 1104 ahd->chip = AHD_AIC7901A; 1105 ahd->features = AHD_AIC7901A_FE; 1106 return (ahd_aic790X_setup(ahd, pa)); 1107 } 1108 1109 static int 1110 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1111 { 1112 1113 ahd->chip = AHD_AIC7902; 1114 ahd->features = AHD_AIC7902_FE; 1115 return (ahd_aic790X_setup(ahd, pa)); 1116 } 1117 1118 static int 1119 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1120 { 1121 u_int rev; 1122 1123 rev = PCI_REVISION(pa->pa_class); 1124 #ifdef AHD_DEBUG 1125 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1126 #endif 1127 if (rev < ID_AIC7902_PCI_REV_A4) { 1128 aprint_error("%s: Unable to attach to " 1129 "unsupported chip revision %d\n", ahd_name(ahd), rev); 1130 pci_conf_write(pa->pa_pc, pa->pa_tag, 1131 PCI_COMMAND_STATUS_REG, 0); 1132 return (ENXIO); 1133 } 1134 1135 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1136 if (rev < ID_AIC7902_PCI_REV_B0) { 1137 /* 1138 * Enable A series workarounds. 1139 */ 1140 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1141 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1142 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1143 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1144 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1145 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1146 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1147 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1148 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1149 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1150 | AHD_FAINT_LED_BUG; 1151 1152 1153 /* 1154 * IO Cell parameter setup. 1155 */ 1156 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1157 1158 if ((ahd->flags & AHD_HP_BOARD) == 0) 1159 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1160 } else { 1161 u_int devconfig1; 1162 1163 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1164 | AHD_NEW_DFCNTRL_OPTS; 1165 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1166 1167 /* 1168 * Some issues have been resolved in the 7901B. 1169 */ 1170 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1171 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1172 1173 /* 1174 * IO Cell parameter setup. 1175 */ 1176 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1177 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1178 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1179 1180 /* 1181 * Set the PREQDIS bit for H2B which disables some workaround 1182 * that doesn't work on regular PCI busses. 1183 * XXX - Find out exactly what this does from the hardware 1184 * folks! 1185 */ 1186 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1187 pci_conf_write(pa->pa_pc, pa->pa_tag, 1188 DEVCONFIG1, devconfig1|PREQDIS); 1189 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1190 } 1191 1192 return (0); 1193 } 1194