1 /* $NetBSD: aac_pci.c,v 1.39 2018/10/15 09:27:30 uwe Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * Copyright (c) 2000 Niklas Hallqvist 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 * 59 * from FreeBSD: aac_pci.c,v 1.1 2000/09/13 03:20:34 msmith Exp 60 * via OpenBSD: aac_pci.c,v 1.7 2002/03/14 01:26:58 millert Exp 61 */ 62 63 /* 64 * PCI front-end for the `aac' driver. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: aac_pci.c,v 1.39 2018/10/15 09:27:30 uwe Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/device.h> 73 #include <sys/kernel.h> 74 #include <sys/malloc.h> 75 #include <sys/queue.h> 76 77 #include <sys/bus.h> 78 #include <machine/endian.h> 79 #include <sys/intr.h> 80 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 85 #include <dev/ic/aacreg.h> 86 #include <dev/ic/aacvar.h> 87 88 struct aac_pci_softc { 89 struct aac_softc sc_aac; 90 pci_chipset_tag_t sc_pc; 91 pci_intr_handle_t sc_ih; 92 }; 93 94 /* i960Rx interface */ 95 static int aac_rx_get_fwstatus(struct aac_softc *); 96 static void aac_rx_qnotify(struct aac_softc *, int); 97 static int aac_rx_get_istatus(struct aac_softc *); 98 static void aac_rx_clear_istatus(struct aac_softc *, int); 99 static void aac_rx_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 100 u_int32_t, u_int32_t, u_int32_t); 101 static uint32_t aac_rx_get_mailbox(struct aac_softc *, int); 102 static void aac_rx_set_interrupts(struct aac_softc *, int); 103 static int aac_rx_send_command(struct aac_softc *, struct aac_ccb *); 104 static int aac_rx_get_outb_queue(struct aac_softc *); 105 static void aac_rx_set_outb_queue(struct aac_softc *, int); 106 107 /* StrongARM interface */ 108 static int aac_sa_get_fwstatus(struct aac_softc *); 109 static void aac_sa_qnotify(struct aac_softc *, int); 110 static int aac_sa_get_istatus(struct aac_softc *); 111 static void aac_sa_clear_istatus(struct aac_softc *, int); 112 static void aac_sa_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 113 u_int32_t, u_int32_t, u_int32_t); 114 static uint32_t aac_sa_get_mailbox(struct aac_softc *, int); 115 static void aac_sa_set_interrupts(struct aac_softc *, int); 116 117 /* Rocket/MIPS interface */ 118 static int aac_rkt_get_fwstatus(struct aac_softc *); 119 static void aac_rkt_qnotify(struct aac_softc *, int); 120 static int aac_rkt_get_istatus(struct aac_softc *); 121 static void aac_rkt_clear_istatus(struct aac_softc *, int); 122 static void aac_rkt_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 123 u_int32_t, u_int32_t, u_int32_t); 124 static uint32_t aac_rkt_get_mailbox(struct aac_softc *, int); 125 static void aac_rkt_set_interrupts(struct aac_softc *, int); 126 static int aac_rkt_send_command(struct aac_softc *, struct aac_ccb *); 127 static int aac_rkt_get_outb_queue(struct aac_softc *); 128 static void aac_rkt_set_outb_queue(struct aac_softc *, int); 129 130 static const struct aac_interface aac_rx_interface = { 131 aac_rx_get_fwstatus, 132 aac_rx_qnotify, 133 aac_rx_get_istatus, 134 aac_rx_clear_istatus, 135 aac_rx_set_mailbox, 136 aac_rx_get_mailbox, 137 aac_rx_set_interrupts, 138 aac_rx_send_command, 139 aac_rx_get_outb_queue, 140 aac_rx_set_outb_queue 141 }; 142 143 static const struct aac_interface aac_sa_interface = { 144 aac_sa_get_fwstatus, 145 aac_sa_qnotify, 146 aac_sa_get_istatus, 147 aac_sa_clear_istatus, 148 aac_sa_set_mailbox, 149 aac_sa_get_mailbox, 150 aac_sa_set_interrupts, 151 NULL, NULL, NULL 152 }; 153 154 static const struct aac_interface aac_rkt_interface = { 155 aac_rkt_get_fwstatus, 156 aac_rkt_qnotify, 157 aac_rkt_get_istatus, 158 aac_rkt_clear_istatus, 159 aac_rkt_set_mailbox, 160 aac_rkt_get_mailbox, 161 aac_rkt_set_interrupts, 162 aac_rkt_send_command, 163 aac_rkt_get_outb_queue, 164 aac_rkt_set_outb_queue 165 }; 166 167 static struct aac_ident { 168 u_short vendor; 169 u_short device; 170 u_short subvendor; 171 u_short subdevice; 172 u_short hwif; 173 u_short quirks; 174 const char *prodstr; 175 } const aac_ident[] = { 176 { 177 PCI_VENDOR_DELL, 178 PCI_PRODUCT_DELL_PERC_2SI, 179 PCI_VENDOR_DELL, 180 PCI_PRODUCT_DELL_PERC_2SI, 181 AAC_HWIF_I960RX, 182 0, 183 "Dell PERC 2/Si" 184 }, 185 { 186 PCI_VENDOR_DELL, 187 PCI_PRODUCT_DELL_PERC_3DI, 188 PCI_VENDOR_DELL, 189 PCI_PRODUCT_DELL_PERC_3DI, 190 AAC_HWIF_I960RX, 191 0, 192 "Dell PERC 3/Di" 193 }, 194 { 195 PCI_VENDOR_DELL, 196 PCI_PRODUCT_DELL_PERC_3DI, 197 PCI_VENDOR_DELL, 198 PCI_PRODUCT_DELL_PERC_3DI_SUB2, 199 AAC_HWIF_I960RX, 200 0, 201 "Dell PERC 3/Di" 202 }, 203 { 204 PCI_VENDOR_DELL, 205 PCI_PRODUCT_DELL_PERC_3DI, 206 PCI_VENDOR_DELL, 207 PCI_PRODUCT_DELL_PERC_3DI_SUB3, 208 AAC_HWIF_I960RX, 209 0, 210 "Dell PERC 3/Di" 211 }, 212 { 213 PCI_VENDOR_DELL, 214 PCI_PRODUCT_DELL_PERC_3DI_2, 215 PCI_VENDOR_DELL, 216 PCI_PRODUCT_DELL_PERC_3DI_2_SUB, 217 AAC_HWIF_I960RX, 218 0, 219 "Dell PERC 3/Di" 220 }, 221 { 222 PCI_VENDOR_DELL, 223 PCI_PRODUCT_DELL_PERC_3DI_3, 224 PCI_VENDOR_DELL, 225 PCI_PRODUCT_DELL_PERC_3DI_3_SUB, 226 AAC_HWIF_I960RX, 227 0, 228 "Dell PERC 3/Di" 229 }, 230 { 231 PCI_VENDOR_DELL, 232 PCI_PRODUCT_DELL_PERC_3DI_3, 233 PCI_VENDOR_DELL, 234 PCI_PRODUCT_DELL_PERC_3DI_3_SUB2, 235 AAC_HWIF_I960RX, 236 0, 237 "Dell PERC 3/Di" 238 }, 239 { 240 PCI_VENDOR_DELL, 241 PCI_PRODUCT_DELL_PERC_3DI_3, 242 PCI_VENDOR_DELL, 243 PCI_PRODUCT_DELL_PERC_3DI_3_SUB3, 244 AAC_HWIF_I960RX, 245 0, 246 "Dell PERC 3/Di" 247 }, 248 { 249 PCI_VENDOR_DELL, 250 PCI_PRODUCT_DELL_PERC_3SI, 251 PCI_VENDOR_DELL, 252 PCI_PRODUCT_DELL_PERC_3SI, 253 AAC_HWIF_I960RX, 254 0, 255 "Dell PERC 3/Si" 256 }, 257 { 258 PCI_VENDOR_DELL, 259 PCI_PRODUCT_DELL_PERC_3SI_2, 260 PCI_VENDOR_DELL, 261 PCI_PRODUCT_DELL_PERC_3SI_2_SUB, 262 AAC_HWIF_I960RX, 263 0, 264 "Dell PERC 3/Si" 265 }, 266 { 267 PCI_VENDOR_ADP2, 268 PCI_PRODUCT_ADP2_ASR2200S, 269 PCI_VENDOR_DELL, 270 PCI_PRODUCT_DELL_CERC_1_5, 271 AAC_HWIF_I960RX, 272 AAC_QUIRK_NO4GB, 273 "Dell CERC SATA RAID 1.5/6ch" 274 }, 275 { 276 PCI_VENDOR_ADP2, 277 PCI_PRODUCT_ADP2_AAC2622, 278 PCI_VENDOR_ADP2, 279 PCI_PRODUCT_ADP2_AAC2622, 280 AAC_HWIF_I960RX, 281 0, 282 "Adaptec ADP-2622" 283 }, 284 { 285 PCI_VENDOR_ADP2, 286 PCI_PRODUCT_ADP2_ASR2200S, 287 PCI_VENDOR_ADP2, 288 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 289 AAC_HWIF_I960RX, 290 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 291 "Adaptec ASR-2200S" 292 }, 293 { 294 PCI_VENDOR_ADP2, 295 PCI_PRODUCT_ADP2_ASR2200S, 296 PCI_VENDOR_DELL, 297 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 298 AAC_HWIF_I960RX, 299 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 300 "Dell PERC 320/DC" 301 }, 302 { 303 PCI_VENDOR_ADP2, 304 PCI_PRODUCT_ADP2_ASR2200S, 305 PCI_VENDOR_ADP2, 306 PCI_PRODUCT_ADP2_ASR2200S, 307 AAC_HWIF_I960RX, 308 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 309 "Adaptec ASR-2200S" 310 }, 311 { 312 PCI_VENDOR_ADP2, 313 PCI_PRODUCT_ADP2_ASR2200S, 314 PCI_VENDOR_ADP2, 315 PCI_PRODUCT_ADP2_AAR2810SA, 316 AAC_HWIF_I960RX, 317 AAC_QUIRK_NO4GB, 318 "Adaptec AAR-2810SA" 319 }, 320 { 321 PCI_VENDOR_ADP2, 322 PCI_PRODUCT_ADP2_ASR2200S, 323 PCI_VENDOR_ADP2, 324 PCI_PRODUCT_ADP2_ASR2120S, 325 AAC_HWIF_I960RX, 326 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 327 "Adaptec ASR-2120S" 328 }, 329 { 330 PCI_VENDOR_ADP2, 331 PCI_PRODUCT_ADP2_ASR2200S, 332 PCI_VENDOR_ADP2, 333 PCI_PRODUCT_ADP2_ASR2410SA, 334 AAC_HWIF_I960RX, 335 AAC_QUIRK_NO4GB, 336 "Adaptec ASR-2410SA" 337 }, 338 { 339 PCI_VENDOR_ADP2, 340 PCI_PRODUCT_ADP2_ASR2200S, 341 PCI_VENDOR_HP, 342 PCI_PRODUCT_ADP2_HP_M110_G2, 343 AAC_HWIF_I960RX, 344 AAC_QUIRK_NO4GB, 345 "HP ML110 G2 (Adaptec ASR-2610SA)" 346 }, 347 { 348 PCI_VENDOR_ADP2, 349 PCI_PRODUCT_ADP2_ASR2120S, 350 PCI_VENDOR_IBM, 351 PCI_PRODUCT_IBM_SERVERAID8K, 352 AAC_HWIF_RKT, 353 0, 354 "IBM ServeRAID 8k" 355 }, 356 { PCI_VENDOR_ADP2, 357 PCI_PRODUCT_ADP2_ASR2200S, 358 PCI_VENDOR_ADP2, 359 PCI_PRODUCT_ADP2_2405, 360 AAC_HWIF_I960RX, 361 0, 362 "Adaptec RAID 2405" 363 }, 364 { PCI_VENDOR_ADP2, 365 PCI_PRODUCT_ADP2_ASR2200S, 366 PCI_VENDOR_ADP2, 367 PCI_PRODUCT_ADP2_2445, 368 AAC_HWIF_I960RX, 369 0, 370 "Adaptec RAID 2445" 371 }, 372 { PCI_VENDOR_ADP2, 373 PCI_PRODUCT_ADP2_ASR2200S, 374 PCI_VENDOR_ADP2, 375 PCI_PRODUCT_ADP2_2805, 376 AAC_HWIF_I960RX, 377 0, 378 "Adaptec RAID 2805" 379 }, 380 { PCI_VENDOR_ADP2, 381 PCI_PRODUCT_ADP2_ASR2200S, 382 PCI_VENDOR_ADP2, 383 PCI_PRODUCT_ADP2_3405, 384 AAC_HWIF_I960RX, 385 0, 386 "Adaptec RAID 3405" 387 }, 388 { PCI_VENDOR_ADP2, 389 PCI_PRODUCT_ADP2_ASR2200S, 390 PCI_VENDOR_ADP2, 391 PCI_PRODUCT_ADP2_3805, 392 AAC_HWIF_I960RX, 393 0, 394 "Adaptec RAID 3805" 395 }, 396 { 397 PCI_VENDOR_DEC, 398 PCI_PRODUCT_DEC_21554, 399 PCI_VENDOR_ADP2, 400 PCI_PRODUCT_ADP2_AAC364, 401 AAC_HWIF_STRONGARM, 402 0, 403 "Adaptec AAC-364" 404 }, 405 { 406 PCI_VENDOR_DEC, 407 PCI_PRODUCT_DEC_21554, 408 PCI_VENDOR_ADP2, 409 PCI_PRODUCT_ADP2_ASR5400S, 410 AAC_HWIF_STRONGARM, 411 AAC_QUIRK_BROKEN_MMAP, 412 "Adaptec ASR-5400S" 413 }, 414 { 415 PCI_VENDOR_DEC, 416 PCI_PRODUCT_DEC_21554, 417 PCI_VENDOR_ADP2, 418 PCI_PRODUCT_ADP2_PERC_2QC, 419 AAC_HWIF_STRONGARM, 420 AAC_QUIRK_PERC2QC, 421 "Dell PERC 2/QC" 422 }, 423 { 424 PCI_VENDOR_DEC, 425 PCI_PRODUCT_DEC_21554, 426 PCI_VENDOR_ADP2, 427 PCI_PRODUCT_ADP2_PERC_3QC, 428 AAC_HWIF_STRONGARM, 429 0, 430 "Dell PERC 3/QC" 431 }, 432 { 433 PCI_VENDOR_DEC, 434 PCI_PRODUCT_DEC_21554, 435 PCI_VENDOR_HP, 436 PCI_PRODUCT_HP_NETRAID_4M, 437 AAC_HWIF_STRONGARM, 438 0, 439 "HP NetRAID-4M" 440 }, 441 { 442 PCI_VENDOR_ADP2, 443 PCI_PRODUCT_ADP2_ASR2200S, 444 PCI_VENDOR_SUN, 445 PCI_PRODUCT_ADP2_ASR2120S, 446 AAC_HWIF_I960RX, 447 0, 448 "SG-XPCIESAS-R-IN" 449 }, 450 }; 451 452 static const struct aac_ident * 453 aac_find_ident(struct pci_attach_args *pa) 454 { 455 const struct aac_ident *m, *mm; 456 u_int32_t subsysid; 457 458 m = aac_ident; 459 mm = aac_ident + (sizeof(aac_ident) / sizeof(aac_ident[0])); 460 461 while (m < mm) { 462 if (m->vendor == PCI_VENDOR(pa->pa_id) && 463 m->device == PCI_PRODUCT(pa->pa_id)) { 464 subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, 465 PCI_SUBSYS_ID_REG); 466 if (m->subvendor == PCI_VENDOR(subsysid) && 467 m->subdevice == PCI_PRODUCT(subsysid)) 468 return (m); 469 } 470 m++; 471 } 472 473 return (NULL); 474 } 475 476 static int 477 aac_pci_intr_set(struct aac_softc *sc, int (*hand)(void*), void *arg) 478 { 479 struct aac_pci_softc *pcisc; 480 481 pcisc = (struct aac_pci_softc *) sc; 482 483 pci_intr_disestablish(pcisc->sc_pc, sc->sc_ih); 484 sc->sc_ih = pci_intr_establish(pcisc->sc_pc, pcisc->sc_ih, 485 IPL_BIO, hand, arg); 486 if (sc->sc_ih == NULL) { 487 return ENXIO; 488 } 489 return 0; 490 } 491 492 static int 493 aac_pci_match(device_t parent, cfdata_t match, void *aux) 494 { 495 struct pci_attach_args *pa; 496 497 pa = aux; 498 499 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 500 return (0); 501 502 return (aac_find_ident(pa) != NULL); 503 } 504 505 static void 506 aac_pci_attach(device_t parent, device_t self, void *aux) 507 { 508 struct pci_attach_args *pa; 509 pci_chipset_tag_t pc; 510 struct aac_pci_softc *pcisc; 511 struct aac_softc *sc; 512 u_int16_t command; 513 bus_addr_t membase; 514 bus_size_t memsize; 515 const char *intrstr; 516 int state; 517 const struct aac_ident *m; 518 char intrbuf[PCI_INTRSTR_LEN]; 519 520 pa = aux; 521 pc = pa->pa_pc; 522 pcisc = device_private(self); 523 pcisc->sc_pc = pc; 524 sc = &pcisc->sc_aac; 525 sc->sc_dv = self; 526 state = 0; 527 528 aprint_naive(": RAID controller\n"); 529 aprint_normal(": "); 530 531 /* 532 * Verify that the adapter is correctly set up in PCI space. 533 */ 534 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 535 command |= PCI_COMMAND_MASTER_ENABLE; 536 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 537 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 538 AAC_DPRINTF(AAC_D_MISC, ("pci command status reg 0x08x ")); 539 540 if ((command & PCI_COMMAND_MASTER_ENABLE) == 0) { 541 aprint_error("can't enable bus-master feature\n"); 542 goto bail_out; 543 } 544 545 if ((command & PCI_COMMAND_MEM_ENABLE) == 0) { 546 aprint_error("memory window not available\n"); 547 goto bail_out; 548 } 549 550 /* 551 * Map control/status registers. 552 */ 553 if (pci_mapreg_map(pa, PCI_MAPREG_START, 554 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_memt, 555 &sc->sc_memh, &membase, &memsize)) { 556 aprint_error("can't find mem space\n"); 557 goto bail_out; 558 } 559 state++; 560 561 if (pci_intr_map(pa, &pcisc->sc_ih)) { 562 aprint_error("couldn't map interrupt\n"); 563 goto bail_out; 564 } 565 intrstr = pci_intr_string(pc, pcisc->sc_ih, intrbuf, sizeof(intrbuf)); 566 sc->sc_ih = pci_intr_establish(pc, pcisc->sc_ih, IPL_BIO, aac_intr, sc); 567 if (sc->sc_ih == NULL) { 568 aprint_error("couldn't establish interrupt"); 569 if (intrstr != NULL) 570 aprint_error(" at %s", intrstr); 571 aprint_error("\n"); 572 goto bail_out; 573 } 574 state++; 575 576 sc->sc_dmat = pa->pa_dmat; 577 578 m = aac_find_ident(pa); 579 aprint_normal("%s\n", m->prodstr); 580 if (intrstr != NULL) 581 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 582 583 sc->sc_hwif = m->hwif; 584 sc->sc_quirks = m->quirks; 585 switch (sc->sc_hwif) { 586 case AAC_HWIF_I960RX: 587 AAC_DPRINTF(AAC_D_MISC, 588 ("set hardware up for i960Rx")); 589 sc->sc_if = aac_rx_interface; 590 break; 591 592 case AAC_HWIF_STRONGARM: 593 AAC_DPRINTF(AAC_D_MISC, 594 ("set hardware up for StrongARM")); 595 sc->sc_if = aac_sa_interface; 596 break; 597 598 case AAC_HWIF_RKT: 599 AAC_DPRINTF(AAC_D_MISC, 600 ("set hardware up for MIPS/Rocket")); 601 sc->sc_if = aac_rkt_interface; 602 break; 603 } 604 sc->sc_regsize = memsize; 605 sc->sc_intr_set = aac_pci_intr_set; 606 607 if (!aac_attach(sc)) 608 return; 609 610 bail_out: 611 if (state > 1) 612 pci_intr_disestablish(pc, sc->sc_ih); 613 if (state > 0) 614 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 615 } 616 617 /* ARGSUSED */ 618 static int 619 aac_pci_rescan(device_t self, const char *attr, const int *flags) 620 { 621 622 return aac_devscan(device_private(self)); 623 } 624 625 CFATTACH_DECL3_NEW(aac_pci, sizeof(struct aac_pci_softc), 626 aac_pci_match, aac_pci_attach, NULL, NULL, aac_pci_rescan, NULL, 0); 627 628 /* 629 * Read the current firmware status word. 630 */ 631 static int 632 aac_sa_get_fwstatus(struct aac_softc *sc) 633 { 634 635 return (AAC_GETREG4(sc, AAC_SA_FWSTATUS)); 636 } 637 638 static int 639 aac_rx_get_fwstatus(struct aac_softc *sc) 640 { 641 642 return (AAC_GETREG4(sc, AAC_RX_FWSTATUS)); 643 } 644 645 static int 646 aac_rkt_get_fwstatus(struct aac_softc *sc) 647 { 648 649 return (AAC_GETREG4(sc, AAC_RKT_FWSTATUS)); 650 } 651 652 /* 653 * Notify the controller of a change in a given queue 654 */ 655 656 static void 657 aac_sa_qnotify(struct aac_softc *sc, int qbit) 658 { 659 660 AAC_SETREG2(sc, AAC_SA_DOORBELL1_SET, qbit); 661 } 662 663 static void 664 aac_rx_qnotify(struct aac_softc *sc, int qbit) 665 { 666 667 AAC_SETREG4(sc, AAC_RX_IDBR, qbit); 668 } 669 670 static void 671 aac_rkt_qnotify(struct aac_softc *sc, int qbit) 672 { 673 674 AAC_SETREG4(sc, AAC_RKT_IDBR, qbit); 675 } 676 677 /* 678 * Get the interrupt reason bits 679 */ 680 static int 681 aac_sa_get_istatus(struct aac_softc *sc) 682 { 683 684 return (AAC_GETREG2(sc, AAC_SA_DOORBELL0)); 685 } 686 687 static int 688 aac_rx_get_istatus(struct aac_softc *sc) 689 { 690 691 return (AAC_GETREG4(sc, AAC_RX_ODBR)); 692 } 693 694 static int 695 aac_rkt_get_istatus(struct aac_softc *sc) 696 { 697 698 return (AAC_GETREG4(sc, AAC_RKT_ODBR)); 699 } 700 701 /* 702 * Clear some interrupt reason bits 703 */ 704 static void 705 aac_sa_clear_istatus(struct aac_softc *sc, int mask) 706 { 707 708 AAC_SETREG2(sc, AAC_SA_DOORBELL0_CLEAR, mask); 709 } 710 711 static void 712 aac_rx_clear_istatus(struct aac_softc *sc, int mask) 713 { 714 715 AAC_SETREG4(sc, AAC_RX_ODBR, mask); 716 } 717 718 static void 719 aac_rkt_clear_istatus(struct aac_softc *sc, int mask) 720 { 721 722 AAC_SETREG4(sc, AAC_RKT_ODBR, mask); 723 } 724 725 /* 726 * Populate the mailbox and set the command word 727 */ 728 static void 729 aac_sa_set_mailbox(struct aac_softc *sc, u_int32_t command, 730 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 731 u_int32_t arg3) 732 { 733 734 AAC_SETREG4(sc, AAC_SA_MAILBOX, command); 735 AAC_SETREG4(sc, AAC_SA_MAILBOX + 4, arg0); 736 AAC_SETREG4(sc, AAC_SA_MAILBOX + 8, arg1); 737 AAC_SETREG4(sc, AAC_SA_MAILBOX + 12, arg2); 738 AAC_SETREG4(sc, AAC_SA_MAILBOX + 16, arg3); 739 } 740 741 static void 742 aac_rx_set_mailbox(struct aac_softc *sc, u_int32_t command, 743 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 744 u_int32_t arg3) 745 { 746 747 AAC_SETREG4(sc, AAC_RX_MAILBOX, command); 748 AAC_SETREG4(sc, AAC_RX_MAILBOX + 4, arg0); 749 AAC_SETREG4(sc, AAC_RX_MAILBOX + 8, arg1); 750 AAC_SETREG4(sc, AAC_RX_MAILBOX + 12, arg2); 751 AAC_SETREG4(sc, AAC_RX_MAILBOX + 16, arg3); 752 } 753 754 static void 755 aac_rkt_set_mailbox(struct aac_softc *sc, u_int32_t command, 756 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 757 u_int32_t arg3) 758 { 759 760 AAC_SETREG4(sc, AAC_RKT_MAILBOX, command); 761 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 4, arg0); 762 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 8, arg1); 763 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 12, arg2); 764 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 16, arg3); 765 } 766 767 /* 768 * Fetch the specified mailbox 769 */ 770 static uint32_t 771 aac_sa_get_mailbox(struct aac_softc *sc, int mb) 772 { 773 774 return (AAC_GETREG4(sc, AAC_SA_MAILBOX + (mb * 4))); 775 } 776 777 static uint32_t 778 aac_rx_get_mailbox(struct aac_softc *sc, int mb) 779 { 780 781 return (AAC_GETREG4(sc, AAC_RX_MAILBOX + (mb * 4))); 782 } 783 784 static uint32_t 785 aac_rkt_get_mailbox(struct aac_softc *sc, int mb) 786 { 787 788 return (AAC_GETREG4(sc, AAC_RKT_MAILBOX + (mb * 4))); 789 } 790 791 /* 792 * Set/clear interrupt masks 793 */ 794 static void 795 aac_sa_set_interrupts(struct aac_softc *sc, int enable) 796 { 797 798 if (enable) 799 AAC_SETREG2((sc), AAC_SA_MASK0_CLEAR, AAC_DB_INTERRUPTS); 800 else 801 AAC_SETREG2((sc), AAC_SA_MASK0_SET, ~0); 802 } 803 804 static void 805 aac_rx_set_interrupts(struct aac_softc *sc, int enable) 806 { 807 808 if (enable) { 809 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 810 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INT_NEW_COMM); 811 else 812 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INTERRUPTS); 813 } else { 814 AAC_SETREG4(sc, AAC_RX_OIMR, ~0); 815 } 816 } 817 818 static void 819 aac_rkt_set_interrupts(struct aac_softc *sc, int enable) 820 { 821 822 if (enable) { 823 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 824 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INT_NEW_COMM); 825 else 826 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INTERRUPTS); 827 } else { 828 AAC_SETREG4(sc, AAC_RKT_OIMR, ~0); 829 } 830 } 831 832 /* 833 * New comm. interface: Send command functions 834 */ 835 static int 836 aac_rx_send_command(struct aac_softc *sc, struct aac_ccb *ac) 837 { 838 u_int32_t index, device; 839 840 index = AAC_GETREG4(sc, AAC_RX_IQUE); 841 if (index == 0xffffffffL) 842 index = AAC_GETREG4(sc, AAC_RX_IQUE); 843 if (index == 0xffffffffL) 844 return index; 845 #ifdef notyet 846 aac_enqueue_busy(ac); 847 #endif 848 device = index; 849 AAC_SETREG4(sc, device, 850 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 851 device += 4; 852 if (sizeof(bus_addr_t) > 4) { 853 AAC_SETREG4(sc, device, 854 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 855 } else { 856 AAC_SETREG4(sc, device, 0); 857 } 858 device += 4; 859 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 860 AAC_SETREG4(sc, AAC_RX_IQUE, index); 861 return 0; 862 } 863 864 static int 865 aac_rkt_send_command(struct aac_softc *sc, struct aac_ccb *ac) 866 { 867 u_int32_t index, device; 868 869 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 870 if (index == 0xffffffffL) 871 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 872 if (index == 0xffffffffL) 873 return index; 874 #ifdef notyet 875 aac_enqueue_busy(ac); 876 #endif 877 device = index; 878 AAC_SETREG4(sc, device, 879 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 880 device += 4; 881 if (sizeof(bus_addr_t) > 4) { 882 AAC_SETREG4(sc, device, 883 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 884 } else { 885 AAC_SETREG4(sc, device, 0); 886 } 887 device += 4; 888 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 889 AAC_SETREG4(sc, AAC_RKT_IQUE, index); 890 return 0; 891 } 892 893 /* 894 * New comm. interface: get, set outbound queue index 895 */ 896 static int 897 aac_rx_get_outb_queue(struct aac_softc *sc) 898 { 899 900 return AAC_GETREG4(sc, AAC_RX_OQUE); 901 } 902 903 static int 904 aac_rkt_get_outb_queue(struct aac_softc *sc) 905 { 906 907 return AAC_GETREG4(sc, AAC_RKT_OQUE); 908 } 909 910 static void 911 aac_rx_set_outb_queue(struct aac_softc *sc, int index) 912 { 913 914 AAC_SETREG4(sc, AAC_RX_OQUE, index); 915 } 916 917 static void 918 aac_rkt_set_outb_queue(struct aac_softc *sc, int index) 919 { 920 921 AAC_SETREG4(sc, AAC_RKT_OQUE, index); 922 } 923