11ed09d9cSrkujawa /******************************************************************************* 21ed09d9cSrkujawa Copyright (C) Marvell International Ltd. and its affiliates 31ed09d9cSrkujawa 41ed09d9cSrkujawa Developed by Semihalf 51ed09d9cSrkujawa 61ed09d9cSrkujawa ******************************************************************************** 71ed09d9cSrkujawa Marvell BSD License 81ed09d9cSrkujawa 91ed09d9cSrkujawa If you received this File from Marvell, you may opt to use, redistribute and/or 101ed09d9cSrkujawa modify this File under the following licensing terms. 111ed09d9cSrkujawa Redistribution and use in source and binary forms, with or without modification, 121ed09d9cSrkujawa are permitted provided that the following conditions are met: 131ed09d9cSrkujawa 141ed09d9cSrkujawa * Redistributions of source code must retain the above copyright notice, 151ed09d9cSrkujawa this list of conditions and the following disclaimer. 161ed09d9cSrkujawa 171ed09d9cSrkujawa * Redistributions in binary form must reproduce the above copyright 181ed09d9cSrkujawa notice, this list of conditions and the following disclaimer in the 191ed09d9cSrkujawa documentation and/or other materials provided with the distribution. 201ed09d9cSrkujawa 211ed09d9cSrkujawa * Neither the name of Marvell nor the names of its contributors may be 221ed09d9cSrkujawa used to endorse or promote products derived from this software without 231ed09d9cSrkujawa specific prior written permission. 241ed09d9cSrkujawa 251ed09d9cSrkujawa THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 261ed09d9cSrkujawa ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 271ed09d9cSrkujawa WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 281ed09d9cSrkujawa DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 291ed09d9cSrkujawa ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 301ed09d9cSrkujawa (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 311ed09d9cSrkujawa LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 321ed09d9cSrkujawa ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 331ed09d9cSrkujawa (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 341ed09d9cSrkujawa SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 351ed09d9cSrkujawa 361ed09d9cSrkujawa *******************************************************************************/ 371ed09d9cSrkujawa 381ed09d9cSrkujawa #ifndef _MVSPIREG_H_ 391ed09d9cSrkujawa #define _MVSPIREG_H_ 401ed09d9cSrkujawa 41*89ea2da7Skiyohara #define MVSPI_SIZE 0x80 /* Size of MVSPI */ 421ed09d9cSrkujawa 431ed09d9cSrkujawa /* Definition of registers */ 441ed09d9cSrkujawa #define MVSPI_CTRL_REG 0x00 /* MVSPI Control Register */ 451ed09d9cSrkujawa #define MVSPI_INTCONF_REG 0x04 /* MVSPI Interface Configuration Register */ 461ed09d9cSrkujawa #define MVSPI_DATAOUT_REG 0x08 /* MVSPI Data Out Register */ 471ed09d9cSrkujawa #define MVSPI_DATAIN_REG 0x0C /* MVSPI Data In Register */ 481ed09d9cSrkujawa #define MVSPI_IRQCAUSE_REG 0x10 /* MVSPI Interrupt Cause Register */ 491ed09d9cSrkujawa #define MVSPI_IRQMASK_REG 0x14 /* MVSPI Interrupt Mask Register */ 501ed09d9cSrkujawa #define MVSPI_TIMEPAR1_REG 0x18 /* MVSPI Timing Parameters 1 Register*/ 511ed09d9cSrkujawa #define MVSPI_TIMEPAR2_REG 0x1C /* MVSPI Timing Parameters 2 Register */ 521ed09d9cSrkujawa #define MVSPI_DIRWRITE_REG 0x20 /* MVSPI Direct Write Configuration Register*/ 531ed09d9cSrkujawa #define MVSPI_DIRWRITEHD_REG 0x24 /* MVSPI Direct Write Header Register */ 541ed09d9cSrkujawa #define MVSPI_DIRREADHD_REG 0x28 /* MVSPI Direct Read Header Register */ 551ed09d9cSrkujawa #define MVSPI_CSADRDEC_REG 0x2C /* MVSPI CS Address Decode Register */ 561ed09d9cSrkujawa #define MVSPI_CSnTIMPAR_REG 0x30 /* MVSPI CSn Timing Parameters Register */ 571ed09d9cSrkujawa #define MVSPI_CNTVER_REG 0x50 /* MVSPI Controller Version Register */ 581ed09d9cSrkujawa 591ed09d9cSrkujawa /* Masks */ 601ed09d9cSrkujawa #define MVSPI_CPOL_MASK 0x0800 /* CPOL bit = 1 */ 611ed09d9cSrkujawa #define MVSPI_CPHA_MASK 0x1000 /* CPHA bit = 1 */ 621ed09d9cSrkujawa #define MVSPI_DIRHS_MASK 0xFBFF /* SPI Direct Read High Speed Transaction Mask */ 631ed09d9cSrkujawa #define MVSPI_1BYTE_MASK 0xFFDF /* Number of bits in each I/O transfer Mask */ 641ed09d9cSrkujawa #define MVSPI_SPR_MASK 0x0007 /* SPR field mask */ 651ed09d9cSrkujawa #define MVSPI_SPPR_MASK 0x00D0 /* SPPR field mask */ 661ed09d9cSrkujawa #define MVSPI_SPPRHI_MASK 0x00C0 /* SPPR_HI field mask */ 671ed09d9cSrkujawa #define MVSPI_SPPR0_MASK 0x0010 /* SPPR0 field mask */ 681ed09d9cSrkujawa #define MVSPI_CSNACT_MASK 0x0001 /* CSn transfer acknowledge bit */ 691ed09d9cSrkujawa 701ed09d9cSrkujawa #define MVSPI_CR_SMEMRDY 0x0002 /* MVSPI Control Register Serial Memory Data Transfer Ready */ 711ed09d9cSrkujawa 721ed09d9cSrkujawa #define MVSPI_DUMMY_BYTE 0xFF /* Dummy byte */ 731ed09d9cSrkujawa 741ed09d9cSrkujawa #define MVSPI_WAIT_RDY_MAX_LOOP 100000 /* Transfer timeout threshold */ 751ed09d9cSrkujawa #define MVSPI_SPR_MAXVALUE 15 /* Maximum value for SPR coeficient */ 761ed09d9cSrkujawa #define MVSPI_SPPR_MAXVALUE 7 /* Maximum value for SPPR coeficient */ 771ed09d9cSrkujawa 781ed09d9cSrkujawa #endif /* _MVSPIREG_H_ */ 79