1*077d1c0fSandvar /* $NetBSD: gtintrreg.h,v 1.6 2021/08/02 12:56:24 andvar Exp $ */ 2ff2281b4Smatt 3ff2281b4Smatt /* 4ff2281b4Smatt * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5ff2281b4Smatt * All rights reserved. 6ff2281b4Smatt * 7ff2281b4Smatt * Redistribution and use in source and binary forms, with or without 8ff2281b4Smatt * modification, are permitted provided that the following conditions 9ff2281b4Smatt * are met: 10ff2281b4Smatt * 1. Redistributions of source code must retain the above copyright 11ff2281b4Smatt * notice, this list of conditions and the following disclaimer. 12ff2281b4Smatt * 2. Redistributions in binary form must reproduce the above copyright 13ff2281b4Smatt * notice, this list of conditions and the following disclaimer in the 14ff2281b4Smatt * documentation and/or other materials provided with the distribution. 15ff2281b4Smatt * 3. All advertising materials mentioning features or use of this software 16ff2281b4Smatt * must display the following acknowledgement: 17ff2281b4Smatt * This product includes software developed for the NetBSD Project by 18ff2281b4Smatt * Allegro Networks, Inc., and Wasabi Systems, Inc. 19ff2281b4Smatt * 4. The name of Allegro Networks, Inc. may not be used to endorse 20ff2281b4Smatt * or promote products derived from this software without specific prior 21ff2281b4Smatt * written permission. 22ff2281b4Smatt * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23ff2281b4Smatt * or promote products derived from this software without specific prior 24ff2281b4Smatt * written permission. 25ff2281b4Smatt * 26ff2281b4Smatt * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27ff2281b4Smatt * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28ff2281b4Smatt * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29ff2281b4Smatt * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30ff2281b4Smatt * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31ff2281b4Smatt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32ff2281b4Smatt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33ff2281b4Smatt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34ff2281b4Smatt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35ff2281b4Smatt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36ff2281b4Smatt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37ff2281b4Smatt * POSSIBILITY OF SUCH DAMAGE. 38ff2281b4Smatt */ 39ff2281b4Smatt 40ff2281b4Smatt /* 41ff2281b4Smatt * gt64260intr.h: defines for GT-64260 system controller interrupts 42ff2281b4Smatt * 43ff2281b4Smatt * creation Sun Jan 7 18:05:59 PST 2001 cliff 44ff2281b4Smatt * 45ff2281b4Smatt * NOTE: 46ff2281b4Smatt * Galileo GT-64260 manual bit defines assume Little Endian 47ff2281b4Smatt * ordering of bits within bytes, i.e. 48ff2281b4Smatt * bit #0 --> 0x01 49ff2281b4Smatt * vs. Motorola Big Endian bit numbering where 50ff2281b4Smatt * bit #0 --> 0x80 51ff2281b4Smatt * Consequently we define bits in Little Endian format and plan 52ff2281b4Smatt * to swizzle bytes during programmed I/O by using lwbrx/swbrx 53ff2281b4Smatt * to load/store GT-64260 registers. 54ff2281b4Smatt */ 55ff2281b4Smatt 56ff2281b4Smatt 57ff2281b4Smatt #ifndef _DISCOVERY_GT64260INTR_H 58ff2281b4Smatt #define _DISCOVERY_GT64260INTR_H 59ff2281b4Smatt 60ff2281b4Smatt 61ff2281b4Smatt /* 62ff2281b4Smatt * GT-64260 Interrupt Controller Register Map 63ff2281b4Smatt */ 64ff2281b4Smatt #define ICR_MIC_LO 0xc18 /* main interrupt cause low */ 65ff2281b4Smatt #define ICR_MIC_HI 0xc68 /* main interrupt cause high */ 66d20841bbSwiz #define ICR_CIM_LO 0xc1c /* CPU interrupt mask low */ 67d20841bbSwiz #define ICR_CIM_HI 0xc6c /* CPU interrupt mask high */ 68d20841bbSwiz #define ICR_CSC 0xc70 /* CPU select cause */ 69ff2281b4Smatt #define ICR_P0IM_LO 0xc24 /* PCI_0 interrupt mask low */ 70ff2281b4Smatt #define ICR_P0IM_HI 0xc64 /* PCI_0 interrupt mask high */ 71ff2281b4Smatt #define ICR_P0SC 0xc74 /* PCI_0 select cause */ 72ff2281b4Smatt #define ICR_P1IM_LO 0xca4 /* PCI_1 interrupt mask low */ 73ff2281b4Smatt #define ICR_P1IM_HI 0xce4 /* PCI_1 interrupt mask high */ 74ff2281b4Smatt #define ICR_P1SC 0xcf4 /* PCI_1 select cause */ 75ff2281b4Smatt #define ICR_CI0M 0xe60 /* CPU int[0] mask */ 76ff2281b4Smatt #define ICR_CI1M 0xe64 /* CPU int[1] mask */ 77ff2281b4Smatt #define ICR_CI2M 0xe68 /* CPU int[2] mask */ 78ff2281b4Smatt #define ICR_CI3M 0xe6c /* CPU int[3] mask */ 79ff2281b4Smatt 80ff2281b4Smatt #define IRQ_DEV 1 /* device interface interrupt */ 81*077d1c0fSandvar #define IRQ_DMA 2 /* DMA address error interrupt */ 82ff2281b4Smatt #define IRQ_CPU 3 /* CPU interface interrupt */ 83ff2281b4Smatt #define IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt */ 84ff2281b4Smatt #define IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt */ 85ff2281b4Smatt #define IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt */ 86ff2281b4Smatt #define IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt */ 87ff2281b4Smatt #define IRQ_TIME0_1 8 /* Timer 0..1 interrupt */ 88ff2281b4Smatt #define IRQ_TIME2_3 9 /* Timer 2..3 interrupt */ 89ff2281b4Smatt #define IRQ_TIME4_5 10 /* Timer 4..5 interrupt */ 90ff2281b4Smatt #define IRQ_TIME6_7 11 /* Timer 6..7 interrupt */ 91ff2281b4Smatt #define IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary */ 92ff2281b4Smatt #define IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary */ 93ff2281b4Smatt #define IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */ 94ff2281b4Smatt #define IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */ 95ff2281b4Smatt #define IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary */ 96ff2281b4Smatt #define IRQ_ECC 17 /* ECC error interrupt */ 97ff2281b4Smatt #define IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */ 98ff2281b4Smatt #define IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */ 99ff2281b4Smatt #define IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */ 100ff2281b4Smatt #define IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */ 101ff2281b4Smatt #define IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */ 102ff2281b4Smatt #define IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */ 103ff2281b4Smatt #define IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */ 104ff2281b4Smatt #define IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */ 105ff2281b4Smatt #define IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */ 106ff2281b4Smatt #define IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */ 107ff2281b4Smatt #define IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */ 108a748aedcSkiyohara #define IRQ_ETH0 32 /* Ethernet controller 0 interrupt */ 109a748aedcSkiyohara #define IRQ_ETH1 33 /* Ethernet controller 1 interrupt */ 110a748aedcSkiyohara #define IRQ_ETH2 34 /* Ethernet controller 2 interrupt */ 111a748aedcSkiyohara #define IRQ_SDMA 36 /* SDMA interrupt */ 112a748aedcSkiyohara #define IRQ_I2C 37 /* I2C interrupt */ 113a748aedcSkiyohara #define IRQ_BRG 39 /* Baud Rate Generator interrupt */ 114a748aedcSkiyohara #define IRQ_MPSC0 40 /* MPSC 0 interrupt */ 115a748aedcSkiyohara #define IRQ_MPSC1 42 /* MPSC 1 interrupt */ 116a748aedcSkiyohara #define IRQ_COMM 43 /* Comm unit interrupt */ 117a748aedcSkiyohara #define IRQ_GPP7_0 56 /* GPP[7..0] interrupt */ 118a748aedcSkiyohara #define IRQ_GPP15_8 57 /* GPP[15..8] interrupt */ 119a748aedcSkiyohara #define IRQ_GPP23_16 58 /* GPP[23..16] interrupt */ 120a748aedcSkiyohara #define IRQ_GPP31_24 59 /* GPP[31..24] interrupt */ 121ff2281b4Smatt 122ff2281b4Smatt #endif /* _DISCOVERY_GT64260INTR_H */ 123