1*33ff1f69Sjoerg /* $NetBSD: gtbrgreg.h,v 1.3 2016/01/15 12:09:15 joerg Exp $ */ 2ff2281b4Smatt 3ff2281b4Smatt /* 4ff2281b4Smatt * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5ff2281b4Smatt * All rights reserved. 6ff2281b4Smatt * 7ff2281b4Smatt * Redistribution and use in source and binary forms, with or without 8ff2281b4Smatt * modification, are permitted provided that the following conditions 9ff2281b4Smatt * are met: 10ff2281b4Smatt * 1. Redistributions of source code must retain the above copyright 11ff2281b4Smatt * notice, this list of conditions and the following disclaimer. 12ff2281b4Smatt * 2. Redistributions in binary form must reproduce the above copyright 13ff2281b4Smatt * notice, this list of conditions and the following disclaimer in the 14ff2281b4Smatt * documentation and/or other materials provided with the distribution. 15ff2281b4Smatt * 3. All advertising materials mentioning features or use of this software 16ff2281b4Smatt * must display the following acknowledgement: 17ff2281b4Smatt * This product includes software developed for the NetBSD Project by 18ff2281b4Smatt * Allegro Networks, Inc., and Wasabi Systems, Inc. 19ff2281b4Smatt * 4. The name of Allegro Networks, Inc. may not be used to endorse 20ff2281b4Smatt * or promote products derived from this software without specific prior 21ff2281b4Smatt * written permission. 22ff2281b4Smatt * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23ff2281b4Smatt * or promote products derived from this software without specific prior 24ff2281b4Smatt * written permission. 25ff2281b4Smatt * 26ff2281b4Smatt * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27ff2281b4Smatt * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28ff2281b4Smatt * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29ff2281b4Smatt * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30ff2281b4Smatt * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31ff2281b4Smatt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32ff2281b4Smatt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33ff2281b4Smatt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34ff2281b4Smatt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35ff2281b4Smatt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36ff2281b4Smatt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37ff2281b4Smatt * POSSIBILITY OF SUCH DAMAGE. 38ff2281b4Smatt */ 39ff2281b4Smatt 40ff2281b4Smatt /* 41ff2281b4Smatt * gtbrgreg.h - register defines for GT-64260 Baud Rate Generator 42ff2281b4Smatt * 43ff2281b4Smatt * creation Thu Apr 12 21:47:54 PDT 2001 cliff 44ff2281b4Smatt */ 45ff2281b4Smatt 46ff2281b4Smatt #ifndef _GTBRGREG_H 47ff2281b4Smatt #define _GTBRGREG_H 48ff2281b4Smatt 49a748aedcSkiyohara #define GTBRG_NCHAN 3 /* Number of MPSC channels */ 50ff2281b4Smatt 51ff2281b4Smatt /******************************************************************************* 52ff2281b4Smatt * 53ff2281b4Smatt * BRG register address offsets relative to the base mapping 54ff2281b4Smatt */ 55a748aedcSkiyohara #define BRG_BCR(c) (0xb200 + ((c) << 3)) /* Baud Config Register */ 56a748aedcSkiyohara #define BRG_BTR(c) (0xb204 + ((c) << 3)) /* Baud Tuning Register */ 57ff2281b4Smatt #define BRG_CAUSE 0xb834 /* BRG Cause Register */ 58ff2281b4Smatt #define BRG_MASK 0xb8b4 /* BRG Cause Register */ 59ff2281b4Smatt 60ff2281b4Smatt /******************************************************************************* 61ff2281b4Smatt * 62ff2281b4Smatt * BRG register values & bit defines 63ff2281b4Smatt */ 64ff2281b4Smatt /* 65ff2281b4Smatt * BRG Configuration Register bits 66ff2281b4Smatt */ 67*33ff1f69Sjoerg #define BRG_BCR_CDV __BITS(15,0) /* Count Down Value */ 68*33ff1f69Sjoerg #define BRG_BCR_EN __BIT(16) /* Enable BRG */ 69*33ff1f69Sjoerg #define BRG_BCR_RST __BIT(17) /* Reset BRG */ 70*33ff1f69Sjoerg #define BRG_BCR_CLKS_MASK __BITS(22,18) /* Clock Source */ 71ff2281b4Smatt #define BRG_BCR_CLKS_BCLKIN (0 << 18) /* from MPP */ 72ff2281b4Smatt #define BRG_BCR_CLKS_SCLK0 (2 << 18) /* from S0 port */ 73ff2281b4Smatt #define BRG_BCR_CLKS_TSCLK0 (3 << 18) /* from S0 port */ 74ff2281b4Smatt #define BRG_BCR_CLKS_SCLK1 (6 << 18) /* from S1 port */ 75ff2281b4Smatt #define BRG_BCR_CLKS_TSCLK1 (7 << 18) /* from S1 port */ 76ff2281b4Smatt #define BRG_BCR_CLKS_TCLK (8 << 18) /* "Tclk" ??? */ 77ff2281b4Smatt /* all other values resvd. */ 78*33ff1f69Sjoerg #define BRG_BCR_RES __BITS(31,23) 79ff2281b4Smatt /* 80ff2281b4Smatt * BRG Baud Tuning Register bits 81ff2281b4Smatt */ 82*33ff1f69Sjoerg #define BRG_BTR_CUV __BITS(15,0) /* Count Up Value */ 83*33ff1f69Sjoerg #define BRG_BTR_RES __BITS(31,16) 84ff2281b4Smatt /* 85ff2281b4Smatt * BRG Cause and Mask interrupt Register bits 86ff2281b4Smatt */ 87*33ff1f69Sjoerg #define BRG_INTR_BTR0 __BIT(0) /* Baud Tuning 0 irpt. */ 88*33ff1f69Sjoerg #define BRG_INTR_BTR1 __BIT(1) /* Baud Tuning 1 irpt. */ 89*33ff1f69Sjoerg #define BRG_INTR_BTR2 __BIT(2) /* Baud Tuning 2 irpt. */ 90*33ff1f69Sjoerg #define BRG_INTR_RES __BITS(31,3) 91ff2281b4Smatt 92ff2281b4Smatt #endif /* _GTBRGREG_H */ 93