1 /* $NetBSD: wdc.c,v 1.291 2018/10/27 05:38:08 maya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.291 2018/10/27 05:38:08 maya Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/syslog.h> 74 #include <sys/proc.h> 75 76 #include <sys/intr.h> 77 #include <sys/bus.h> 78 79 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 80 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 81 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 82 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 83 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 84 #define bus_space_read_stream_2 bus_space_read_2 85 #define bus_space_read_stream_4 bus_space_read_4 86 #define bus_space_write_stream_2 bus_space_write_2 87 #define bus_space_write_stream_4 bus_space_write_4 88 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 89 90 #include <dev/ata/atavar.h> 91 #include <dev/ata/atareg.h> 92 #include <dev/ata/satareg.h> 93 #include <dev/ata/satavar.h> 94 #include <dev/ic/wdcreg.h> 95 #include <dev/ic/wdcvar.h> 96 97 #include "locators.h" 98 99 #include "atapibus.h" 100 #include "wd.h" 101 #include "sata.h" 102 103 #define WDCDELAY 100 /* 100 microseconds */ 104 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 105 #if 0 106 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 107 #define WDCNDELAY_DEBUG 50 108 #endif 109 110 /* When polling wait that much and then kpause for 1/hz seconds */ 111 #define WDCDELAY_POLL 1 /* ms */ 112 113 /* timeout for the control commands */ 114 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 115 116 /* 117 * timeout when waiting for BSY to deassert when probing. 118 * set to 5s. From the standards this could be up to 31, but we can't 119 * wait that much at boot time, and 5s seems to be enough. 120 */ 121 #define WDC_PROBE_WAIT 5 122 123 124 #if NWD > 0 125 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 126 #else 127 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 128 const struct ata_bustype wdc_ata_bustype = { 129 .bustype_type = SCSIPI_BUSTYPE_ATA, 130 .ata_bio = NULL, 131 .ata_reset_drive = NULL, 132 .ata_reset_channel = wdc_reset_channel, 133 .ata_exec_command = wdc_exec_command, 134 .ata_get_params = NULL, 135 .ata_addref = NULL, 136 .ata_delref = NULL, 137 .ata_killpending = NULL, 138 .ata_recovery = NULL, 139 }; 140 #endif 141 142 /* Flags to wdcreset(). */ 143 #define RESET_POLL 1 144 #define RESET_SLEEP 0 /* wdcreset() will use kpause() */ 145 146 static int wdcprobe1(struct ata_channel *, int); 147 static int wdcreset(struct ata_channel *, int); 148 static void __wdcerror(struct ata_channel *, const char *); 149 static int __wdcwait_reset(struct ata_channel *, int, int); 150 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 151 static void __wdccommand_poll(struct ata_channel *, struct ata_xfer *); 152 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 153 static void __wdccommand_kill_xfer(struct ata_channel *, 154 struct ata_xfer *, int); 155 static int __wdccommand_start(struct ata_channel *, struct ata_xfer *); 156 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 157 static int __wdcwait(struct ata_channel *, int, int, int, int *); 158 159 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 160 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 161 #define DEBUG_INTR 0x01 162 #define DEBUG_XFERS 0x02 163 #define DEBUG_STATUS 0x04 164 #define DEBUG_FUNCS 0x08 165 #define DEBUG_PROBE 0x10 166 #define DEBUG_DETACH 0x20 167 #define DEBUG_DELAY 0x40 168 #ifdef ATADEBUG 169 extern int atadebug_mask; /* init'ed in ata.c */ 170 int wdc_nxfer = 0; 171 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 172 #else 173 #define ATADEBUG_PRINT(args, level) 174 #endif 175 176 /* 177 * Initialize the "shadow register" handles for a standard wdc controller. 178 */ 179 void 180 wdc_init_shadow_regs(struct wdc_regs *wdr) 181 { 182 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 183 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 184 } 185 186 /* 187 * Allocate a wdc_regs array, based on the number of channels. 188 */ 189 void 190 wdc_allocate_regs(struct wdc_softc *wdc) 191 { 192 193 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 194 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 195 } 196 197 #if NSATA > 0 198 /* 199 * probe drives on SATA controllers with standard SATA registers: 200 * bring the PHYs online, read the drive signature and set drive flags 201 * appropriately. 202 */ 203 void 204 wdc_sataprobe(struct ata_channel *chp) 205 { 206 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 207 uint8_t st = 0, sc __unused, sn __unused, cl, ch; 208 int i; 209 210 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 211 212 /* do this before we take lock */ 213 214 ata_channel_lock(chp); 215 216 /* reset the PHY and bring online */ 217 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 218 wdr->sata_status, AT_WAIT)) { 219 case SStatus_DET_DEV: 220 /* wait 5s for BSY to clear */ 221 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 222 bus_space_write_1(wdr->cmd_iot, 223 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 224 delay(10); /* 400ns delay */ 225 st = bus_space_read_1(wdr->cmd_iot, 226 wdr->cmd_iohs[wd_status], 0); 227 if ((st & WDCS_BSY) == 0) 228 break; 229 ata_delay(chp, 1, "sataprb", AT_WAIT); 230 } 231 if (i == WDC_PROBE_WAIT * hz) 232 aprint_error_dev(chp->ch_atac->atac_dev, 233 "BSY never cleared, status 0x%02x\n", st); 234 sc = bus_space_read_1(wdr->cmd_iot, 235 wdr->cmd_iohs[wd_seccnt], 0); 236 sn = bus_space_read_1(wdr->cmd_iot, 237 wdr->cmd_iohs[wd_sector], 0); 238 cl = bus_space_read_1(wdr->cmd_iot, 239 wdr->cmd_iohs[wd_cyl_lo], 0); 240 ch = bus_space_read_1(wdr->cmd_iot, 241 wdr->cmd_iohs[wd_cyl_hi], 0); 242 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 243 "cl=0x%x ch=0x%x\n", 244 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 245 sc, sn, cl, ch), DEBUG_PROBE); 246 if (atabus_alloc_drives(chp, 1) != 0) 247 return; 248 /* 249 * sc and sn are supposed to be 0x1 for ATAPI, but in some 250 * cases we get wrong values here, so ignore it. 251 */ 252 if (cl == 0x14 && ch == 0xeb) 253 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 254 else 255 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 256 257 /* 258 * issue a reset in case only the interface part of the drive 259 * is up 260 */ 261 if (wdcreset(chp, RESET_SLEEP) != 0) 262 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 263 break; 264 265 default: 266 break; 267 } 268 269 ata_channel_unlock(chp); 270 } 271 #endif /* NSATA > 0 */ 272 273 274 /* Test to see controller with at last one attached drive is there. 275 * Returns a bit for each possible drive found (0x01 for drive 0, 276 * 0x02 for drive 1). 277 * Logic: 278 * - If a status register is at 0xff, assume there is no drive here 279 * (ISA has pull-up resistors). Similarly if the status register has 280 * the value we last wrote to the bus (for IDE interfaces without pullups). 281 * If no drive at all -> return. 282 * - reset the controller, wait for it to complete (may take up to 31s !). 283 * If timeout -> return. 284 * - test ATA/ATAPI signatures. If at last one drive found -> return. 285 * - try an ATA command on the master. 286 */ 287 288 void 289 wdc_drvprobe(struct ata_channel *chp) 290 { 291 struct ataparams params; /* XXX: large struct */ 292 struct atac_softc *atac = chp->ch_atac; 293 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 294 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 295 u_int8_t st0 = 0, st1 = 0; 296 int i, j, error, tfd; 297 298 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) 299 return; 300 if (wdcprobe1(chp, 0) == 0) { 301 /* No drives, abort the attach here. */ 302 atabus_free_drives(chp); 303 return; 304 } 305 306 ata_channel_lock(chp); 307 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 308 for (i = 0; i < mstohz(3000); i++) { 309 /* 310 * select drive 1 first, so that master is selected on 311 * exit from the loop 312 */ 313 if (chp->ch_ndrives > 1 && 314 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 315 if (wdc->select) 316 wdc->select(chp,1); 317 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 318 0, WDSD_IBM | 0x10); 319 delay(10); /* 400ns delay */ 320 st1 = bus_space_read_1(wdr->cmd_iot, 321 wdr->cmd_iohs[wd_status], 0); 322 } 323 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 324 if (wdc->select) 325 wdc->select(chp,0); 326 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 327 0, WDSD_IBM); 328 delay(10); /* 400ns delay */ 329 st0 = bus_space_read_1(wdr->cmd_iot, 330 wdr->cmd_iohs[wd_status], 0); 331 } 332 333 334 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 335 (st0 & WDCS_DRDY)) && 336 (chp->ch_ndrives < 2 || 337 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 338 (st1 & WDCS_DRDY))) 339 break; 340 #ifdef WDC_NO_IDS 341 /* cannot kpause here (can't enable IPL_BIO interrups), 342 * delay instead 343 */ 344 delay(1000000 / hz); 345 #else 346 ata_delay(chp, 1, "atadrdy", AT_WAIT); 347 #endif 348 } 349 if ((st0 & WDCS_DRDY) == 0 && 350 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 351 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 352 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 353 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 354 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 355 ata_channel_unlock(chp); 356 357 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 358 device_xname(atac->atac_dev), 359 chp->ch_channel, st0, st1), DEBUG_PROBE); 360 361 /* Wait a bit, some devices are weird just after a reset. */ 362 delay(5000); 363 364 for (i = 0; i < chp->ch_ndrives; i++) { 365 #if NATA_DMA 366 /* 367 * Init error counter so that an error within the first xfers 368 * will trigger a downgrade 369 */ 370 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 371 #endif 372 373 /* If controller can't do 16bit flag the drives as 32bit */ 374 if ((atac->atac_cap & 375 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 376 ata_channel_lock(chp); 377 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 378 ata_channel_unlock(chp); 379 } 380 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 381 continue; 382 383 /* Shortcut in case we've been shutdown */ 384 if (chp->ch_flags & ATACH_SHUTDOWN) 385 return; 386 387 /* 388 * Issue an identify, to try to detect ghosts. 389 * Note that we can't use interrupts here, because if there 390 * is no devices, we will get a command aborted without 391 * interrupts. 392 */ 393 error = ata_get_params(&chp->ch_drive[i], 394 AT_WAIT | AT_POLL, ¶ms); 395 if (error != CMD_OK) { 396 ata_channel_lock(chp); 397 ata_delay(chp, 1000, "atacnf", AT_WAIT); 398 ata_channel_unlock(chp); 399 400 /* Shortcut in case we've been shutdown */ 401 if (chp->ch_flags & ATACH_SHUTDOWN) 402 return; 403 404 error = ata_get_params(&chp->ch_drive[i], 405 AT_WAIT | AT_POLL, ¶ms); 406 } 407 if (error != CMD_OK) { 408 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 409 device_xname(atac->atac_dev), 410 chp->ch_channel, i, error), DEBUG_PROBE); 411 ata_channel_lock(chp); 412 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 413 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 414 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 415 ata_channel_unlock(chp); 416 continue; 417 } 418 /* 419 * Pre-ATA drive ? 420 * Test registers writability (Error register not 421 * writable, but cyllo is), then try an ATA command. 422 */ 423 if (wdc->select) 424 wdc->select(chp,i); 425 bus_space_write_1(wdr->cmd_iot, 426 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 427 delay(10); /* 400ns delay */ 428 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 429 0, 0x58); 430 bus_space_write_1(wdr->cmd_iot, 431 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 432 if (bus_space_read_1(wdr->cmd_iot, 433 wdr->cmd_iohs[wd_error], 0) == 0x58 || 434 bus_space_read_1(wdr->cmd_iot, 435 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 436 ATADEBUG_PRINT(("%s:%d:%d: register " 437 "writability failed\n", 438 device_xname(atac->atac_dev), 439 chp->ch_channel, i), DEBUG_PROBE); 440 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 441 ata_channel_unlock(chp); 442 continue; 443 } 444 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 445 WDCWAIT_TOUT) { 446 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 447 device_xname(atac->atac_dev), 448 chp->ch_channel, i), DEBUG_PROBE); 449 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 450 ata_channel_unlock(chp); 451 continue; 452 } 453 bus_space_write_1(wdr->cmd_iot, 454 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 455 delay(10); /* 400ns delay */ 456 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 457 WDCWAIT_TOUT) { 458 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 459 device_xname(atac->atac_dev), 460 chp->ch_channel, i), DEBUG_PROBE); 461 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 462 ata_channel_unlock(chp); 463 } else { 464 for (j = 0; j < chp->ch_ndrives; j++) { 465 if (chp->ch_drive[i].drive_type != 466 ATA_DRIVET_NONE) { 467 chp->ch_drive[j].drive_type = 468 ATA_DRIVET_OLD; 469 } 470 } 471 ata_channel_unlock(chp); 472 } 473 } 474 } 475 } 476 477 int 478 wdcprobe(struct wdc_regs *wdr) 479 { 480 struct wdc_softc wdc; 481 struct ata_channel ch; 482 int rv; 483 484 memset(&wdc, 0, sizeof(wdc)); 485 memset(&ch, 0, sizeof(ch)); 486 ata_channel_init(&ch); 487 ch.ch_atac = &wdc.sc_atac; 488 wdc.regs = wdr; 489 490 /* default reset method */ 491 if (wdc.reset == NULL) 492 wdc.reset = wdc_do_reset; 493 494 rv = wdcprobe1(&ch, 1); 495 496 ata_channel_destroy(&ch); 497 498 return rv; 499 } 500 501 static int 502 wdcprobe1(struct ata_channel *chp, int poll) 503 { 504 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 505 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 506 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; 507 u_int8_t ret_value = 0x03; 508 u_int8_t drive; 509 /* XXX if poll, wdc_probe_count is 0. */ 510 int wdc_probe_count = 511 poll ? (WDC_PROBE_WAIT / WDCDELAY) 512 : (WDC_PROBE_WAIT * hz); 513 514 /* 515 * Sanity check to see if the wdc channel responds at all. 516 */ 517 518 ata_channel_lock(chp); 519 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 520 while (wdc_probe_count-- > 0) { 521 if (wdc->select) 522 wdc->select(chp,0); 523 524 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 525 0, WDSD_IBM); 526 delay(10); /* 400ns delay */ 527 st0 = bus_space_read_1(wdr->cmd_iot, 528 wdr->cmd_iohs[wd_status], 0); 529 530 if (wdc->select) 531 wdc->select(chp,1); 532 533 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 534 0, WDSD_IBM | 0x10); 535 delay(10); /* 400ns delay */ 536 st1 = bus_space_read_1(wdr->cmd_iot, 537 wdr->cmd_iohs[wd_status], 0); 538 if ((st0 & WDCS_BSY) == 0) 539 break; 540 } 541 542 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 543 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); 544 545 if (st0 == 0xff || st0 == WDSD_IBM) 546 ret_value &= ~0x01; 547 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 548 ret_value &= ~0x02; 549 /* Register writability test, drive 0. */ 550 if (ret_value & 0x01) { 551 if (wdc->select) 552 wdc->select(chp,0); 553 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 554 0, WDSD_IBM); 555 bus_space_write_1(wdr->cmd_iot, 556 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 557 cl = bus_space_read_1(wdr->cmd_iot, 558 wdr->cmd_iohs[wd_cyl_lo], 0); 559 if (cl != 0x02) { 560 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 561 "got 0x%x != 0x02\n", 562 __func__, chp->ch_channel, cl), 563 DEBUG_PROBE); 564 ret_value &= ~0x01; 565 } 566 bus_space_write_1(wdr->cmd_iot, 567 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 568 cl = bus_space_read_1(wdr->cmd_iot, 569 wdr->cmd_iohs[wd_cyl_lo], 0); 570 if (cl != 0x01) { 571 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 572 "got 0x%x != 0x01\n", 573 __func__, chp->ch_channel, cl), 574 DEBUG_PROBE); 575 ret_value &= ~0x01; 576 } 577 bus_space_write_1(wdr->cmd_iot, 578 wdr->cmd_iohs[wd_sector], 0, 0x01); 579 cl = bus_space_read_1(wdr->cmd_iot, 580 wdr->cmd_iohs[wd_sector], 0); 581 if (cl != 0x01) { 582 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 583 "got 0x%x != 0x01\n", 584 __func__, chp->ch_channel, cl), 585 DEBUG_PROBE); 586 ret_value &= ~0x01; 587 } 588 bus_space_write_1(wdr->cmd_iot, 589 wdr->cmd_iohs[wd_sector], 0, 0x02); 590 cl = bus_space_read_1(wdr->cmd_iot, 591 wdr->cmd_iohs[wd_sector], 0); 592 if (cl != 0x02) { 593 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 594 "got 0x%x != 0x02\n", 595 __func__, chp->ch_channel, cl), 596 DEBUG_PROBE); 597 ret_value &= ~0x01; 598 } 599 cl = bus_space_read_1(wdr->cmd_iot, 600 wdr->cmd_iohs[wd_cyl_lo], 0); 601 if (cl != 0x01) { 602 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 603 "got 0x%x != 0x01\n", 604 __func__, chp->ch_channel, cl), 605 DEBUG_PROBE); 606 ret_value &= ~0x01; 607 } 608 } 609 /* Register writability test, drive 1. */ 610 if (ret_value & 0x02) { 611 if (wdc->select) 612 wdc->select(chp,1); 613 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 614 0, WDSD_IBM | 0x10); 615 bus_space_write_1(wdr->cmd_iot, 616 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 617 cl = bus_space_read_1(wdr->cmd_iot, 618 wdr->cmd_iohs[wd_cyl_lo], 0); 619 if (cl != 0x02) { 620 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 621 "got 0x%x != 0x02\n", 622 __func__, chp->ch_channel, cl), 623 DEBUG_PROBE); 624 ret_value &= ~0x02; 625 } 626 bus_space_write_1(wdr->cmd_iot, 627 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 628 cl = bus_space_read_1(wdr->cmd_iot, 629 wdr->cmd_iohs[wd_cyl_lo], 0); 630 if (cl != 0x01) { 631 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 632 "got 0x%x != 0x01\n", 633 __func__, chp->ch_channel, cl), 634 DEBUG_PROBE); 635 ret_value &= ~0x02; 636 } 637 bus_space_write_1(wdr->cmd_iot, 638 wdr->cmd_iohs[wd_sector], 0, 0x01); 639 cl = bus_space_read_1(wdr->cmd_iot, 640 wdr->cmd_iohs[wd_sector], 0); 641 if (cl != 0x01) { 642 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 643 "got 0x%x != 0x01\n", 644 __func__, chp->ch_channel, cl), 645 DEBUG_PROBE); 646 ret_value &= ~0x02; 647 } 648 bus_space_write_1(wdr->cmd_iot, 649 wdr->cmd_iohs[wd_sector], 0, 0x02); 650 cl = bus_space_read_1(wdr->cmd_iot, 651 wdr->cmd_iohs[wd_sector], 0); 652 if (cl != 0x02) { 653 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 654 "got 0x%x != 0x02\n", 655 __func__, chp->ch_channel, cl), 656 DEBUG_PROBE); 657 ret_value &= ~0x02; 658 } 659 cl = bus_space_read_1(wdr->cmd_iot, 660 wdr->cmd_iohs[wd_cyl_lo], 0); 661 if (cl != 0x01) { 662 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 663 "got 0x%x != 0x01\n", 664 __func__, chp->ch_channel, cl), 665 DEBUG_PROBE); 666 ret_value &= ~0x02; 667 } 668 } 669 670 if (ret_value == 0) { 671 ata_channel_unlock(chp); 672 return 0; 673 } 674 } 675 676 #if 0 /* XXX this break some ATA or ATAPI devices */ 677 /* 678 * reset bus. Also send an ATAPI_RESET to devices, in case there are 679 * ATAPI device out there which don't react to the bus reset 680 */ 681 if (ret_value & 0x01) { 682 if (wdc->select) 683 wdc->select(chp,0); 684 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 685 0, WDSD_IBM); 686 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 687 ATAPI_SOFT_RESET); 688 } 689 if (ret_value & 0x02) { 690 if (wdc->select) 691 wdc->select(chp,0); 692 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 693 0, WDSD_IBM | 0x10); 694 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 695 ATAPI_SOFT_RESET); 696 } 697 698 delay(5000); 699 #endif 700 701 wdc->reset(chp, RESET_POLL); 702 DELAY(2000); 703 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 704 705 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 706 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 707 WDCTL_4BIT); 708 709 #ifdef WDC_NO_IDS 710 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 711 #else 712 ret_value = __wdcwait_reset(chp, ret_value, poll); 713 #endif 714 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n", 715 __func__, chp->ch_channel, ret_value), DEBUG_PROBE); 716 717 /* if reset failed, there's nothing here */ 718 if (ret_value == 0) { 719 ata_channel_unlock(chp); 720 return 0; 721 } 722 723 /* 724 * Test presence of drives. First test register signatures looking 725 * for ATAPI devices. If it's not an ATAPI and reset said there may 726 * be something here assume it's ATA or OLD. Ghost will be killed 727 * later in attach routine. 728 */ 729 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 730 if ((ret_value & (0x01 << drive)) == 0) 731 continue; 732 if (wdc->select) 733 wdc->select(chp,drive); 734 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 735 WDSD_IBM | (drive << 4)); 736 delay(10); /* 400ns delay */ 737 /* Save registers contents */ 738 sc = bus_space_read_1(wdr->cmd_iot, 739 wdr->cmd_iohs[wd_seccnt], 0); 740 sn = bus_space_read_1(wdr->cmd_iot, 741 wdr->cmd_iohs[wd_sector], 0); 742 cl = bus_space_read_1(wdr->cmd_iot, 743 wdr->cmd_iohs[wd_cyl_lo], 0); 744 ch = bus_space_read_1(wdr->cmd_iot, 745 wdr->cmd_iohs[wd_cyl_hi], 0); 746 747 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 748 "cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc, 749 sn, cl, ch), DEBUG_PROBE); 750 /* 751 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 752 * we get wrong values here, so ignore it. 753 */ 754 if (chp->ch_drive != NULL) { 755 if (cl == 0x14 && ch == 0xeb) { 756 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 757 } else { 758 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 759 } 760 } 761 } 762 /* 763 * Select an existing drive before lowering spl, some WDC_NO_IDS 764 * devices incorrectly assert IRQ on nonexistent slave 765 */ 766 if (ret_value & 0x01) { 767 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 768 WDSD_IBM); 769 (void)bus_space_read_1(wdr->cmd_iot, 770 wdr->cmd_iohs[wd_status], 0); 771 } 772 ata_channel_unlock(chp); 773 return (ret_value); 774 } 775 776 void 777 wdcattach(struct ata_channel *chp) 778 { 779 struct atac_softc *atac = chp->ch_atac; 780 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 781 782 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 783 784 /* default data transfer methods */ 785 if (wdc->datain_pio == NULL) 786 wdc->datain_pio = wdc_datain_pio; 787 if (wdc->dataout_pio == NULL) 788 wdc->dataout_pio = wdc_dataout_pio; 789 /* default reset method */ 790 if (wdc->reset == NULL) 791 wdc->reset = wdc_do_reset; 792 793 /* initialise global data */ 794 if (atac->atac_bustype_ata == NULL) 795 atac->atac_bustype_ata = &wdc_ata_bustype; 796 if (atac->atac_probe == NULL) 797 atac->atac_probe = wdc_drvprobe; 798 #if NATAPIBUS > 0 799 if (atac->atac_atapibus_attach == NULL) 800 atac->atac_atapibus_attach = wdc_atapibus_attach; 801 #endif 802 803 ata_channel_attach(chp); 804 } 805 806 void 807 wdc_childdetached(device_t self, device_t child) 808 { 809 struct atac_softc *atac = device_private(self); 810 struct ata_channel *chp; 811 int i; 812 813 for (i = 0; i < atac->atac_nchannels; i++) { 814 chp = atac->atac_channels[i]; 815 if (child == chp->atabus) { 816 chp->atabus = NULL; 817 return; 818 } 819 } 820 } 821 822 int 823 wdcdetach(device_t self, int flags) 824 { 825 struct atac_softc *atac = device_private(self); 826 struct ata_channel *chp; 827 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 828 int i, error = 0; 829 830 for (i = 0; i < atac->atac_nchannels; i++) { 831 chp = atac->atac_channels[i]; 832 if (chp->atabus == NULL) 833 continue; 834 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 835 device_xname(atac->atac_dev), device_xname(chp->atabus)), 836 DEBUG_DETACH); 837 if ((error = config_detach(chp->atabus, flags)) != 0) 838 return error; 839 ata_channel_detach(chp); 840 } 841 if (adapt->adapt_refcnt != 0) 842 return EBUSY; 843 return 0; 844 } 845 846 /* restart an interrupted I/O */ 847 void 848 wdcrestart(void *v) 849 { 850 struct ata_channel *chp = v; 851 int s; 852 853 s = splbio(); 854 atastart(chp); 855 splx(s); 856 } 857 858 859 /* 860 * Interrupt routine for the controller. Acknowledge the interrupt, check for 861 * errors on the current operation, mark it done if necessary, and start the 862 * next request. Also check for a partially done transfer, and continue with 863 * the next chunk if so. 864 */ 865 int 866 wdcintr(void *arg) 867 { 868 struct ata_channel *chp = arg; 869 struct atac_softc *atac = chp->ch_atac; 870 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 871 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 872 struct ata_xfer *xfer; 873 int ret; 874 875 if (!device_is_active(atac->atac_dev)) { 876 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 877 DEBUG_INTR); 878 return (0); 879 } 880 881 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 882 ATADEBUG_PRINT(("wdcintr: irq not expected\n"), DEBUG_INTR); 883 goto ignore; 884 } 885 886 xfer = ata_queue_get_active_xfer(chp); 887 if (xfer == NULL) { 888 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 889 ignore: 890 /* try to clear the pending interrupt anyway */ 891 (void)bus_space_read_1(wdr->cmd_iot, 892 wdr->cmd_iohs[wd_status], 0); 893 return (0); 894 } 895 896 /* 897 * On some controllers (e.g. some PCI-IDE) setting the WDCTL_IDS bit 898 * actually has no effect, and interrupt is triggered regardless. 899 * Ignore polled commands here, they are processed separately. 900 */ 901 if (ISSET(xfer->c_flags, C_POLL)) { 902 ATADEBUG_PRINT(("%s: polled xfer ignored\n", __func__), 903 DEBUG_INTR); 904 goto ignore; 905 } 906 907 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 908 KASSERT(xfer != NULL); 909 910 #if NATA_DMA || NATA_PIOBM 911 if (chp->ch_flags & ATACH_DMA_WAIT) { 912 wdc->dma_status = 913 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 914 xfer->c_drive, WDC_DMAEND_END); 915 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 916 /* IRQ not for us, not detected by DMA engine */ 917 return 0; 918 } 919 chp->ch_flags &= ~ATACH_DMA_WAIT; 920 } 921 #endif 922 chp->ch_flags &= ~ATACH_IRQ_WAIT; 923 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 924 ret = xfer->ops->c_intr(chp, xfer, 1); 925 if (ret == 0) /* irq was not for us, still waiting for irq */ 926 chp->ch_flags |= ATACH_IRQ_WAIT; 927 return (ret); 928 } 929 930 /* Put all disk in RESET state */ 931 void 932 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 933 { 934 struct ata_channel *chp = drvp->chnl_softc; 935 936 ata_channel_lock_owned(chp); 937 938 KASSERT(sigp == NULL); 939 940 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 941 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 942 drvp->drive), DEBUG_FUNCS); 943 944 ata_thread_run(chp, flags, ATACH_TH_RESET, ATACH_NODRIVE); 945 } 946 947 void 948 wdc_reset_channel(struct ata_channel *chp, int flags) 949 { 950 struct ata_xfer *xfer; 951 952 ata_channel_lock_owned(chp); 953 954 #if NATA_DMA || NATA_PIOBM 955 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 956 #endif 957 958 chp->ch_flags &= ~ATACH_IRQ_WAIT; 959 960 /* 961 * if the current command is on an ATAPI device, issue a 962 * ATAPI_SOFT_RESET 963 */ 964 xfer = ata_queue_get_active_xfer_locked(chp); 965 966 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 967 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 968 ata_delay(chp, 1000, "atardl", flags); 969 } 970 971 /* reset the channel */ 972 if (flags & AT_WAIT) 973 (void) wdcreset(chp, RESET_SLEEP); 974 else 975 (void) wdcreset(chp, RESET_POLL); 976 977 /* 978 * wait a bit after reset; in case the DMA engines needs some time 979 * to recover. 980 */ 981 ata_delay(chp, 1000, "atardl", flags); 982 983 /* 984 * Look for pending xfers. If we have a shared queue, we'll also reset 985 * the other channel if the current xfer is running on it. 986 * Then we'll kill the eventual active transfer explicitely, so that 987 * it is queued for retry immediatelly without waiting for I/O timeout. 988 */ 989 if (xfer) { 990 if (xfer->c_chp != chp) { 991 ata_thread_run(xfer->c_chp, flags, ATACH_TH_RESET, 992 ATACH_NODRIVE); 993 } else { 994 #if NATA_DMA || NATA_PIOBM 995 /* 996 * If we're waiting for DMA, stop the 997 * DMA engine 998 */ 999 if (chp->ch_flags & ATACH_DMA_WAIT) { 1000 (*wdc->dma_finish)(wdc->dma_arg, 1001 chp->ch_channel, xfer->c_drive, 1002 WDC_DMAEND_ABRT_QUIET); 1003 chp->ch_flags &= ~ATACH_DMA_WAIT; 1004 } 1005 #endif 1006 } 1007 } 1008 1009 ata_kill_active(chp, KILL_RESET, flags); 1010 } 1011 1012 static int 1013 wdcreset(struct ata_channel *chp, int poll) 1014 { 1015 struct atac_softc *atac = chp->ch_atac; 1016 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1017 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1018 int drv_mask1, drv_mask2; 1019 1020 ata_channel_lock_owned(chp); 1021 1022 #ifdef WDC_NO_IDS 1023 poll = RESET_POLL; 1024 #endif 1025 wdc->reset(chp, poll); 1026 1027 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) 1028 ? 0x01 : 0x00; 1029 if (chp->ch_ndrives > 1) 1030 drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) 1031 ? 0x02 : 0x00; 1032 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1033 (poll == RESET_SLEEP) ? 0 : 1); 1034 if (drv_mask2 != drv_mask1) { 1035 aprint_error("%s channel %d: reset failed for", 1036 device_xname(atac->atac_dev), chp->ch_channel); 1037 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1038 aprint_normal(" drive 0"); 1039 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1040 aprint_normal(" drive 1"); 1041 aprint_normal("\n"); 1042 } 1043 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1044 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1045 WDCTL_4BIT); 1046 1047 return (drv_mask1 != drv_mask2) ? 1 : 0; 1048 } 1049 1050 void 1051 wdc_do_reset(struct ata_channel *chp, int poll) 1052 { 1053 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1054 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1055 int s = 0; 1056 1057 if (poll != RESET_SLEEP) 1058 s = splbio(); 1059 if (wdc->select) 1060 wdc->select(chp,0); 1061 /* master */ 1062 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1063 delay(10); /* 400ns delay */ 1064 /* assert SRST, wait for reset to complete */ 1065 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1066 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1067 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1068 delay(2000); 1069 } 1070 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1071 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1072 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1073 WDCTL_4BIT | WDCTL_IDS); 1074 delay(10); /* 400ns delay */ 1075 if (poll != RESET_SLEEP) { 1076 /* ACK interrupt in case there is one pending left */ 1077 if (wdc->irqack) 1078 wdc->irqack(chp); 1079 splx(s); 1080 } 1081 } 1082 1083 static int 1084 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1085 { 1086 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1087 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1088 int timeout, nloop; 1089 int wflags = poll ? AT_POLL : AT_WAIT; 1090 u_int8_t st0 = 0, st1 = 0; 1091 #ifdef ATADEBUG 1092 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1093 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1094 #endif 1095 if (poll) 1096 nloop = WDCNDELAY_RST; 1097 else 1098 nloop = WDC_RESET_WAIT * hz / 1000; 1099 /* wait for BSY to deassert */ 1100 for (timeout = 0; timeout < nloop; timeout++) { 1101 if ((drv_mask & 0x01) != 0) { 1102 if (wdc->select) 1103 wdc->select(chp,0); 1104 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1105 0, WDSD_IBM); /* master */ 1106 delay(10); 1107 st0 = bus_space_read_1(wdr->cmd_iot, 1108 wdr->cmd_iohs[wd_status], 0); 1109 #ifdef ATADEBUG 1110 sc0 = bus_space_read_1(wdr->cmd_iot, 1111 wdr->cmd_iohs[wd_seccnt], 0); 1112 sn0 = bus_space_read_1(wdr->cmd_iot, 1113 wdr->cmd_iohs[wd_sector], 0); 1114 cl0 = bus_space_read_1(wdr->cmd_iot, 1115 wdr->cmd_iohs[wd_cyl_lo], 0); 1116 ch0 = bus_space_read_1(wdr->cmd_iot, 1117 wdr->cmd_iohs[wd_cyl_hi], 0); 1118 #endif 1119 } 1120 if ((drv_mask & 0x02) != 0) { 1121 if (wdc->select) 1122 wdc->select(chp,1); 1123 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1124 0, WDSD_IBM | 0x10); /* slave */ 1125 delay(10); 1126 st1 = bus_space_read_1(wdr->cmd_iot, 1127 wdr->cmd_iohs[wd_status], 0); 1128 #ifdef ATADEBUG 1129 sc1 = bus_space_read_1(wdr->cmd_iot, 1130 wdr->cmd_iohs[wd_seccnt], 0); 1131 sn1 = bus_space_read_1(wdr->cmd_iot, 1132 wdr->cmd_iohs[wd_sector], 0); 1133 cl1 = bus_space_read_1(wdr->cmd_iot, 1134 wdr->cmd_iohs[wd_cyl_lo], 0); 1135 ch1 = bus_space_read_1(wdr->cmd_iot, 1136 wdr->cmd_iohs[wd_cyl_hi], 0); 1137 #endif 1138 } 1139 1140 if ((drv_mask & 0x01) == 0) { 1141 /* no master */ 1142 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1143 /* No master, slave is ready, it's done */ 1144 goto end; 1145 } 1146 if ((drv_mask & 0x02) == 0) { 1147 /* No master, no slave: it's done */ 1148 goto end; 1149 } 1150 } else if ((drv_mask & 0x02) == 0) { 1151 /* no slave */ 1152 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1153 /* No slave, master is ready, it's done */ 1154 goto end; 1155 } 1156 } else { 1157 /* Wait for both master and slave to be ready */ 1158 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1159 goto end; 1160 } 1161 } 1162 ata_delay(chp, WDCDELAY, "atarst", wflags); 1163 } 1164 /* Reset timed out. Maybe it's because drv_mask was not right */ 1165 if (st0 & WDCS_BSY) 1166 drv_mask &= ~0x01; 1167 if (st1 & WDCS_BSY) 1168 drv_mask &= ~0x02; 1169 end: 1170 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1171 "cl=0x%x ch=0x%x\n", 1172 device_xname(chp->ch_atac->atac_dev), 1173 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1174 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1175 "cl=0x%x ch=0x%x\n", 1176 device_xname(chp->ch_atac->atac_dev), 1177 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1178 1179 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1180 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1181 st0, st1), DEBUG_PROBE); 1182 1183 return drv_mask; 1184 } 1185 1186 /* 1187 * Wait for a drive to be !BSY, and have mask in its status register. 1188 * return -1 for a timeout after "timeout" ms. 1189 */ 1190 static int 1191 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd) 1192 { 1193 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1194 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1195 u_char status, error = 0; 1196 int xtime = 0; 1197 int rv; 1198 1199 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1200 device_xname(chp->ch_atac->atac_dev), 1201 chp->ch_channel), DEBUG_STATUS); 1202 *tfd = 0; 1203 1204 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1205 1206 for (;;) { 1207 status = 1208 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1209 if ((status & (WDCS_BSY | mask)) == bits) 1210 break; 1211 if (++xtime > timeout) { 1212 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1213 "status %x error %x (mask 0x%x bits 0x%x)\n", 1214 xtime, status, 1215 bus_space_read_1(wdr->cmd_iot, 1216 wdr->cmd_iohs[wd_error], 0), mask, bits), 1217 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1218 rv = WDCWAIT_TOUT; 1219 goto out; 1220 } 1221 delay(WDCDELAY); 1222 } 1223 #ifdef ATADEBUG 1224 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1225 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1226 #endif 1227 if (status & WDCS_ERR) 1228 error = bus_space_read_1(wdr->cmd_iot, 1229 wdr->cmd_iohs[wd_error], 0); 1230 #ifdef WDCNDELAY_DEBUG 1231 /* After autoconfig, there should be no long delays. */ 1232 if (!cold && xtime > WDCNDELAY_DEBUG) { 1233 struct ata_xfer *xfer; 1234 1235 xfer = ata_queue_get_active_xfer(chp); 1236 if (xfer == NULL) 1237 printf("%s channel %d: warning: busy-wait took %dus\n", 1238 device_xname(chp->ch_atac->atac_dev), 1239 chp->ch_channel, WDCDELAY * xtime); 1240 else 1241 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1242 device_xname(chp->ch_atac->atac_dev), 1243 chp->ch_channel, xfer->c_drive, 1244 WDCDELAY * xtime); 1245 } 1246 #endif 1247 rv = WDCWAIT_OK; 1248 1249 out: 1250 *tfd = ATACH_ERR_ST(error, status); 1251 return rv; 1252 } 1253 1254 /* 1255 * Call __wdcwait(), polling using kpause() or waking up the kernel 1256 * thread if possible 1257 */ 1258 int 1259 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags, 1260 int *tfd) 1261 { 1262 int error, i, timeout_hz = mstohz(timeout); 1263 1264 ata_channel_lock_owned(chp); 1265 1266 if (timeout_hz == 0 || 1267 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1268 error = __wdcwait(chp, mask, bits, timeout, tfd); 1269 else { 1270 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd); 1271 if (error != 0) { 1272 if ((chp->ch_flags & ATACH_TH_RUN) || 1273 (flags & AT_WAIT)) { 1274 /* 1275 * we're running in the channel thread 1276 * or some userland thread context 1277 */ 1278 for (i = 0; i < timeout_hz; i++) { 1279 if (__wdcwait(chp, mask, bits, 1280 WDCDELAY_POLL, tfd) == 0) { 1281 error = 0; 1282 break; 1283 } 1284 kpause("atapoll", true, 1, 1285 &chp->ch_lock); 1286 } 1287 } else { 1288 /* 1289 * we're probably in interrupt context, 1290 * caller must ask the thread to come back here 1291 */ 1292 return(WDCWAIT_THR); 1293 } 1294 } 1295 } 1296 return (error); 1297 } 1298 1299 1300 #if NATA_DMA 1301 /* 1302 * Busy-wait for DMA to complete 1303 */ 1304 int 1305 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1306 { 1307 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1308 int xtime; 1309 1310 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1311 wdc->dma_status = 1312 (*wdc->dma_finish)(wdc->dma_arg, 1313 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1314 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1315 return 0; 1316 delay(WDCDELAY); 1317 } 1318 /* timeout, force a DMA halt */ 1319 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1320 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1321 return 1; 1322 } 1323 #endif 1324 1325 void 1326 wdctimeout(void *arg) 1327 { 1328 struct ata_xfer *xfer; 1329 struct ata_channel *chp = arg; 1330 #if NATA_DMA || NATA_PIOBM 1331 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1332 #endif 1333 int s; 1334 1335 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1336 1337 s = splbio(); 1338 1339 callout_ack(&chp->c_timo_callout); 1340 1341 xfer = ata_queue_get_active_xfer(chp); 1342 KASSERT(xfer != NULL); 1343 1344 if (ata_timo_xfer_check(xfer)) { 1345 /* Already logged */ 1346 goto out; 1347 } 1348 1349 __wdcerror(chp, "lost interrupt"); 1350 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1351 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1352 xfer->c_bcount, xfer->c_skip); 1353 #if NATA_DMA || NATA_PIOBM 1354 if (chp->ch_flags & ATACH_DMA_WAIT) { 1355 wdc->dma_status = 1356 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 1357 xfer->c_drive, WDC_DMAEND_ABRT); 1358 chp->ch_flags &= ~ATACH_DMA_WAIT; 1359 } 1360 #endif 1361 /* 1362 * Call the interrupt routine. If we just missed an interrupt, 1363 * it will do what's needed. Else, it will take the needed 1364 * action (reset the device). 1365 * Before that we need to reinstall the timeout callback, 1366 * in case it will miss another irq while in this transfer 1367 * We arbitray chose it to be 1s 1368 */ 1369 callout_reset(&chp->c_timo_callout, hz, wdctimeout, chp); 1370 xfer->c_flags |= C_TIMEOU; 1371 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 1372 xfer->ops->c_intr(chp, xfer, 1); 1373 1374 out: 1375 splx(s); 1376 } 1377 1378 static const struct ata_xfer_ops wdc_cmd_xfer_ops = { 1379 .c_start = __wdccommand_start, 1380 .c_poll = __wdccommand_poll, 1381 .c_abort = __wdccommand_done, 1382 .c_intr = __wdccommand_intr, 1383 .c_kill_xfer = __wdccommand_kill_xfer, 1384 }; 1385 1386 int 1387 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1388 { 1389 struct ata_channel *chp = drvp->chnl_softc; 1390 struct ata_command *ata_c = &xfer->c_ata_c; 1391 int s, ret; 1392 1393 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1394 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1395 drvp->drive), DEBUG_FUNCS); 1396 1397 /* set up an xfer and queue. Wait for completion */ 1398 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1399 ata_c->flags |= AT_POLL; 1400 if (ata_c->flags & AT_POLL) 1401 xfer->c_flags |= C_POLL; 1402 if (ata_c->flags & AT_WAIT) 1403 xfer->c_flags |= C_WAIT; 1404 xfer->c_drive = drvp->drive; 1405 xfer->c_databuf = ata_c->data; 1406 xfer->c_bcount = ata_c->bcount; 1407 xfer->ops = &wdc_cmd_xfer_ops; 1408 1409 s = splbio(); 1410 ata_exec_xfer(chp, xfer); 1411 #ifdef DIAGNOSTIC 1412 if ((ata_c->flags & AT_POLL) != 0 && 1413 (ata_c->flags & AT_DONE) == 0) 1414 panic("wdc_exec_command: polled command not done"); 1415 #endif 1416 if (ata_c->flags & AT_DONE) { 1417 ret = ATACMD_COMPLETE; 1418 } else { 1419 if (ata_c->flags & AT_WAIT) { 1420 ata_wait_cmd(chp, xfer); 1421 ret = ATACMD_COMPLETE; 1422 } else { 1423 ret = ATACMD_QUEUED; 1424 } 1425 } 1426 splx(s); 1427 return ret; 1428 } 1429 1430 static int 1431 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1432 { 1433 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1434 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1435 int drive = xfer->c_drive; 1436 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1437 struct ata_command *ata_c = &xfer->c_ata_c; 1438 int tfd; 1439 1440 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1441 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1442 xfer->c_drive), DEBUG_FUNCS); 1443 1444 if (wdc->select) 1445 wdc->select(chp,drive); 1446 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1447 WDSD_IBM | (drive << 4)); 1448 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1449 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1450 case WDCWAIT_OK: 1451 break; 1452 case WDCWAIT_TOUT: 1453 ata_c->flags |= AT_TIMEOU; 1454 return ATASTART_ABORT; 1455 case WDCWAIT_THR: 1456 return ATASTART_TH; 1457 } 1458 if (ata_c->flags & AT_POLL) { 1459 /* polled command, disable interrupts */ 1460 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1461 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1462 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1463 } 1464 if ((ata_c->flags & AT_LBA48) != 0) { 1465 wdccommandext(chp, drive, ata_c->r_command, 1466 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1467 ata_c->r_device & ~0x10); 1468 } else { 1469 wdccommand(chp, drive, ata_c->r_command, 1470 (ata_c->r_lba >> 8) & 0xffff, 1471 WDSD_IBM | (drive << 4) | 1472 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1473 ((ata_c->r_lba >> 24) & 0x0f), 1474 ata_c->r_lba & 0xff, 1475 ata_c->r_count & 0xff, 1476 ata_c->r_features & 0xff); 1477 } 1478 1479 if ((ata_c->flags & AT_POLL) == 0) { 1480 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1481 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1482 wdctimeout, chp); 1483 return ATASTART_STARTED; 1484 } 1485 1486 /* 1487 * Polled command. Wait for drive ready or drq. Done in intr(). 1488 * Wait for at last 400ns for status bit to be valid. 1489 */ 1490 delay(10); /* 400ns delay */ 1491 return ATASTART_POLL; 1492 } 1493 1494 static void 1495 __wdccommand_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1496 { 1497 __wdccommand_intr(chp, xfer, 0); 1498 } 1499 1500 static int 1501 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1502 { 1503 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1504 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1505 struct ata_command *ata_c = &xfer->c_ata_c; 1506 int bcount = ata_c->bcount; 1507 char *data = ata_c->data; 1508 int wflags, tfd; 1509 int drive_flags; 1510 1511 if (ata_c->r_command == WDCC_IDENTIFY || 1512 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1513 /* 1514 * The IDENTIFY data has been designed as an array of 1515 * u_int16_t, so we can byteswap it on the fly. 1516 * Historically it's what we have always done so keeping it 1517 * here ensure binary backward compatibility. 1518 */ 1519 drive_flags = ATA_DRIVE_NOSTREAM | 1520 chp->ch_drive[xfer->c_drive].drive_flags; 1521 } else { 1522 /* 1523 * Other data structure are opaque and should be transfered 1524 * as is. 1525 */ 1526 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1527 } 1528 1529 #ifdef WDC_NO_IDS 1530 wflags = AT_POLL; 1531 #else 1532 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1533 /* both wait and poll, we can kpause here */ 1534 wflags = AT_WAIT | AT_POLL; 1535 } else { 1536 wflags = AT_POLL; 1537 } 1538 #endif 1539 1540 ata_channel_lock(chp); 1541 1542 again: 1543 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1544 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1545 xfer->c_drive), DEBUG_INTR); 1546 /* 1547 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1548 * Reselect again, it doesn't hurt for others commands, and the time 1549 * penalty for the extra register write is acceptable, 1550 * wdc_exec_command() isn't called often (mostly for autoconfig) 1551 */ 1552 if ((xfer->c_flags & C_ATAPI) != 0) { 1553 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1554 WDSD_IBM | (xfer->c_drive << 4)); 1555 } 1556 if ((ata_c->flags & AT_XFDONE) != 0) { 1557 /* 1558 * We have completed a data xfer. The drive should now be 1559 * in its initial state 1560 */ 1561 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1562 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1563 wflags, &tfd) == WDCWAIT_TOUT) { 1564 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1565 ata_channel_unlock(chp); 1566 return 0; /* IRQ was not for us */ 1567 } 1568 ata_c->flags |= AT_TIMEOU; 1569 } 1570 goto out; 1571 } 1572 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1573 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1574 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1575 ata_channel_unlock(chp); 1576 return 0; /* IRQ was not for us */ 1577 } 1578 ata_c->flags |= AT_TIMEOU; 1579 goto out; 1580 } 1581 if (wdc->irqack) 1582 wdc->irqack(chp); 1583 if (ata_c->flags & AT_READ) { 1584 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1585 ata_c->flags |= AT_TIMEOU; 1586 goto out; 1587 } 1588 wdc->datain_pio(chp, drive_flags, data, bcount); 1589 /* at this point the drive should be in its initial state */ 1590 ata_c->flags |= AT_XFDONE; 1591 /* 1592 * XXX checking the status register again here cause some 1593 * hardware to timeout. 1594 */ 1595 } else if (ata_c->flags & AT_WRITE) { 1596 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1597 ata_c->flags |= AT_TIMEOU; 1598 goto out; 1599 } 1600 wdc->dataout_pio(chp, drive_flags, data, bcount); 1601 ata_c->flags |= AT_XFDONE; 1602 if ((ata_c->flags & AT_POLL) == 0) { 1603 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1604 callout_reset(&chp->c_timo_callout, 1605 mstohz(ata_c->timeout), wdctimeout, chp); 1606 ata_channel_unlock(chp); 1607 return 1; 1608 } else { 1609 goto again; 1610 } 1611 } 1612 out: 1613 if (ATACH_ST(tfd) & WDCS_DWF) 1614 ata_c->flags |= AT_DF; 1615 if (ATACH_ST(tfd) & WDCS_ERR) { 1616 ata_c->flags |= AT_ERROR; 1617 ata_c->r_error = ATACH_ST(tfd); 1618 } 1619 1620 ata_channel_unlock(chp); 1621 1622 __wdccommand_done(chp, xfer); 1623 return 1; 1624 } 1625 1626 static void 1627 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1628 { 1629 struct atac_softc *atac = chp->ch_atac; 1630 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1631 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1632 struct ata_command *ata_c = &xfer->c_ata_c; 1633 bool start = true; 1634 1635 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1636 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1637 ata_c->flags), DEBUG_FUNCS); 1638 1639 if (ata_waitdrain_xfer_check(chp, xfer)) { 1640 start = false; 1641 goto out; 1642 } 1643 1644 if ((ata_c->flags & AT_READREG) != 0 && 1645 device_is_active(atac->atac_dev) && 1646 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1647 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1648 wdr->cmd_iohs[wd_status], 0); 1649 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1650 wdr->cmd_iohs[wd_error], 0); 1651 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1652 wdr->cmd_iohs[wd_seccnt], 0); 1653 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1654 wdr->cmd_iohs[wd_sector], 0) << 0; 1655 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1656 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1657 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1658 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1659 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1660 wdr->cmd_iohs[wd_sdh], 0); 1661 1662 if ((ata_c->flags & AT_LBA48) != 0) { 1663 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1664 if ((ata_c->flags & AT_POLL) != 0) 1665 bus_space_write_1(wdr->ctl_iot, 1666 wdr->ctl_ioh, wd_aux_ctlr, 1667 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1668 else 1669 bus_space_write_1(wdr->ctl_iot, 1670 wdr->ctl_ioh, wd_aux_ctlr, 1671 WDCTL_HOB|WDCTL_4BIT); 1672 } 1673 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1674 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1675 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1676 wdr->cmd_iohs[wd_sector], 0) << 24; 1677 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1678 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1679 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1680 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1681 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1682 if ((ata_c->flags & AT_POLL) != 0) 1683 bus_space_write_1(wdr->ctl_iot, 1684 wdr->ctl_ioh, wd_aux_ctlr, 1685 WDCTL_4BIT|WDCTL_IDS); 1686 else 1687 bus_space_write_1(wdr->ctl_iot, 1688 wdr->ctl_ioh, wd_aux_ctlr, 1689 WDCTL_4BIT); 1690 } 1691 } else { 1692 ata_c->r_lba |= 1693 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1694 } 1695 ata_c->r_device &= 0xf0; 1696 } 1697 1698 __wdccommand_done_end(chp, xfer); 1699 1700 ata_deactivate_xfer(chp, xfer); 1701 1702 out: 1703 if (ata_c->flags & AT_POLL) { 1704 /* enable interrupts */ 1705 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1706 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1707 wd_aux_ctlr, WDCTL_4BIT); 1708 delay(10); /* some drives need a little delay here */ 1709 } 1710 1711 if (start) 1712 atastart(chp); 1713 } 1714 1715 static void 1716 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1717 { 1718 struct ata_command *ata_c = &xfer->c_ata_c; 1719 1720 ata_c->flags |= AT_DONE; 1721 } 1722 1723 static void 1724 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1725 int reason) 1726 { 1727 struct ata_command *ata_c = &xfer->c_ata_c; 1728 bool deactivate = true; 1729 1730 switch (reason) { 1731 case KILL_GONE_INACTIVE: 1732 deactivate = false; 1733 /* FALLTHROUGH */ 1734 case KILL_GONE: 1735 ata_c->flags |= AT_GONE; 1736 break; 1737 case KILL_RESET: 1738 ata_c->flags |= AT_RESET; 1739 break; 1740 default: 1741 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1742 reason); 1743 panic("__wdccommand_kill_xfer"); 1744 } 1745 1746 __wdccommand_done_end(chp, xfer); 1747 1748 if (deactivate) 1749 ata_deactivate_xfer(chp, xfer); 1750 } 1751 1752 /* 1753 * Send a command. The drive should be ready. 1754 * Assumes interrupts are blocked. 1755 */ 1756 void 1757 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1758 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1759 u_int8_t features) 1760 { 1761 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1762 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1763 1764 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1765 "sector=%d count=%d features=%d\n", 1766 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1767 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1768 1769 if (wdc->select) 1770 wdc->select(chp,drive); 1771 1772 /* Select drive, head, and addressing mode. */ 1773 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1774 WDSD_IBM | (drive << 4) | head); 1775 /* Load parameters into the wd_features register. */ 1776 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1777 features); 1778 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1779 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1780 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1781 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1782 0, cylin >> 8); 1783 1784 /* Send command. */ 1785 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1786 return; 1787 } 1788 1789 /* 1790 * Send a 48-bit addressing command. The drive should be ready. 1791 * Assumes interrupts are blocked. 1792 */ 1793 void 1794 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1795 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1796 { 1797 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1798 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1799 1800 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1801 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1802 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1803 chp->ch_channel, drive, command, blkno, count, features, device), 1804 DEBUG_FUNCS); 1805 1806 KASSERT(drive < wdc->wdc_maxdrives); 1807 1808 if (wdc->select) 1809 wdc->select(chp,drive); 1810 1811 /* Select drive, head, and addressing mode. */ 1812 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1813 (drive << 4) | device); 1814 1815 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1816 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1817 0, features); 1818 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1819 0, count); 1820 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1821 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1822 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1823 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1824 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1825 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1826 } else { 1827 /* previous */ 1828 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1829 0, features >> 8); 1830 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1831 0, count >> 8); 1832 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1833 0, blkno >> 24); 1834 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1835 0, blkno >> 32); 1836 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1837 0, blkno >> 40); 1838 1839 /* current */ 1840 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1841 0, features); 1842 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1843 0, count); 1844 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1845 0, blkno); 1846 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1847 0, blkno >> 8); 1848 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1849 0, blkno >> 16); 1850 } 1851 1852 /* Send command. */ 1853 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1854 return; 1855 } 1856 1857 /* 1858 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1859 * tested by the caller. 1860 */ 1861 void 1862 wdccommandshort(struct ata_channel *chp, int drive, int command) 1863 { 1864 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1865 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1866 1867 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1868 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1869 command), DEBUG_FUNCS); 1870 1871 if (wdc->select) 1872 wdc->select(chp,drive); 1873 1874 /* Select drive. */ 1875 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1876 WDSD_IBM | (drive << 4)); 1877 1878 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1879 } 1880 1881 static void 1882 __wdcerror(struct ata_channel *chp, const char *msg) 1883 { 1884 struct atac_softc *atac = chp->ch_atac; 1885 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1886 1887 if (xfer == NULL) 1888 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1889 chp->ch_channel, msg); 1890 else 1891 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1892 chp->ch_channel, xfer->c_drive, msg); 1893 } 1894 1895 /* 1896 * the bit bucket 1897 */ 1898 void 1899 wdcbit_bucket(struct ata_channel *chp, int size) 1900 { 1901 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1902 1903 for (; size >= 2; size -= 2) 1904 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1905 if (size) 1906 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1907 } 1908 1909 static void 1910 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1911 { 1912 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1913 1914 #ifndef __NO_STRICT_ALIGNMENT 1915 if ((uintptr_t)bf & 1) 1916 goto unaligned; 1917 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1918 goto unaligned; 1919 #endif 1920 1921 if (flags & ATA_DRIVE_NOSTREAM) { 1922 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1923 bus_space_read_multi_4(wdr->data32iot, 1924 wdr->data32ioh, 0, bf, len >> 2); 1925 bf = (char *)bf + (len & ~3); 1926 len &= 3; 1927 } 1928 if (len > 1) { 1929 bus_space_read_multi_2(wdr->cmd_iot, 1930 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1931 bf = (char *)bf + (len & ~1); 1932 len &= 1; 1933 } 1934 } else { 1935 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1936 bus_space_read_multi_stream_4(wdr->data32iot, 1937 wdr->data32ioh, 0, bf, len >> 2); 1938 bf = (char *)bf + (len & ~3); 1939 len &= 3; 1940 } 1941 if (len > 1) { 1942 bus_space_read_multi_stream_2(wdr->cmd_iot, 1943 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1944 bf = (char *)bf + (len & ~1); 1945 len &= 1; 1946 } 1947 } 1948 if (len) 1949 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1950 wdr->cmd_iohs[wd_data], 0); 1951 return; 1952 1953 #ifndef __NO_STRICT_ALIGNMENT 1954 unaligned: 1955 if (flags & ATA_DRIVE_NOSTREAM) { 1956 if (flags & ATA_DRIVE_CAP32) { 1957 while (len > 3) { 1958 uint32_t val; 1959 1960 val = bus_space_read_4(wdr->data32iot, 1961 wdr->data32ioh, 0); 1962 memcpy(bf, &val, 4); 1963 bf = (char *)bf + 4; 1964 len -= 4; 1965 } 1966 } 1967 while (len > 1) { 1968 uint16_t val; 1969 1970 val = bus_space_read_2(wdr->cmd_iot, 1971 wdr->cmd_iohs[wd_data], 0); 1972 memcpy(bf, &val, 2); 1973 bf = (char *)bf + 2; 1974 len -= 2; 1975 } 1976 } else { 1977 if (flags & ATA_DRIVE_CAP32) { 1978 while (len > 3) { 1979 uint32_t val; 1980 1981 val = bus_space_read_stream_4(wdr->data32iot, 1982 wdr->data32ioh, 0); 1983 memcpy(bf, &val, 4); 1984 bf = (char *)bf + 4; 1985 len -= 4; 1986 } 1987 } 1988 while (len > 1) { 1989 uint16_t val; 1990 1991 val = bus_space_read_stream_2(wdr->cmd_iot, 1992 wdr->cmd_iohs[wd_data], 0); 1993 memcpy(bf, &val, 2); 1994 bf = (char *)bf + 2; 1995 len -= 2; 1996 } 1997 } 1998 #endif 1999 } 2000 2001 static void 2002 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 2003 { 2004 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 2005 2006 #ifndef __NO_STRICT_ALIGNMENT 2007 if ((uintptr_t)bf & 1) 2008 goto unaligned; 2009 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 2010 goto unaligned; 2011 #endif 2012 2013 if (flags & ATA_DRIVE_NOSTREAM) { 2014 if (flags & ATA_DRIVE_CAP32) { 2015 bus_space_write_multi_4(wdr->data32iot, 2016 wdr->data32ioh, 0, bf, len >> 2); 2017 bf = (char *)bf + (len & ~3); 2018 len &= 3; 2019 } 2020 if (len) { 2021 bus_space_write_multi_2(wdr->cmd_iot, 2022 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2023 } 2024 } else { 2025 if (flags & ATA_DRIVE_CAP32) { 2026 bus_space_write_multi_stream_4(wdr->data32iot, 2027 wdr->data32ioh, 0, bf, len >> 2); 2028 bf = (char *)bf + (len & ~3); 2029 len &= 3; 2030 } 2031 if (len) { 2032 bus_space_write_multi_stream_2(wdr->cmd_iot, 2033 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2034 } 2035 } 2036 return; 2037 2038 #ifndef __NO_STRICT_ALIGNMENT 2039 unaligned: 2040 if (flags & ATA_DRIVE_NOSTREAM) { 2041 if (flags & ATA_DRIVE_CAP32) { 2042 while (len > 3) { 2043 uint32_t val; 2044 2045 memcpy(&val, bf, 4); 2046 bus_space_write_4(wdr->data32iot, 2047 wdr->data32ioh, 0, val); 2048 bf = (char *)bf + 4; 2049 len -= 4; 2050 } 2051 } 2052 while (len > 1) { 2053 uint16_t val; 2054 2055 memcpy(&val, bf, 2); 2056 bus_space_write_2(wdr->cmd_iot, 2057 wdr->cmd_iohs[wd_data], 0, val); 2058 bf = (char *)bf + 2; 2059 len -= 2; 2060 } 2061 } else { 2062 if (flags & ATA_DRIVE_CAP32) { 2063 while (len > 3) { 2064 uint32_t val; 2065 2066 memcpy(&val, bf, 4); 2067 bus_space_write_stream_4(wdr->data32iot, 2068 wdr->data32ioh, 0, val); 2069 bf = (char *)bf + 4; 2070 len -= 4; 2071 } 2072 } 2073 while (len > 1) { 2074 uint16_t val; 2075 2076 memcpy(&val, bf, 2); 2077 bus_space_write_stream_2(wdr->cmd_iot, 2078 wdr->cmd_iohs[wd_data], 0, val); 2079 bf = (char *)bf + 2; 2080 len -= 2; 2081 } 2082 } 2083 #endif 2084 } 2085