1 /* $NetBSD: adwlib.c,v 1.3 1999/02/23 20:18:16 dante Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante@mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-1998 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 */ 53 54 #include <sys/types.h> 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <vm/vm.h> 70 #include <vm/vm_param.h> 71 #include <vm/pmap.h> 72 73 #include <dev/ic/adwlib.h> 74 #include <dev/ic/adw.h> 75 #include <dev/ic/adwmcode.h> 76 77 78 /* Static Functions */ 79 80 static u_int16_t AdvGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 81 ADWEEP_CONFIG *)); 82 static u_int16_t AdvReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, 83 int)); 84 static void AdvWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); 85 static void AdvSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 86 ADWEEP_CONFIG *)); 87 static int AdvSendScsiCmd __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 88 static void AdvInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); 89 90 static void DvcSleepMilliSecond __P((ulong)); 91 static void DvcDelayMicroSecond __P((ulong)); 92 93 94 /* 95 * EEPROM Configuration. 96 * 97 * All drivers should use this structure to set the default EEPROM 98 * configuration. The BIOS now uses this structure when it is built. 99 * Additional structure information can be found in advlib.h where 100 * the structure is defined. 101 */ 102 static ADWEEP_CONFIG 103 Default_EEPROM_Config = { 104 ADW_EEPROM_BIOS_ENABLE, /* cfg_msw */ 105 0x0000, /* cfg_lsw */ 106 0xFFFF, /* disc_enable */ 107 0xFFFF, /* wdtr_able */ 108 0xFFFF, /* sdtr_able */ 109 0xFFFF, /* start_motor */ 110 0xFFFF, /* tagqng_able */ 111 0xFFFF, /* bios_scan */ 112 0, /* scam_tolerant */ 113 7, /* adapter_scsi_id */ 114 0, /* bios_boot_delay */ 115 3, /* scsi_reset_delay */ 116 0, /* bios_id_lun */ 117 0, /* termination */ 118 0, /* reserved1 */ 119 0xFFEF, /* bios_ctrl */ 120 0xFFFF, /* ultra_able */ 121 0, /* reserved2 */ 122 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ 123 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 124 0, /* dvc_cntl */ 125 0, /* bug_fix */ 126 0, /* serial_number_word1 */ 127 0, /* serial_number_word2 */ 128 0, /* serial_number_word3 */ 129 0, /* check_sum */ 130 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* oem_name[16] */ 131 0, /* dvc_err_code */ 132 0, /* adv_err_code */ 133 0, /* adv_err_addr */ 134 0, /* saved_dvc_err_code */ 135 0, /* saved_adv_err_code */ 136 0, /* saved_adv_err_addr */ 137 0 /* num_of_err */ 138 }; 139 140 /* 141 * Initialize the ASC3550. 142 * 143 * On failure set the ADW_SOFTC field 'err_code' and return ADW_ERROR. 144 * 145 * For a non-fatal error return a warning code. If there are no warnings 146 * then 0 is returned. 147 */ 148 int 149 AdvInitAsc3550Driver(sc) 150 ADW_SOFTC *sc; 151 { 152 bus_space_tag_t iot = sc->sc_iot; 153 bus_space_handle_t ioh = sc->sc_ioh; 154 u_int16_t warn_code; 155 u_int32_t sum; 156 int begin_addr; 157 int end_addr; 158 int code_sum; 159 int word; 160 int rql_addr; /* RISC Queue List address */ 161 int i; 162 u_int16_t scsi_cfg1; 163 u_int8_t biosmem[ASC_MC_BIOSLEN]; /* BIOS RISC Memory 164 * 0x40-0x8F */ 165 166 167 warn_code = 0; 168 169 /* 170 * Save the RISC memory BIOS region before writing the microcode. 171 * The BIOS may already be loaded and using its RISC LRAM region 172 * so its region must be saved and restored. 173 * 174 * Note: This code makes the assumption, which is currently true, 175 * that a chip reset does not clear RISC LRAM. 176 */ 177 for (i = 0; i < ASC_MC_BIOSLEN; i++) { 178 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_BIOSMEM + i, biosmem[i]); 179 } 180 181 /* 182 * Load the Microcode 183 * 184 * Write the microcode image to RISC memory starting at address 0. 185 */ 186 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 187 for (word = 0; word < adv_mcode_size; word += 2) { 188 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 189 *((u_int16_t *) (&adv_mcode[word]))); 190 } 191 192 /* 193 * Clear the rest of Condor's Internal RAM (8KB). 194 */ 195 for (; word < ADW_CONDOR_MEMSIZE; word += 2) { 196 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 197 } 198 199 /* 200 * Verify the microcode checksum. 201 */ 202 sum = 0; 203 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 204 for (word = 0; word < adv_mcode_size; word += 2) { 205 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 206 } 207 208 if (sum != adv_mcode_chksum) 209 return ASC_IERR_MCODE_CHKSUM; 210 211 /* 212 * Restore the RISC memory BIOS region. 213 */ 214 for (i = 0; i < ASC_MC_BIOSLEN; i++) { 215 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_BIOSMEM + i, biosmem[i]); 216 } 217 218 /* 219 * Calculate and write the microcode code checksum to the microcode 220 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 221 */ 222 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 223 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); 224 code_sum = 0; 225 for (word = begin_addr; word < end_addr; word += 2) { 226 code_sum += *((u_int16_t *) (&adv_mcode[word])); 227 } 228 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); 229 230 /* 231 * Read microcode version and date. 232 */ 233 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, sc->cfg.mcode_date); 234 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, sc->cfg.mcode_version); 235 236 /* 237 * Initialize microcode operating variables 238 */ 239 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_ADAPTER_SCSI_ID, 240 sc->chip_scsi_id); 241 242 /* 243 * If the PCI Configuration Command Register "Parity Error Response 244 * Control" Bit was clear (0), then set the microcode variable 245 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 246 * to ignore DMA parity errors. 247 */ 248 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 249 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 250 word |= CONTROL_FLAG_IGNORE_PERR; 251 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); 252 } 253 /* 254 * Set default microcode operating variables for WDTR, SDTR, and 255 * command tag queuing based on the EEPROM configuration values. 256 * 257 * These ADW_DVC_VAR fields and the microcode variables will be 258 * changed in AdvInquiryHandling() if it is found a device is 259 * incapable of a particular feature. 260 */ 261 262 /* 263 * Set the microcode ULTRA target mask from EEPROM value. The 264 * SDTR target mask overrides the ULTRA target mask in the 265 * microcode so it is safe to set this value without determining 266 * whether the device supports SDTR. 267 * 268 * Note: There is no way to know whether a device supports ULTRA 269 * speed without attempting a SDTR ULTRA speed negotiation with 270 * the device. The device will reject the speed if it does not 271 * support it by responding with an SDTR message containing a 272 * slower speed. 273 */ 274 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_ULTRA_ABLE, sc->ultra_able); 275 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); 276 277 278 /* 279 * Set SCSI_CFG0 Microcode Default Value. 280 * 281 * The microcode will set the SCSI_CFG0 register using this value 282 * after it is started below. 283 */ 284 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, 285 ADW_PARITY_EN | ADW_SEL_TMO_LONG | ADW_OUR_ID_EN | sc->chip_scsi_id); 286 287 /* 288 * Determine SCSI_CFG1 Microcode Default Value. 289 * 290 * The microcode will set the SCSI_CFG1 register using this value 291 * after it is started below. 292 */ 293 294 /* Read current SCSI_CFG1 Register value. */ 295 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 296 297 /* 298 * If all three connectors are in use, return an error. 299 */ 300 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 301 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 302 return ASC_IERR_ILLEGAL_CONNECTION; 303 } 304 /* 305 * If the internal narrow cable is reversed all of the SCSI_CTRL 306 * register signals will be set. Check for and return an error if 307 * this condition is found. 308 */ 309 if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == 310 0x3F07) { 311 312 return ASC_IERR_REVERSED_CABLE; 313 } 314 315 /* 316 * If this is a differential board and a single-ended device 317 * is attached to one of the connectors, return an error. 318 */ 319 if ((scsi_cfg1 & ADW_DIFF_MODE) && (scsi_cfg1 & ADW_DIFF_SENSE) == 0) 320 return ASC_IERR_SINGLE_END_DEVICE; 321 322 /* 323 * If automatic termination control is enabled, then set the 324 * termination value based on a table listed in advlib.h. 325 * 326 * If manual termination was specified with an EEPROM setting 327 * then 'termination' was set-up in AdvInitFromEEP() and 328 * is ready to be 'ored' into SCSI_CFG1. 329 */ 330 if (sc->cfg.termination == 0) { 331 /* 332 * The software always controls termination by setting 333 * ADW_TERM_CTL_SEL. 334 * If ADW_TERM_CTL_SEL were set to 0, the hardware would 335 * set termination. 336 */ 337 sc->cfg.termination |= ADW_TERM_CTL_SEL; 338 339 switch (scsi_cfg1 & ADW_CABLE_DETECT) { 340 /* ADW_TERM_CTL_H: on, ADW_TERM_CTL_L: on */ 341 case 0x3: 342 case 0x7: 343 case 0xB: 344 case 0xD: 345 case 0xE: 346 case 0xF: 347 sc->cfg.termination |= (ADW_TERM_CTL_H | 348 ADW_TERM_CTL_L); 349 break; 350 351 /* ADW_TERM_CTL_H: on, ADW_TERM_CTL_L: off */ 352 case 0x1: 353 case 0x5: 354 case 0x9: 355 case 0xA: 356 case 0xC: 357 sc->cfg.termination |= ADW_TERM_CTL_H; 358 break; 359 360 /* ADW_TERM_CTL_H: off, ADW_TERM_CTL_L: off */ 361 case 0x2: 362 case 0x6: 363 break; 364 } 365 } 366 /* 367 * Clear any set ADW_TERM_CTL_H and ADW_TERM_CTL_L bits. 368 */ 369 scsi_cfg1 &= ~ADW_TERM_CTL; 370 371 /* 372 * Invert the ADW_TERM_CTL_H and ADW_TERM_CTL_L bits and then 373 * set 'scsi_cfg1'. The ADW_TERM_POL bit does not need to be 374 * referenced, because the hardware internally inverts 375 * the Termination High and Low bits if ADW_TERM_POL is set. 376 */ 377 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~sc->cfg.termination & ADW_TERM_CTL)); 378 379 /* 380 * Set SCSI_CFG1 Microcode Default Value 381 * 382 * Set filter value and possibly modified termination control 383 * bits in the Microcode SCSI_CFG1 Register Value. 384 * 385 * The microcode will set the SCSI_CFG1 register using this value 386 * after it is started below. 387 */ 388 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, 389 ADW_FLTR_11_TO_20NS | scsi_cfg1); 390 391 /* 392 * Set SEL_MASK Microcode Default Value 393 * 394 * The microcode will set the SEL_MASK register using this value 395 * after it is started below. 396 */ 397 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, 398 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 399 400 /* 401 * Link all the RISC Queue Lists together in a doubly-linked 402 * NULL terminated list. 403 * 404 * Skip the NULL (0) queue which is not used. 405 */ 406 for (i = 1, rql_addr = ASC_MC_RISC_Q_LIST_BASE+ASC_MC_RISC_Q_LIST_SIZE; 407 i < ASC_MC_RISC_Q_TOTAL_CNT; 408 i++, rql_addr += ASC_MC_RISC_Q_LIST_SIZE) { 409 /* 410 * Set the current RISC Queue List's RQL_FWD and 411 * RQL_BWD pointers in a one word write and set 412 * the state (RQL_STATE) to free. 413 */ 414 ADW_WRITE_WORD_LRAM(iot, ioh, rql_addr, 415 ((i + 1) + ((i - 1) << 8))); 416 ADW_WRITE_BYTE_LRAM(iot, ioh, rql_addr + RQL_STATE, 417 ASC_MC_QS_FREE); 418 } 419 420 /* 421 * Set the Host and RISC Queue List pointers. 422 * 423 * Both sets of pointers are initialized with the same values: 424 * ASC_MC_RISC_Q_FIRST(0x01) and ASC_MC_RISC_Q_LAST (0xFF). 425 */ 426 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_READY, 427 ASC_MC_RISC_Q_FIRST); 428 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_DONE, 429 ASC_MC_RISC_Q_LAST); 430 431 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_RISC_NEXT_READY, 432 ASC_MC_RISC_Q_FIRST); 433 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_RISC_NEXT_DONE, 434 ASC_MC_RISC_Q_LAST); 435 436 /* 437 * Finally, set up the last RISC Queue List (255) with 438 * a NULL forward pointer. 439 */ 440 ADW_WRITE_WORD_LRAM(iot, ioh, rql_addr, 441 (ASC_MC_NULL_Q + ((i - 1) << 8))); 442 ADW_WRITE_BYTE_LRAM(iot, ioh, rql_addr + RQL_STATE, ASC_MC_QS_FREE); 443 444 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 445 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 446 447 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); 448 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 449 450 /* finally, finally, gentlemen, start your engine */ 451 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 452 453 return warn_code; 454 } 455 456 /* 457 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 458 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 459 * all of this is done. 460 * 461 * On failure set the ADW_DVC_VAR field 'err_code' and return ADW_ERROR. 462 * 463 * For a non-fatal error return a warning code. If there are no warnings 464 * then 0 is returned. 465 * 466 * Note: Chip is stopped on entry. 467 */ 468 int 469 AdvInitFromEEP(sc) 470 ADW_SOFTC *sc; 471 { 472 bus_space_tag_t iot = sc->sc_iot; 473 bus_space_handle_t ioh = sc->sc_ioh; 474 u_int16_t warn_code; 475 ADWEEP_CONFIG eep_config; 476 int eep_chksum, i; 477 478 479 warn_code = 0; 480 481 /* 482 * Read the board's EEPROM configuration. 483 * 484 * Set default values if a bad checksum is found. 485 */ 486 eep_chksum = AdvGetEEPConfig(iot, ioh, &eep_config); 487 488 if (eep_chksum != eep_config.check_sum) { 489 warn_code |= ASC_WARN_EEPROM_CHKSUM; 490 491 /* 492 * Set EEPROM default values. 493 */ 494 for (i = 0; i < sizeof(ADWEEP_CONFIG); i++) { 495 *((u_int8_t *) & eep_config + i) = 496 *((u_int8_t *) & Default_EEPROM_Config + i); 497 } 498 499 /* 500 * Assume the 6 byte board serial number that was read 501 * from EEPROM is correct even if the EEPROM checksum 502 * failed. 503 */ 504 eep_config.serial_number_word3 = 505 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); 506 eep_config.serial_number_word2 = 507 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); 508 eep_config.serial_number_word1 = 509 AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); 510 AdvSetEEPConfig(iot, ioh, &eep_config); 511 } 512 /* 513 * Set ADW_DVC_VAR and ADW_DVC_CFG variables from the 514 * EEPROM configuration that was read. 515 * 516 * This is the mapping of EEPROM fields to Adv Library fields. 517 */ 518 sc->wdtr_able = eep_config.wdtr_able; 519 sc->sdtr_able = eep_config.sdtr_able; 520 sc->ultra_able = eep_config.ultra_able; 521 sc->tagqng_able = eep_config.tagqng_able; 522 sc->cfg.disc_enable = eep_config.disc_enable; 523 sc->max_host_qng = eep_config.max_host_qng; 524 sc->max_dvc_qng = eep_config.max_dvc_qng; 525 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 526 sc->start_motor = eep_config.start_motor; 527 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 528 sc->cfg.bios_boot_wait = eep_config.bios_boot_delay; 529 sc->bios_ctrl = eep_config.bios_ctrl; 530 sc->no_scam = eep_config.scam_tolerant; 531 sc->cfg.serial1 = eep_config.serial_number_word1; 532 sc->cfg.serial2 = eep_config.serial_number_word2; 533 sc->cfg.serial3 = eep_config.serial_number_word3; 534 535 /* 536 * Set the host maximum queuing (max. 253, min. 16) and the per device 537 * maximum queuing (max. 63, min. 4). 538 */ 539 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 540 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 541 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 542 /* If the value is zero, assume it is uninitialized. */ 543 if (eep_config.max_host_qng == 0) { 544 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 545 } else { 546 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 547 } 548 } 549 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 550 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 551 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 552 /* If the value is zero, assume it is uninitialized. */ 553 if (eep_config.max_dvc_qng == 0) { 554 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 555 } else { 556 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 557 } 558 } 559 /* 560 * If 'max_dvc_qng' is greater than 'max_host_qng', then 561 * set 'max_dvc_qng' to 'max_host_qng'. 562 */ 563 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 564 eep_config.max_dvc_qng = eep_config.max_host_qng; 565 } 566 /* 567 * Set ADW_DVC_VAR 'max_host_qng' and ADW_DVC_CFG 'max_dvc_qng' 568 * values based on possibly adjusted EEPROM values. 569 */ 570 sc->max_host_qng = eep_config.max_host_qng; 571 sc->max_dvc_qng = eep_config.max_dvc_qng; 572 573 574 /* 575 * If the EEPROM 'termination' field is set to automatic (0), then set 576 * the ADW_DVC_CFG 'termination' field to automatic also. 577 * 578 * If the termination is specified with a non-zero 'termination' 579 * value check that a legal value is set and set the ADW_DVC_CFG 580 * 'termination' field appropriately. 581 */ 582 if (eep_config.termination == 0) { 583 sc->cfg.termination = 0; /* auto termination */ 584 } else { 585 /* Enable manual control with low off / high off. */ 586 if (eep_config.termination == 1) { 587 sc->cfg.termination = ADW_TERM_CTL_SEL; 588 589 /* Enable manual control with low off / high on. */ 590 } else if (eep_config.termination == 2) { 591 sc->cfg.termination = ADW_TERM_CTL_SEL | ADW_TERM_CTL_H; 592 593 /* Enable manual control with low on / high on. */ 594 } else if (eep_config.termination == 3) { 595 sc->cfg.termination = ADW_TERM_CTL_SEL | 596 ADW_TERM_CTL_H | ADW_TERM_CTL_L; 597 } else { 598 /* 599 * The EEPROM 'termination' field contains a bad value. 600 * Use automatic termination instead. 601 */ 602 sc->cfg.termination = 0; 603 warn_code |= ASC_WARN_EEPROM_TERMINATION; 604 } 605 } 606 607 return warn_code; 608 } 609 610 /* 611 * Read EEPROM configuration into the specified buffer. 612 * 613 * Return a checksum based on the EEPROM configuration read. 614 */ 615 static u_int16_t 616 AdvGetEEPConfig(iot, ioh, cfg_buf) 617 bus_space_tag_t iot; 618 bus_space_handle_t ioh; 619 ADWEEP_CONFIG *cfg_buf; 620 { 621 u_int16_t wval, chksum; 622 u_int16_t *wbuf; 623 int eep_addr; 624 625 wbuf = (u_int16_t *) cfg_buf; 626 chksum = 0; 627 628 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 629 eep_addr < ASC_EEP_DVC_CFG_END; 630 eep_addr++, wbuf++) { 631 wval = AdvReadEEPWord(iot, ioh, eep_addr); 632 chksum += wval; 633 *wbuf = wval; 634 } 635 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 636 wbuf++; 637 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 638 eep_addr < ASC_EEP_MAX_WORD_ADDR; 639 eep_addr++, wbuf++) { 640 *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); 641 } 642 return chksum; 643 } 644 645 /* 646 * Read the EEPROM from specified location 647 */ 648 static u_int16_t 649 AdvReadEEPWord(iot, ioh, eep_word_addr) 650 bus_space_tag_t iot; 651 bus_space_handle_t ioh; 652 int eep_word_addr; 653 { 654 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 655 ASC_EEP_CMD_READ | eep_word_addr); 656 AdvWaitEEPCmd(iot, iot); 657 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 658 } 659 660 /* 661 * Wait for EEPROM command to complete 662 */ 663 static void 664 AdvWaitEEPCmd(iot, ioh) 665 bus_space_tag_t iot; 666 bus_space_handle_t ioh; 667 { 668 DvcSleepMilliSecond(1); 669 670 for (;;) { 671 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 672 ASC_EEP_CMD_DONE) { 673 break; 674 } 675 DvcSleepMilliSecond(1); 676 } 677 678 return; 679 } 680 681 /* 682 * Write the EEPROM from 'cfg_buf'. 683 */ 684 static void 685 AdvSetEEPConfig(iot, ioh, cfg_buf) 686 bus_space_tag_t iot; 687 bus_space_handle_t ioh; 688 ADWEEP_CONFIG *cfg_buf; 689 { 690 u_int16_t *wbuf; 691 u_int16_t addr, chksum; 692 693 wbuf = (u_int16_t *) cfg_buf; 694 chksum = 0; 695 696 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 697 AdvWaitEEPCmd(iot, ioh); 698 699 /* 700 * Write EEPROM from word 0 to word 15 701 */ 702 for (addr = ASC_EEP_DVC_CFG_BEGIN; 703 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 704 chksum += *wbuf; 705 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 706 ADW_WRITE_WORD_REGISTER(iot, ioh, 707 IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 708 AdvWaitEEPCmd(iot, ioh); 709 DvcSleepMilliSecond(ASC_EEP_DELAY_MS); 710 } 711 712 /* 713 * Write EEPROM checksum at word 18 714 */ 715 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 716 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 717 ASC_EEP_CMD_WRITE | addr); 718 AdvWaitEEPCmd(iot, ioh); 719 wbuf++; /* skip over check_sum */ 720 721 /* 722 * Write EEPROM OEM name at words 19 to 26 723 */ 724 for (addr = ASC_EEP_DVC_CTL_BEGIN; 725 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 726 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 727 ADW_WRITE_WORD_REGISTER(iot, ioh, 728 IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 729 AdvWaitEEPCmd(iot, ioh); 730 } 731 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 732 ASC_EEP_CMD_WRITE_DISABLE); 733 AdvWaitEEPCmd(iot, ioh); 734 return; 735 } 736 737 /* 738 * This function resets the chip and SCSI bus 739 * 740 * It is up to the caller to add a delay to let the bus settle after 741 * calling this function. 742 * 743 * The SCSI_CFG0, SCSI_CFG1, and MEM_CFG registers are set-up in 744 * AdvInitAsc3550Driver(). Here when doing a write to one of these 745 * registers read first and then write. 746 * 747 * Note: A SCSI Bus Reset can not be done until after the EEPROM 748 * configuration is read to determine whether SCSI Bus Resets 749 * should be performed. 750 */ 751 void 752 AdvResetChip(iot, ioh) 753 bus_space_tag_t iot; 754 bus_space_handle_t ioh; 755 { 756 u_int16_t word; 757 u_int8_t byte; 758 759 760 /* 761 * Reset Chip. 762 */ 763 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 764 ADW_CTRL_REG_CMD_RESET); 765 DvcSleepMilliSecond(100); 766 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 767 ADW_CTRL_REG_CMD_WR_IO_REG); 768 769 /* 770 * Initialize Chip registers. 771 * 772 * Note: Don't remove the use of a temporary variable in the following 773 * code, otherwise the Microsoft C compiler will turn the following 774 * lines into a no-op. 775 */ 776 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_MEM_CFG); 777 byte |= RAM_SZ_8KB; 778 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_MEM_CFG, byte); 779 780 word = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 781 word &= ~BIG_ENDIAN; 782 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, word); 783 784 /* 785 * Setting the START_CTL_EMFU 3:2 bits sets a FIFO threshold 786 * of 128 bytes. This register is only accessible to the host. 787 */ 788 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 789 START_CTL_EMFU | READ_CMD_MRM); 790 } 791 792 /* 793 * Description: 794 * Send a SCSI request to the ASC3550 chip 795 * 796 * If there is no SG list for the request, set 'sg_entry_cnt' to 0. 797 * 798 * If 'sg_real_addr' is non-zero on entry, AscGetSGList() will not be 799 * called. It is assumed the caller has already initialized 'sg_real_addr'. 800 * 801 * Return: 802 * ADW_SUCCESS(1) - the request is in the mailbox 803 * ADW_BUSY(0) - total request count > 253, try later 804 * ADW_ERROR(-1) - invalid scsi request Q 805 */ 806 int 807 AdvExeScsiQueue(sc, scsiq) 808 ADW_SOFTC *sc; 809 ADW_SCSI_REQ_Q *scsiq; 810 { 811 return AdvSendScsiCmd(sc, scsiq); 812 } 813 814 /* 815 * Reset SCSI Bus and purge all outstanding requests. 816 * 817 * Return Value: 818 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 819 * 820 * Note: Should always return ADW_TRUE. 821 */ 822 int 823 AdvResetCCB(sc) 824 ADW_SOFTC *sc; 825 { 826 int status; 827 828 status = AdvSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET, 0L, 0); 829 830 AdvResetSCSIBus(sc); 831 832 return status; 833 } 834 835 /* 836 * Reset SCSI Bus and delay. 837 */ 838 void 839 AdvResetSCSIBus(sc) 840 ADW_SOFTC *sc; 841 { 842 bus_space_tag_t iot = sc->sc_iot; 843 bus_space_handle_t ioh = sc->sc_ioh; 844 u_int16_t scsi_ctrl; 845 846 847 848 /* 849 * The microcode currently sets the SCSI Bus Reset signal while 850 * handling the AdvSendIdleCmd() IDLE_CMD_SCSI_RESET command above. 851 * But the SCSI Bus Reset Hold Time in the uCode is not deterministic 852 * (it may in fact be for less than the SCSI Spec. minimum of 25 us). 853 * Therefore on return the Adv Library sets the SCSI Bus Reset signal 854 * for ASC_SCSI_RESET_HOLD_TIME_US, which is defined to be greater 855 * than 25 us. 856 */ 857 scsi_ctrl = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL); 858 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL, 859 scsi_ctrl | ADW_SCSI_CTRL_RSTOUT); 860 DvcDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 861 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL, 862 scsi_ctrl & ~ADW_SCSI_CTRL_RSTOUT); 863 864 DvcSleepMilliSecond((ulong) sc->scsi_reset_wait * 1000); 865 } 866 867 868 /* 869 * Adv Library Interrupt Service Routine 870 * 871 * This function is called by a driver's interrupt service routine. 872 * The function disables and re-enables interrupts. 873 * 874 * When a microcode idle command is completed, the ADW_DVC_VAR 875 * 'idle_cmd_done' field is set to ADW_TRUE. 876 * 877 * Note: AdvISR() can be called when interrupts are disabled or even 878 * when there is no hardware interrupt condition present. It will 879 * always check for completed idle commands and microcode requests. 880 * This is an important feature that shouldn't be changed because it 881 * allows commands to be completed from polling mode loops. 882 * 883 * Return: 884 * ADW_TRUE(1) - interrupt was pending 885 * ADW_FALSE(0) - no interrupt was pending 886 */ 887 int 888 AdvISR(sc) 889 ADW_SOFTC *sc; 890 { 891 bus_space_tag_t iot = sc->sc_iot; 892 bus_space_handle_t ioh = sc->sc_ioh; 893 u_int8_t int_stat; 894 u_int16_t next_done_loc, target_bit; 895 int completed_q; 896 ADW_SCSI_REQ_Q *scsiq; 897 ASC_REQ_SENSE *sense_data; 898 int ret; 899 900 901 ret = (ADW_IS_INT_PENDING(iot, ioh)) ? ADW_TRUE : ADW_FALSE; 902 903 /* Reading the register clears the interrupt. */ 904 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 905 906 if (int_stat & ADW_INTR_STATUS_INTRB) { 907 sc->idle_cmd_done = ADW_TRUE; 908 } 909 /* 910 * Notify the driver of a hardware detected SCSI Bus Reset. 911 */ 912 if (int_stat & ADW_INTR_STATUS_INTRC) { 913 if (sc->sbreset_callback) { 914 (*(ADW_SBRESET_CALLBACK) sc->sbreset_callback) (sc); 915 } 916 } 917 /* 918 * ASC_MC_HOST_NEXT_DONE (0x129) is actually the last completed RISC 919 * Queue List request. Its forward pointer (RQL_FWD) points to the 920 * current completed RISC Queue List request. 921 */ 922 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_DONE, next_done_loc); 923 next_done_loc = ASC_MC_RISC_Q_LIST_BASE + 924 (next_done_loc * ASC_MC_RISC_Q_LIST_SIZE) + RQL_FWD; 925 926 ADW_READ_BYTE_LRAM(iot, ioh, next_done_loc, completed_q); 927 928 /* Loop until all completed Q's are processed. */ 929 while (completed_q != ASC_MC_NULL_Q) { 930 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_DONE, 931 completed_q); 932 933 next_done_loc = ASC_MC_RISC_Q_LIST_BASE + 934 (completed_q * ASC_MC_RISC_Q_LIST_SIZE); 935 936 /* 937 * Read the ADW_SCSI_REQ_Q virtual address pointer from 938 * the RISC list entry. The microcode has changed the 939 * ADW_SCSI_REQ_Q physical address to its virtual address. 940 * 941 * Refer to comments at the end of AdvSendScsiCmd() for 942 * more information on the RISC list structure. 943 */ 944 { 945 ushort lsw, msw; 946 ADW_READ_WORD_LRAM(iot, ioh, 947 next_done_loc + RQL_PHYADDR, lsw); 948 ADW_READ_WORD_LRAM(iot, ioh, 949 next_done_loc + RQL_PHYADDR + 2, msw); 950 951 /* 952 * Here we retrive the virtual address of the 953 * ADW_SCSI_REQ_Q structure. This is accomplished 954 * retriving first the ccb physical address (which 955 * we passed to the board in AdvSendScsiCmd), 956 * translating then to a virtual address, and 957 * retrivieng the the ADW_SCSI_REQ_Q pointer stored 958 * into the ccb structure. 959 */ 960 scsiq = &adw_ccb_phys_kv(sc, 961 (((u_int32_t) msw << 16) | lsw))->scsiq; 962 } 963 964 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 965 966 /* 967 * Clear request microcode control flag. 968 */ 969 scsiq->cntl = 0; 970 971 /* 972 * Check Condition handling 973 */ 974 if ((scsiq->done_status == QD_WITH_ERROR) && 975 (scsiq->scsi_status == SS_CHK_CONDITION) && 976 (sense_data = (ASC_REQ_SENSE *) scsiq->vsense_addr) != 0 && 977 (scsiq->orig_sense_len - scsiq->sense_len) >= 978 ASC_MIN_SENSE_LEN) { 979 /* 980 * Command returned with a check condition and valid 981 * sense data. 982 */ 983 } 984 /* 985 * If the command that completed was a SCSI INQUIRY and 986 * LUN 0 was sent the command, then process the INQUIRY 987 * command information for the device. 988 */ 989 else if (scsiq->done_status == QD_NO_ERROR && 990 scsiq->cdb[0] == INQUIRY && 991 scsiq->target_lun == 0) { 992 AdvInquiryHandling(sc, scsiq); 993 } 994 /* Change the RISC Queue List state to free. */ 995 ADW_WRITE_BYTE_LRAM(iot, ioh, 996 next_done_loc + RQL_STATE, ASC_MC_QS_FREE); 997 998 /* Get the RISC Queue List forward pointer. */ 999 ADW_READ_BYTE_LRAM(iot, ioh, 1000 next_done_loc + RQL_FWD, completed_q); 1001 1002 /* 1003 * Notify the driver of the completed request by passing 1004 * the ADW_SCSI_REQ_Q pointer to its callback function. 1005 */ 1006 sc->cur_host_qng--; 1007 scsiq->a_flag |= ADW_SCSIQ_DONE; 1008 (*(ADW_ISR_CALLBACK) sc->isr_callback) (sc, scsiq); 1009 /* 1010 * Note: After the driver callback function is called, 'scsiq' 1011 * can no longer be referenced. 1012 * 1013 * Fall through and continue processing other completed 1014 * requests... 1015 */ 1016 } 1017 return ret; 1018 } 1019 1020 /* 1021 * Send an idle command to the chip and wait for completion. 1022 * 1023 * Interrupts do not have to be enabled on entry. 1024 * 1025 * Return Values: 1026 * ADW_TRUE - command completed successfully 1027 * ADW_FALSE - command failed 1028 */ 1029 int 1030 AdvSendIdleCmd(sc, idle_cmd, idle_cmd_parameter, flags) 1031 ADW_SOFTC *sc; 1032 u_int16_t idle_cmd; 1033 u_int32_t idle_cmd_parameter; 1034 int flags; 1035 { 1036 bus_space_tag_t iot = sc->sc_iot; 1037 bus_space_handle_t ioh = sc->sc_ioh; 1038 u_int32_t i; 1039 int ret; 1040 1041 sc->idle_cmd_done = 0; 1042 1043 /* 1044 * Write the idle command value after the idle command parameter 1045 * has been written to avoid a race condition. If the order is not 1046 * followed, the microcode may process the idle command before the 1047 * parameters have been written to LRAM. 1048 */ 1049 ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IDLE_PARA_STAT, 1050 idle_cmd_parameter); 1051 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD, idle_cmd); 1052 1053 /* 1054 * If the 'flags' argument contains the ADW_NOWAIT flag, then 1055 * return with success. 1056 */ 1057 if (flags & ADW_NOWAIT) 1058 return ADW_TRUE; 1059 1060 for (i = 0; i < SCSI_WAIT_10_SEC * SCSI_MS_PER_SEC; i++) { 1061 /* 1062 * 'idle_cmd_done' is set by AdvISR(). 1063 */ 1064 if (sc->idle_cmd_done) 1065 break; 1066 1067 DvcSleepMilliSecond(1); 1068 1069 /* 1070 * If interrupts were disabled on entry to AdvSendIdleCmd(), 1071 * then they will still be disabled here. Call AdvISR() to 1072 * check for the idle command completion. 1073 */ 1074 (void) AdvISR(sc); 1075 } 1076 1077 if (sc->idle_cmd_done == ADW_FALSE) { 1078 return ADW_FALSE; 1079 } else { 1080 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_IDLE_PARA_STAT, ret); 1081 return ret; 1082 } 1083 } 1084 1085 /* 1086 * Send the SCSI request block to the adapter 1087 * 1088 * Each of the 255 Adv Library/Microcode RISC Lists or mailboxes has the 1089 * following structure: 1090 * 1091 * 0: RQL_FWD - RISC list forward pointer (1 byte) 1092 * 1: RQL_BWD - RISC list backward pointer (1 byte) 1093 * 2: RQL_STATE - RISC list state byte - free, ready, done, aborted (1 byte) 1094 * 3: RQL_TID - request target id (1 byte) 1095 * 4: RQL_PHYADDR - ADW_SCSI_REQ_Q physical pointer (4 bytes) 1096 * 1097 * Return: 1098 * ADW_SUCCESS(1) - the request is in the mailbox 1099 * ADW_BUSY(0) - total request count > 253, try later 1100 */ 1101 static int 1102 AdvSendScsiCmd(sc, scsiq) 1103 ADW_SOFTC *sc; 1104 ADW_SCSI_REQ_Q *scsiq; 1105 { 1106 bus_space_tag_t iot = sc->sc_iot; 1107 bus_space_handle_t ioh = sc->sc_ioh; 1108 ADW_CCB *ccb; 1109 u_int16_t next_ready_loc; 1110 u_int8_t next_ready_loc_fwd; 1111 long req_size; 1112 u_int32_t q_phy_addr; 1113 1114 1115 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1116 1117 if (sc->cur_host_qng >= sc->max_host_qng) { 1118 return ADW_BUSY; 1119 } else { 1120 sc->cur_host_qng++; 1121 } 1122 1123 /* 1124 * Clear the ADW_SCSI_REQ_Q done flag. 1125 */ 1126 scsiq->a_flag &= ~ADW_SCSIQ_DONE; 1127 1128 /* 1129 * Save the original sense buffer length. 1130 * 1131 * After the request completes 'sense_len' will be set to the residual 1132 * byte count of the Auto-Request Sense if a command returns CHECK 1133 * CONDITION and the Sense Data is valid indicated by 'host_status' not 1134 * being set to QHSTA_M_AUTO_REQ_SENSE_FAIL. To determine the valid 1135 * Sense Data Length subtract 'sense_len' from 'orig_sense_len'. 1136 */ 1137 scsiq->orig_sense_len = scsiq->sense_len; 1138 1139 ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_READY, next_ready_loc); 1140 next_ready_loc = ASC_MC_RISC_Q_LIST_BASE + 1141 (next_ready_loc * ASC_MC_RISC_Q_LIST_SIZE); 1142 1143 /* 1144 * Write the physical address of the Q to the mailbox. 1145 * We need to skip the first four bytes, because the microcode 1146 * uses them internally for linking Q's together. 1147 */ 1148 req_size = sizeof(ADW_SCSI_REQ_Q); 1149 q_phy_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1150 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1151 1152 /* 1153 * The "scsiq" pointer must be passed to the board so we can retrive it 1154 * during the interrupt condition: inside the Adv_ISR() function. 1155 * It should contain the virtual address of ADW_SCSI_REQ_Q structure, 1156 * but actually, to make it works under 64bits architecure it contains 1157 * the physical address of ccb (ADW_CCB). 1158 */ 1159 scsiq->ccb_scsiq_ptr = scsiq->ccb_ptr; 1160 1161 /* 1162 * The RISC list structure, which 'next_ready_loc' is a pointer 1163 * to in microcode LRAM, has the format detailed in the comment 1164 * header for this function. 1165 * 1166 * Write the ADW_SCSI_REQ_Q physical pointer to 1167 * 'next_ready_loc' request. 1168 */ 1169 ADW_WRITE_DWORD_LRAM(iot, ioh, next_ready_loc + RQL_PHYADDR, 1170 q_phy_addr); 1171 1172 /* Write target_id to 'next_ready_loc' request. */ 1173 ADW_WRITE_BYTE_LRAM(iot, ioh, next_ready_loc + RQL_TID, 1174 scsiq->target_id); 1175 1176 /* 1177 * Set the ASC_MC_HOST_NEXT_READY (0x128) microcode variable to 1178 * the 'next_ready_loc' request forward pointer. 1179 * 1180 * Do this *before* changing the 'next_ready_loc' queue to QS_READY. 1181 * After the state is changed to QS_READY 'RQL_FWD' will be changed 1182 * by the microcode. 1183 * 1184 * NOTE: The temporary variable 'next_ready_loc_fwd' is required to 1185 * prevent some compilers from optimizing out 'AdvReadByteLram()' if 1186 * it were used as the 3rd argument to 'AdvWriteByteLram()'. 1187 */ 1188 ADW_READ_BYTE_LRAM(iot, ioh, next_ready_loc + RQL_FWD, 1189 next_ready_loc_fwd); 1190 ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_HOST_NEXT_READY, 1191 next_ready_loc_fwd); 1192 1193 /* 1194 * Change the state of 'next_ready_loc' request from QS_FREE to 1195 * QS_READY which will cause the microcode to pick it up and 1196 * execute it. 1197 * 1198 * Can't reference 'next_ready_loc' after changing the request 1199 * state to QS_READY. The microcode now owns the request. 1200 */ 1201 ADW_WRITE_BYTE_LRAM(iot, ioh, next_ready_loc + RQL_STATE, 1202 ASC_MC_QS_READY); 1203 1204 return ADW_SUCCESS; 1205 } 1206 1207 /* 1208 * Inquiry Information Byte 7 Handling 1209 * 1210 * Handle SCSI Inquiry Command information for a device by setting 1211 * microcode operating variables that affect WDTR, SDTR, and Tag 1212 * Queuing. 1213 */ 1214 static void 1215 AdvInquiryHandling(sc, scsiq) 1216 ADW_SOFTC *sc; 1217 ADW_SCSI_REQ_Q *scsiq; 1218 { 1219 bus_space_tag_t iot = sc->sc_iot; 1220 bus_space_handle_t ioh = sc->sc_ioh; 1221 ASC_SCSI_INQUIRY *inq; 1222 u_int16_t cfg_word; 1223 u_int16_t tidmask; 1224 u_int8_t tid; 1225 1226 /* 1227 * AdvInquiryHandling() requires up to INQUIRY information Byte 7 1228 * to be available. 1229 * 1230 * If less than 8 bytes of INQUIRY information were requested or less 1231 * than 8 bytes were transferred, then return. cdb[4] is the request 1232 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 1233 * microcode to the transfer residual count. 1234 */ 1235 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 1236 return; 1237 } 1238 tid = scsiq->target_id; 1239 inq = (ASC_SCSI_INQUIRY *) scsiq->vdata_addr; 1240 1241 /* 1242 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 1243 */ 1244 if (inq->byte3.rsp_data_fmt < 2 && inq->byte2.ansi_apr_ver < 2) { 1245 return; 1246 } else { 1247 /* 1248 * INQUIRY Byte 7 Handling 1249 * 1250 * Use a device's INQUIRY byte 7 to determine whether it 1251 * supports WDTR, SDTR, and Tag Queuing. If the feature 1252 * is enabled in the EEPROM and the device supports the 1253 * feature, then enable it in the microcode. 1254 */ 1255 1256 tidmask = ADW_TID_TO_TIDMASK(tid); 1257 /* 1258 * Wide Transfers 1259 * 1260 * If the EEPROM enabled WDTR for the device and the device 1261 * supports wide bus (16 bit) transfers, then turn on the 1262 * device's 'wdtr_able' bit and write the new value to the 1263 * microcode. 1264 */ 1265 if ((sc->wdtr_able & tidmask) && inq->byte7.WBus16) { 1266 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 1267 cfg_word); 1268 if ((cfg_word & tidmask) == 0) { 1269 cfg_word |= tidmask; 1270 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, 1271 cfg_word); 1272 1273 /* 1274 * Clear the microcode "WDTR negotiation" done 1275 * indicator for the target to cause it 1276 * to negotiate with the new setting set above. 1277 */ 1278 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, 1279 cfg_word); 1280 cfg_word &= ~tidmask; 1281 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, 1282 cfg_word); 1283 } 1284 } 1285 /* 1286 * Synchronous Transfers 1287 * 1288 * If the EEPROM enabled SDTR for the device and the device 1289 * supports synchronous transfers, then turn on the device's 1290 * 'sdtr_able' bit. Write the new value to the microcode. 1291 */ 1292 if ((sc->sdtr_able & tidmask) && inq->byte7.Sync) { 1293 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 1294 cfg_word); 1295 if ((cfg_word & tidmask) == 0) { 1296 cfg_word |= tidmask; 1297 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, 1298 cfg_word); 1299 1300 /* 1301 * Clear the microcode "SDTR negotiation" done 1302 * indicator for the target to cause it 1303 * to negotiate with the new setting set above. 1304 */ 1305 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 1306 cfg_word); 1307 cfg_word &= ~tidmask; 1308 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, 1309 cfg_word); 1310 } 1311 } 1312 /* 1313 * If the EEPROM enabled Tag Queuing for device and the 1314 * device supports Tag Queuing, then turn on the device's 1315 * 'tagqng_enable' bit in the microcode and set the microcode 1316 * maximum command count to the ADW_DVC_VAR 'max_dvc_qng' 1317 * value. 1318 * 1319 * Tag Queuing is disabled for the BIOS which runs in polled 1320 * mode and would see no benefit from Tag Queuing. Also by 1321 * disabling Tag Queuing in the BIOS devices with Tag Queuing 1322 * bugs will at least work with the BIOS. 1323 */ 1324 if ((sc->tagqng_able & tidmask) && inq->byte7.CmdQue) { 1325 ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 1326 cfg_word); 1327 cfg_word |= tidmask; 1328 ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, 1329 cfg_word); 1330 ADW_WRITE_BYTE_LRAM(iot, ioh, 1331 ASC_MC_NUMBER_OF_MAX_CMD + tid, 1332 sc->max_dvc_qng); 1333 } 1334 } 1335 } 1336 1337 static void 1338 DvcSleepMilliSecond(n) 1339 ulong n; 1340 { 1341 1342 DELAY(n * 1000); 1343 } 1344 1345 static void 1346 DvcDelayMicroSecond(n) 1347 ulong n; 1348 { 1349 1350 DELAY(n); 1351 } 1352