1 /* $NetBSD: advlib.c,v 1.8 1999/02/25 20:21:33 dante Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante@mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Ported from: 41 */ 42 /* 43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 44 * 45 * Copyright (c) 1995-1998 Advanced System Products, Inc. 46 * All Rights Reserved. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that redistributions of source 50 * code retain the above copyright notice and this comment without 51 * modification. 52 * 53 */ 54 55 #include <sys/types.h> 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/queue.h> 61 #include <sys/device.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/scsipi/scsi_all.h> 67 #include <dev/scsipi/scsipi_all.h> 68 #include <dev/scsipi/scsiconf.h> 69 70 #include <vm/vm.h> 71 #include <vm/vm_param.h> 72 #include <vm/pmap.h> 73 74 #include <dev/ic/advlib.h> 75 #include <dev/ic/adv.h> 76 #include <dev/ic/advmcode.h> 77 78 79 /* #define ASC_DEBUG */ 80 81 /******************************************************************************/ 82 /* Static functions */ 83 /******************************************************************************/ 84 85 /* Initializzation routines */ 86 static u_int32_t AscLoadMicroCode __P((bus_space_tag_t, bus_space_handle_t, 87 u_int16_t, u_int16_t *, u_int16_t)); 88 static void AscInitLram __P((ASC_SOFTC *)); 89 static void AscInitQLinkVar __P((ASC_SOFTC *)); 90 static int AscResetChipAndScsiBus __P((bus_space_tag_t, bus_space_handle_t)); 91 static u_int16_t AscGetChipBusType __P((bus_space_tag_t, bus_space_handle_t)); 92 93 /* Chip register routines */ 94 static void AscSetBank __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); 95 96 /* RISC Chip routines */ 97 static int AscStartChip __P((bus_space_tag_t, bus_space_handle_t)); 98 static int AscStopChip __P((bus_space_tag_t, bus_space_handle_t)); 99 static u_int8_t AscSetChipScsiID __P((bus_space_tag_t, bus_space_handle_t, 100 u_int8_t)); 101 static u_int8_t AscGetChipScsiCtrl __P((bus_space_tag_t, bus_space_handle_t)); 102 static u_int8_t AscGetChipVersion __P((bus_space_tag_t, bus_space_handle_t, 103 u_int16_t)); 104 static int AscSetRunChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 105 u_int8_t, u_int8_t)); 106 static int AscSetChipSynRegAtID __P((bus_space_tag_t, bus_space_handle_t, 107 u_int8_t, u_int8_t)); 108 static int AscHostReqRiscHalt __P((bus_space_tag_t, bus_space_handle_t)); 109 static int AscIsChipHalted __P((bus_space_tag_t, bus_space_handle_t)); 110 static void AscSetChipIH __P((bus_space_tag_t, bus_space_handle_t, u_int16_t)); 111 112 /* Lram routines */ 113 static u_int8_t AscReadLramByte __P((bus_space_tag_t, bus_space_handle_t, 114 u_int16_t)); 115 static void AscWriteLramByte __P((bus_space_tag_t, bus_space_handle_t, 116 u_int16_t, u_int8_t)); 117 static u_int16_t AscReadLramWord __P((bus_space_tag_t, bus_space_handle_t, 118 u_int16_t)); 119 static void AscWriteLramWord __P((bus_space_tag_t, bus_space_handle_t, 120 u_int16_t, u_int16_t)); 121 static u_int32_t AscReadLramDWord __P((bus_space_tag_t, bus_space_handle_t, 122 u_int16_t)); 123 static void AscWriteLramDWord __P((bus_space_tag_t, bus_space_handle_t, 124 u_int16_t, u_int32_t)); 125 static void AscMemWordSetLram __P((bus_space_tag_t, bus_space_handle_t, 126 u_int16_t, u_int16_t, int)); 127 static void AscMemWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 128 u_int16_t, u_int16_t *, int)); 129 static void AscMemWordCopyFromLram __P((bus_space_tag_t, bus_space_handle_t, 130 u_int16_t, u_int16_t *, int)); 131 static void AscMemDWordCopyToLram __P((bus_space_tag_t, bus_space_handle_t, 132 u_int16_t, u_int32_t *, int)); 133 static u_int32_t AscMemSumLramWord __P((bus_space_tag_t, bus_space_handle_t, 134 u_int16_t, int)); 135 static int AscTestExternalLram __P((bus_space_tag_t, bus_space_handle_t)); 136 137 /* MicroCode routines */ 138 static u_int16_t AscInitMicroCodeVar __P((ASC_SOFTC *)); 139 static u_int32_t AscGetOnePhyAddr __P((ASC_SOFTC *, u_int8_t *, u_int32_t)); 140 static u_int32_t AscGetSGList __P((ASC_SOFTC *, u_int8_t *, u_int32_t, 141 ASC_SG_HEAD *)); 142 143 /* EEProm routines */ 144 static int AscWriteEEPCmdReg __P((bus_space_tag_t, bus_space_handle_t, 145 u_int8_t)); 146 static int AscWriteEEPDataReg __P((bus_space_tag_t, bus_space_handle_t, 147 u_int16_t)); 148 static void AscWaitEEPRead __P((void)); 149 static void AscWaitEEPWrite __P((void)); 150 static u_int16_t AscReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, 151 u_int8_t)); 152 static u_int16_t AscWriteEEPWord __P((bus_space_tag_t, bus_space_handle_t, 153 u_int8_t, u_int16_t)); 154 static u_int16_t AscGetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 155 ASCEEP_CONFIG *, u_int16_t)); 156 static int AscSetEEPConfig __P((bus_space_tag_t, bus_space_handle_t, 157 ASCEEP_CONFIG *, u_int16_t)); 158 static int AscSetEEPConfigOnce __P((bus_space_tag_t, bus_space_handle_t, 159 ASCEEP_CONFIG *, u_int16_t)); 160 #ifdef ASC_DEBUG 161 static void AscPrintEEPConfig __P((ASCEEP_CONFIG *, u_int16_t)); 162 #endif 163 164 /* Interrupt routines */ 165 static void AscIsrChipHalted __P((ASC_SOFTC *)); 166 static int AscIsrQDone __P((ASC_SOFTC *)); 167 static int AscWaitTixISRDone __P((ASC_SOFTC *, u_int8_t)); 168 static int AscWaitISRDone __P((ASC_SOFTC *)); 169 static u_int8_t _AscCopyLramScsiDoneQ __P((bus_space_tag_t, bus_space_handle_t, 170 u_int16_t, ASC_QDONE_INFO *, 171 u_int32_t)); 172 static void AscGetQDoneInfo __P((bus_space_tag_t, bus_space_handle_t, u_int16_t, 173 ASC_QDONE_INFO *)); 174 static void AscToggleIRQAct __P((bus_space_tag_t, bus_space_handle_t)); 175 static void AscDisableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 176 static void AscEnableInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 177 static u_int8_t AscGetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 178 u_int16_t)); 179 static u_int8_t AscSetChipIRQ __P((bus_space_tag_t, bus_space_handle_t, 180 u_int8_t, u_int16_t)); 181 static void AscAckInterrupt __P((bus_space_tag_t, bus_space_handle_t)); 182 static u_int32_t AscGetMaxDmaCount __P((u_int16_t)); 183 static u_int16_t AscGetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t)); 184 static u_int16_t AscSetIsaDmaChannel __P((bus_space_tag_t, bus_space_handle_t, 185 u_int16_t)); 186 static u_int8_t AscGetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t)); 187 static u_int8_t AscSetIsaDmaSpeed __P((bus_space_tag_t, bus_space_handle_t, 188 u_int8_t)); 189 190 /* Messages routines */ 191 static void AscHandleExtMsgIn __P((ASC_SOFTC *, u_int16_t, u_int8_t, 192 ASC_SCSI_BIT_ID_TYPE, int, u_int8_t)); 193 static u_int8_t AscMsgOutSDTR __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 194 195 /* SDTR routines */ 196 static void AscSetChipSDTR __P((bus_space_tag_t, bus_space_handle_t, 197 u_int8_t, u_int8_t)); 198 static u_int8_t AscCalSDTRData __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 199 static u_int8_t AscGetSynPeriodIndex __P((ASC_SOFTC *, u_int8_t)); 200 201 /* Queue routines */ 202 static int AscSendScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 203 static int AscSgListToQueue __P((int)); 204 static u_int AscGetNumOfFreeQueue __P((ASC_SOFTC *, u_int8_t, u_int8_t)); 205 static int AscPutReadyQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 206 static void AscPutSCSIQ __P((bus_space_tag_t, bus_space_handle_t, 207 u_int16_t, ASC_SCSI_Q *)); 208 static int AscPutReadySgListQueue __P((ASC_SOFTC *, ASC_SCSI_Q *, u_int8_t)); 209 static u_int8_t AscAllocFreeQueue __P((bus_space_tag_t, bus_space_handle_t, 210 u_int8_t)); 211 static u_int8_t AscAllocMultipleFreeQueue __P((bus_space_tag_t, 212 bus_space_handle_t, 213 u_int8_t, u_int8_t)); 214 static int AscStopQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 215 static void AscStartQueueExe __P((bus_space_tag_t, bus_space_handle_t)); 216 static void AscCleanUpBusyQueue __P((bus_space_tag_t, bus_space_handle_t)); 217 static int _AscWaitQDone __P((bus_space_tag_t, bus_space_handle_t, 218 ASC_SCSI_Q *)); 219 static int AscCleanUpDiscQueue __P((bus_space_tag_t, bus_space_handle_t)); 220 221 /* Abort and Reset CCB routines */ 222 static int AscRiscHaltedAbortCCB __P((ASC_SOFTC *, ADV_CCB *)); 223 static int AscRiscHaltedAbortTIX __P((ASC_SOFTC *, u_int8_t)); 224 225 /* Error Handling routines */ 226 static int AscSetLibErrorCode __P((ASC_SOFTC *, u_int16_t)); 227 228 /* Handle bugged borads routines */ 229 static int AscTagQueuingSafe __P((ASC_SCSI_INQUIRY *)); 230 static void AscAsyncFix __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *)); 231 232 /* Miscellaneous routines */ 233 static int AscCompareString __P((u_char *, u_char *, int)); 234 235 /* Device oriented routines */ 236 static int DvcEnterCritical __P((void)); 237 static void DvcLeaveCritical __P((int)); 238 static void DvcSleepMilliSecond __P((u_int32_t)); 239 //static void DvcDelayMicroSecond __P((u_int32_t)); 240 static void DvcDelayNanoSecond __P((u_int32_t)); 241 242 243 /******************************************************************************/ 244 /* Initializzation routines */ 245 /******************************************************************************/ 246 247 /* 248 * This function perform the following steps: 249 * - initialize ASC_SOFTC structure with defaults values. 250 * - inquire board registers to know what kind of board it is. 251 * - keep track of bugged borads. 252 */ 253 void 254 AscInitASC_SOFTC(sc) 255 ASC_SOFTC *sc; 256 { 257 bus_space_tag_t iot = sc->sc_iot; 258 bus_space_handle_t ioh = sc->sc_ioh; 259 int i; 260 u_int8_t chip_version; 261 262 263 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 264 ASC_SET_CHIP_STATUS(iot, ioh, 0); 265 266 sc->bug_fix_cntl = 0; 267 sc->pci_fix_asyn_xfer = 0; 268 sc->pci_fix_asyn_xfer_always = 0; 269 sc->sdtr_done = 0; 270 sc->cur_total_qng = 0; 271 sc->last_q_shortage = 0; 272 sc->use_tagged_qng = 0; 273 sc->unit_not_ready = 0; 274 sc->queue_full_or_busy = 0; 275 sc->host_init_sdtr_index = 0; 276 sc->can_tagged_qng = 0; 277 sc->cmd_qng_enabled = 0; 278 sc->dvc_cntl = ASC_DEF_DVC_CNTL; 279 sc->init_sdtr = 0; 280 sc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 281 sc->scsi_reset_wait = 3; 282 sc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 283 sc->max_dma_count = AscGetMaxDmaCount(sc->bus_type); 284 sc->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 285 sc->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 286 sc->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 287 sc->lib_serial_no = ASC_LIB_SERIAL_NUMBER; 288 sc->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | ASC_LIB_VERSION_MINOR; 289 chip_version = AscGetChipVersion(iot, ioh, sc->bus_type); 290 sc->chip_version = chip_version; 291 if ((sc->bus_type & ASC_IS_PCI) && 292 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 293 sc->bus_type = ASC_IS_PCI_ULTRA; 294 sc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 295 sc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; 296 sc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; 297 sc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; 298 sc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; 299 sc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; 300 sc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; 301 sc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; 302 sc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; 303 sc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; 304 sc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; 305 sc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; 306 sc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; 307 sc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; 308 sc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; 309 sc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; 310 sc->max_sdtr_index = 15; 311 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) 312 ASC_SET_EXTRA_CONTROL(iot, ioh, 313 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 314 else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) 315 ASC_SET_EXTRA_CONTROL(iot, ioh, 316 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER)); 317 } else { 318 sc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 319 sc->sdtr_period_tbl[1] = SYN_XFER_NS_1; 320 sc->sdtr_period_tbl[2] = SYN_XFER_NS_2; 321 sc->sdtr_period_tbl[3] = SYN_XFER_NS_3; 322 sc->sdtr_period_tbl[4] = SYN_XFER_NS_4; 323 sc->sdtr_period_tbl[5] = SYN_XFER_NS_5; 324 sc->sdtr_period_tbl[6] = SYN_XFER_NS_6; 325 sc->sdtr_period_tbl[7] = SYN_XFER_NS_7; 326 sc->max_sdtr_index = 7; 327 } 328 329 if (sc->bus_type == ASC_IS_PCI) 330 ASC_SET_EXTRA_CONTROL(iot, ioh, 331 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 332 333 sc->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 334 if (AscGetChipBusType(iot, ioh) == ASC_IS_ISAPNP) { 335 ASC_SET_CHIP_IFC(iot, ioh, ASC_IFC_INIT_DEFAULT); 336 sc->bus_type = ASC_IS_ISAPNP; 337 } 338 if ((sc->bus_type & ASC_IS_ISA) != 0) 339 sc->isa_dma_channel = AscGetIsaDmaChannel(iot, ioh); 340 341 for (i = 0; i <= ASC_MAX_TID; i++) { 342 sc->cur_dvc_qng[i] = 0; 343 sc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 344 sc->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 345 } 346 } 347 348 349 /* 350 * This function initialize some ASC_SOFTC fields with values read from 351 * on-board EEProm. 352 */ 353 u_int16_t 354 AscInitFromEEP(sc) 355 ASC_SOFTC *sc; 356 { 357 bus_space_tag_t iot = sc->sc_iot; 358 bus_space_handle_t ioh = sc->sc_ioh; 359 ASCEEP_CONFIG eep_config_buf; 360 ASCEEP_CONFIG *eep_config; 361 u_int16_t chksum; 362 u_int16_t warn_code; 363 u_int16_t cfg_msw, cfg_lsw; 364 int i; 365 int write_eep = 0; 366 367 368 warn_code = 0; 369 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0x00FE); 370 AscStopQueueExe(iot, ioh); 371 if ((AscStopChip(iot, ioh) == FALSE) || 372 (AscGetChipScsiCtrl(iot, ioh) != 0)) { 373 AscResetChipAndScsiBus(iot, ioh); 374 DvcSleepMilliSecond(sc->scsi_reset_wait * 1000); 375 } 376 if (AscIsChipHalted(iot, ioh) == FALSE) 377 return (-1); 378 379 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 380 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 381 return (-2); 382 383 eep_config = &eep_config_buf; 384 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 385 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 386 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 387 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 388 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 389 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 390 } 391 chksum = AscGetEEPConfig(iot, ioh, eep_config, sc->bus_type); 392 #ifdef ASC_DEBUG 393 AscPrintEEPConfig(eep_config, chksum); 394 #endif 395 if (chksum == 0) 396 chksum = 0xAA55; 397 398 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 399 warn_code |= ASC_WARN_AUTO_CONFIG; 400 if (sc->chip_version == 3) { 401 if (eep_config->cfg_lsw != cfg_lsw) { 402 warn_code |= ASC_WARN_EEPROM_RECOVER; 403 eep_config->cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 404 } 405 if (eep_config->cfg_msw != cfg_msw) { 406 warn_code |= ASC_WARN_EEPROM_RECOVER; 407 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 408 } 409 } 410 } 411 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 412 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 413 414 if (chksum != eep_config->chksum) { 415 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 416 ASC_CHIP_VER_PCI_ULTRA_3050) { 417 eep_config->init_sdtr = 0xFF; 418 eep_config->disc_enable = 0xFF; 419 eep_config->start_motor = 0xFF; 420 eep_config->use_cmd_qng = 0; 421 eep_config->max_total_qng = 0xF0; 422 eep_config->max_tag_qng = 0x20; 423 eep_config->cntl = 0xBFFF; 424 eep_config->chip_scsi_id = 7; 425 eep_config->no_scam = 0; 426 eep_config->adapter_info[0] = 0; 427 eep_config->adapter_info[1] = 0; 428 eep_config->adapter_info[2] = 0; 429 eep_config->adapter_info[3] = 0; 430 #if BYTE_ORDER == BIG_ENDIAN 431 eep_config->adapter_info[5] = 0; 432 /* Indicate EEPROM-less board. */ 433 eep_config->adapter_info[4] = 0xBB; 434 #else 435 eep_config->adapter_info[4] = 0; 436 /* Indicate EEPROM-less board. */ 437 eep_config->adapter_info[5] = 0xBB; 438 #endif 439 } else { 440 write_eep = 1; 441 warn_code |= ASC_WARN_EEPROM_CHKSUM; 442 } 443 } 444 sc->sdtr_enable = eep_config->init_sdtr; 445 sc->disc_enable = eep_config->disc_enable; 446 sc->cmd_qng_enabled = eep_config->use_cmd_qng; 447 sc->isa_dma_speed = eep_config->isa_dma_speed; 448 sc->start_motor = eep_config->start_motor; 449 sc->dvc_cntl = eep_config->cntl; 450 #if BYTE_ORDER == BIG_ENDIAN 451 sc->adapter_info[0] = eep_config->adapter_info[1]; 452 sc->adapter_info[1] = eep_config->adapter_info[0]; 453 sc->adapter_info[2] = eep_config->adapter_info[3]; 454 sc->adapter_info[3] = eep_config->adapter_info[2]; 455 sc->adapter_info[4] = eep_config->adapter_info[5]; 456 sc->adapter_info[5] = eep_config->adapter_info[4]; 457 #else 458 sc->adapter_info[0] = eep_config->adapter_info[0]; 459 sc->adapter_info[1] = eep_config->adapter_info[1]; 460 sc->adapter_info[2] = eep_config->adapter_info[2]; 461 sc->adapter_info[3] = eep_config->adapter_info[3]; 462 sc->adapter_info[4] = eep_config->adapter_info[4]; 463 sc->adapter_info[5] = eep_config->adapter_info[5]; 464 #endif 465 466 if (!AscTestExternalLram(iot, ioh)) { 467 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) { 468 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 469 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 470 } else { 471 eep_config->cfg_msw |= 0x0800; 472 cfg_msw |= 0x0800; 473 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 474 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 475 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 476 } 477 } 478 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) 479 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 480 481 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) 482 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 483 484 if (eep_config->max_tag_qng > eep_config->max_total_qng) 485 eep_config->max_tag_qng = eep_config->max_total_qng; 486 487 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) 488 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 489 490 sc->max_total_qng = eep_config->max_total_qng; 491 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 492 eep_config->use_cmd_qng) { 493 eep_config->disc_enable = eep_config->use_cmd_qng; 494 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 495 } 496 if (sc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) 497 sc->irq_no = AscGetChipIRQ(iot, ioh, sc->bus_type); 498 499 eep_config->chip_scsi_id &= ASC_MAX_TID; 500 sc->chip_scsi_id = eep_config->chip_scsi_id; 501 if (((sc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 502 !(sc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 503 sc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 504 } 505 for (i = 0; i <= ASC_MAX_TID; i++) { 506 sc->max_tag_qng[i] = eep_config->max_tag_qng; 507 sc->sdtr_period_offset[i] = ASC_DEF_SDTR_OFFSET | 508 (sc->host_init_sdtr_index << 4); 509 } 510 511 eep_config->cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 512 if (write_eep) { 513 AscSetEEPConfig(iot, ioh, eep_config, sc->bus_type); 514 #ifdef ASC_DEBUG 515 AscPrintEEPConfig(eep_config, 0); 516 #endif 517 } 518 519 return (warn_code); 520 } 521 522 523 u_int16_t 524 AscInitFromASC_SOFTC(sc) 525 ASC_SOFTC *sc; 526 { 527 bus_space_tag_t iot = sc->sc_iot; 528 bus_space_handle_t ioh = sc->sc_ioh; 529 u_int16_t cfg_msw; 530 u_int16_t warn_code; 531 u_int16_t pci_device_id = sc->pci_device_id; 532 533 534 warn_code = 0; 535 cfg_msw = ASC_GET_CHIP_CFG_MSW(iot, ioh); 536 537 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 538 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK)); 539 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 540 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 541 } 542 if ((sc->cmd_qng_enabled & sc->disc_enable) != sc->cmd_qng_enabled) { 543 sc->disc_enable = sc->cmd_qng_enabled; 544 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 545 } 546 if (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_AUTO_CONFIG) { 547 warn_code |= ASC_WARN_AUTO_CONFIG; 548 } 549 if ((sc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { 550 AscSetChipIRQ(iot, ioh, sc->irq_no, sc->bus_type); 551 } 552 if (sc->bus_type & ASC_IS_PCI) { 553 cfg_msw &= 0xFFC0; 554 ASC_SET_CHIP_CFG_MSW(iot, ioh, cfg_msw); 555 556 if ((sc->bus_type & ASC_IS_PCI_ULTRA) != ASC_IS_PCI_ULTRA) { 557 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) || 558 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) { 559 sc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 560 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 561 } 562 } 563 } else if (sc->bus_type == ASC_IS_ISAPNP) { 564 if (AscGetChipVersion(iot, ioh, sc->bus_type) == 565 ASC_CHIP_VER_ASYN_BUG) { 566 sc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 567 } 568 } 569 AscSetChipScsiID(iot, ioh, sc->chip_scsi_id); 570 571 if (sc->bus_type & ASC_IS_ISA) { 572 AscSetIsaDmaChannel(iot, ioh, sc->isa_dma_channel); 573 AscSetIsaDmaSpeed(iot, ioh, sc->isa_dma_speed); 574 } 575 return (warn_code); 576 } 577 578 579 /* 580 * - Initialize RISC chip 581 * - Intialize Lram 582 * - Load uCode into Lram 583 * - Enable Interrupts 584 */ 585 int 586 AscInitDriver(sc) 587 ASC_SOFTC *sc; 588 { 589 bus_space_tag_t iot = sc->sc_iot; 590 bus_space_handle_t ioh = sc->sc_ioh; 591 u_int32_t chksum; 592 593 594 if (!AscFindSignature(iot, ioh)) 595 return (1); 596 597 AscDisableInterrupt(iot, ioh); 598 599 AscInitLram(sc); 600 chksum = AscLoadMicroCode(iot, ioh, 0, (u_int16_t *) asc_mcode, 601 asc_mcode_size); 602 if (chksum != asc_mcode_chksum) 603 return (2); 604 605 if (AscInitMicroCodeVar(sc) == 0) 606 return (3); 607 608 AscEnableInterrupt(iot, ioh); 609 610 return (0); 611 } 612 613 614 int 615 AscFindSignature(iot, ioh) 616 bus_space_tag_t iot; 617 bus_space_handle_t ioh; 618 { 619 u_int16_t sig_word; 620 621 if (ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) == ASC_1000_ID1B) { 622 sig_word = ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh); 623 if (sig_word == ASC_1000_ID0W || 624 sig_word == ASC_1000_ID0W_FIX) 625 return (1); 626 } 627 return (0); 628 } 629 630 631 static void 632 AscInitLram(sc) 633 ASC_SOFTC *sc; 634 { 635 bus_space_tag_t iot = sc->sc_iot; 636 bus_space_handle_t ioh = sc->sc_ioh; 637 u_int8_t i; 638 u_int16_t s_addr; 639 640 641 AscMemWordSetLram(iot, ioh, ASC_QADR_BEG, 0, 642 (((sc->max_total_qng + 2 + 1) * 64) >> 1)); 643 644 i = ASC_MIN_ACTIVE_QNO; 645 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 646 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 647 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng); 648 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 649 i++; 650 s_addr += ASC_QBLK_SIZE; 651 for (; i < sc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 652 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i + 1); 653 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i - 1); 654 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 655 } 656 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, ASC_QLINK_END); 657 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, sc->max_total_qng - 1); 658 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, sc->max_total_qng); 659 i++; 660 s_addr += ASC_QBLK_SIZE; 661 for (; i <= (u_int8_t) (sc->max_total_qng + 3); i++, s_addr += ASC_QBLK_SIZE) { 662 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_FWD, i); 663 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_BWD, i); 664 AscWriteLramByte(iot, ioh, s_addr + ASC_SCSIQ_B_QNO, i); 665 } 666 } 667 668 669 void 670 AscReInitLram(sc) 671 ASC_SOFTC *sc; 672 { 673 674 AscInitLram(sc); 675 AscInitQLinkVar(sc); 676 } 677 678 679 static void 680 AscInitQLinkVar(sc) 681 ASC_SOFTC *sc; 682 { 683 bus_space_tag_t iot = sc->sc_iot; 684 bus_space_handle_t ioh = sc->sc_ioh; 685 u_int8_t i; 686 u_int16_t lram_addr; 687 688 689 ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, 1); 690 ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 691 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, 1); 692 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sc->max_total_qng); 693 AscWriteLramByte(iot, ioh, ASCV_BUSY_QHEAD_B, sc->max_total_qng + 1); 694 AscWriteLramByte(iot, ioh, ASCV_DISC1_QHEAD_B, sc->max_total_qng + 2); 695 AscWriteLramByte(iot, ioh, ASCV_TOTAL_READY_Q_B, sc->max_total_qng); 696 AscWriteLramWord(iot, ioh, ASCV_ASCDVC_ERR_CODE_W, 0); 697 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 698 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 699 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, 0); 700 AscWriteLramByte(iot, ioh, ASCV_WTM_FLAG_B, 0); 701 ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, 0); 702 lram_addr = ASC_QADR_BEG; 703 for (i = 0; i < 32; i++, lram_addr += 2) 704 AscWriteLramWord(iot, ioh, lram_addr, 0); 705 } 706 707 708 static int 709 AscResetChipAndScsiBus(bus_space_tag_t iot, 710 bus_space_handle_t ioh) 711 { 712 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 713 714 AscStopChip(iot, ioh); 715 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_SCSI_RESET | ASC_CC_HALT); 716 717 DvcDelayNanoSecond(60000); 718 719 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 720 AscSetChipIH(iot, ioh, ASC_INS_HALT); 721 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_CHIP_RESET | ASC_CC_HALT); 722 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 723 724 DvcSleepMilliSecond(200); 725 726 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 727 AscStartChip(iot, ioh); 728 729 DvcSleepMilliSecond(200); 730 731 return (AscIsChipHalted(iot, ioh)); 732 } 733 734 735 static u_int16_t 736 AscGetChipBusType(iot, ioh) 737 bus_space_tag_t iot; 738 bus_space_handle_t ioh; 739 { 740 u_int16_t chip_ver; 741 742 chip_ver = ASC_GET_CHIP_VER_NO(iot, ioh); 743 if ((chip_ver >= ASC_CHIP_MIN_VER_VL) && 744 (chip_ver <= ASC_CHIP_MAX_VER_VL)) { 745 /* 746 * if(((iop_base & 0x0C30) == 0x0C30) || ((iop_base & 0x0C50) 747 * == 0x0C50)) return (ASC_IS_EISA); 748 */ 749 return (ASC_IS_VL); 750 } 751 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) && 752 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) { 753 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) 754 return (ASC_IS_ISAPNP); 755 756 return (ASC_IS_ISA); 757 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) && 758 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) 759 return (ASC_IS_PCI); 760 761 return (0); 762 } 763 764 765 /******************************************************************************/ 766 /* Chip register routines */ 767 /******************************************************************************/ 768 769 770 static void 771 AscSetBank(iot, ioh, bank) 772 bus_space_tag_t iot; 773 bus_space_handle_t ioh; 774 u_int8_t bank; 775 { 776 u_int8_t val; 777 778 val = ASC_GET_CHIP_CONTROL(iot, ioh) & 779 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | 780 ASC_CC_DIAG | ASC_CC_SCSI_RESET | 781 ASC_CC_CHIP_RESET)); 782 783 switch (bank) { 784 case 1: 785 val |= ASC_CC_BANK_ONE; 786 break; 787 788 case 2: 789 val |= ASC_CC_DIAG | ASC_CC_BANK_ONE; 790 break; 791 792 default: 793 val &= ~ASC_CC_BANK_ONE; 794 } 795 796 ASC_SET_CHIP_CONTROL(iot, ioh, val); 797 return; 798 } 799 800 801 /******************************************************************************/ 802 /* Chip routines */ 803 /******************************************************************************/ 804 805 806 static int 807 AscStartChip(iot, ioh) 808 bus_space_tag_t iot; 809 bus_space_handle_t ioh; 810 { 811 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 812 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 813 return (0); 814 815 return (1); 816 } 817 818 819 static int 820 AscStopChip(iot, ioh) 821 bus_space_tag_t iot; 822 bus_space_handle_t ioh; 823 { 824 u_int8_t cc_val; 825 826 cc_val = ASC_GET_CHIP_CONTROL(iot, ioh) & 827 (~(ASC_CC_SINGLE_STEP | ASC_CC_TEST | ASC_CC_DIAG)); 828 ASC_SET_CHIP_CONTROL(iot, ioh, cc_val | ASC_CC_HALT); 829 AscSetChipIH(iot, ioh, ASC_INS_HALT); 830 AscSetChipIH(iot, ioh, ASC_INS_RFLAG_WTM); 831 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) == 0) 832 return (0); 833 834 return (1); 835 } 836 837 838 static u_int8_t 839 AscGetChipVersion(iot, ioh, bus_type) 840 bus_space_tag_t iot; 841 bus_space_handle_t ioh; 842 u_int16_t bus_type; 843 { 844 if (bus_type & ASC_IS_EISA) { 845 /* 846 * u_int16_t eisa_iop; u_int8_t revision; 847 * 848 * eisa_iop = ASC_GET_EISA_SLOT(iop_base) | 849 * ASC_EISA_REV_IOP_MASK; revision = inp(eisa_iop); 850 * return((ASC_CHIP_MIN_VER_EISA - 1) + revision); 851 */ 852 } 853 return (ASC_GET_CHIP_VER_NO(iot, ioh)); 854 } 855 856 857 static u_int8_t 858 AscSetChipScsiID(iot, ioh, new_id) 859 bus_space_tag_t iot; 860 bus_space_handle_t ioh; 861 u_int8_t new_id; 862 { 863 u_int16_t cfg_lsw; 864 865 if (ASC_GET_CHIP_SCSI_ID(iot, ioh) == new_id) 866 return (new_id); 867 868 cfg_lsw = ASC_GET_CHIP_SCSI_ID(iot, ioh); 869 cfg_lsw &= 0xF8FF; 870 cfg_lsw |= (new_id & ASC_MAX_TID) << 8; 871 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 872 return (ASC_GET_CHIP_SCSI_ID(iot, ioh)); 873 } 874 875 876 static u_int8_t 877 AscGetChipScsiCtrl(iot, ioh) 878 bus_space_tag_t iot; 879 bus_space_handle_t ioh; 880 { 881 u_int8_t scsi_ctrl; 882 883 AscSetBank(iot, ioh, 1); 884 scsi_ctrl = bus_space_read_1(iot, ioh, ASC_IOP_REG_SC); 885 AscSetBank(iot, ioh, 0); 886 return (scsi_ctrl); 887 } 888 889 890 static int 891 AscSetRunChipSynRegAtID(iot, ioh, tid_no, sdtr_data) 892 bus_space_tag_t iot; 893 bus_space_handle_t ioh; 894 u_int8_t tid_no; 895 u_int8_t sdtr_data; 896 { 897 int retval = FALSE; 898 899 if (AscHostReqRiscHalt(iot, ioh)) { 900 retval = AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 901 AscStartChip(iot, ioh); 902 } 903 return (retval); 904 } 905 906 907 static int 908 AscSetChipSynRegAtID(iot, ioh, id, sdtr_data) 909 bus_space_tag_t iot; 910 bus_space_handle_t ioh; 911 u_int8_t id; 912 u_int8_t sdtr_data; 913 { 914 ASC_SCSI_BIT_ID_TYPE org_id; 915 int i; 916 int sta = TRUE; 917 918 AscSetBank(iot, ioh, 1); 919 org_id = ASC_READ_CHIP_DVC_ID(iot, ioh); 920 for (i = 0; i <= ASC_MAX_TID; i++) 921 if (org_id == (0x01 << i)) 922 break; 923 924 org_id = i; 925 ASC_WRITE_CHIP_DVC_ID(iot, ioh, id); 926 if (ASC_READ_CHIP_DVC_ID(iot, ioh) == (0x01 << id)) { 927 AscSetBank(iot, ioh, 0); 928 ASC_SET_CHIP_SYN(iot, ioh, sdtr_data); 929 if (ASC_GET_CHIP_SYN(iot, ioh) != sdtr_data) 930 sta = FALSE; 931 } else 932 sta = FALSE; 933 934 AscSetBank(iot, ioh, 1); 935 ASC_WRITE_CHIP_DVC_ID(iot, ioh, org_id); 936 AscSetBank(iot, ioh, 0); 937 return (sta); 938 } 939 940 941 static int 942 AscHostReqRiscHalt(iot, ioh) 943 bus_space_tag_t iot; 944 bus_space_handle_t ioh; 945 { 946 int count = 0; 947 int retval = 0; 948 u_int8_t saved_stop_code; 949 950 951 if (AscIsChipHalted(iot, ioh)) 952 return (1); 953 saved_stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 954 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 955 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 956 957 do { 958 if (AscIsChipHalted(iot, ioh)) { 959 retval = 1; 960 break; 961 } 962 DvcSleepMilliSecond(100); 963 } while (count++ < 20); 964 965 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, saved_stop_code); 966 967 return (retval); 968 } 969 970 971 static int 972 AscIsChipHalted(iot, ioh) 973 bus_space_tag_t iot; 974 bus_space_handle_t ioh; 975 { 976 if ((ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_HALTED) != 0) 977 if ((ASC_GET_CHIP_CONTROL(iot, ioh) & ASC_CC_HALT) != 0) 978 return (1); 979 980 return (0); 981 } 982 983 984 static void 985 AscSetChipIH(iot, ioh, ins_code) 986 bus_space_tag_t iot; 987 bus_space_handle_t ioh; 988 u_int16_t ins_code; 989 { 990 AscSetBank(iot, ioh, 1); 991 ASC_WRITE_CHIP_IH(iot, ioh, ins_code); 992 AscSetBank(iot, ioh, 0); 993 994 return; 995 } 996 997 998 /******************************************************************************/ 999 /* Lram routines */ 1000 /******************************************************************************/ 1001 1002 1003 static u_int8_t 1004 AscReadLramByte(iot, ioh, addr) 1005 bus_space_tag_t iot; 1006 bus_space_handle_t ioh; 1007 u_int16_t addr; 1008 { 1009 u_int8_t byte_data; 1010 u_int16_t word_data; 1011 1012 1013 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr & 0xFFFE); 1014 word_data = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1015 1016 if (addr & 1) { 1017 /* odd address */ 1018 byte_data = (u_int8_t) ((word_data >> 8) & 0xFF); 1019 } else { 1020 /* even address */ 1021 byte_data = (u_int8_t) (word_data & 0xFF); 1022 } 1023 1024 return (byte_data); 1025 } 1026 1027 1028 static void 1029 AscWriteLramByte(iot, ioh, addr, data) 1030 bus_space_tag_t iot; 1031 bus_space_handle_t ioh; 1032 u_int16_t addr; 1033 u_int8_t data; 1034 { 1035 u_int16_t word_data; 1036 1037 1038 word_data = AscReadLramWord(iot, ioh, addr & 0xFFFE); 1039 1040 if (addr & 1) { 1041 /* odd address */ 1042 word_data &= 0x00FF; 1043 word_data |= (((u_int16_t) data) << 8) & 0xFF00; 1044 } else { 1045 /* even address */ 1046 word_data &= 0xFF00; 1047 word_data |= ((u_int16_t) data) & 0x00FF; 1048 } 1049 1050 AscWriteLramWord(iot, ioh, addr, word_data); 1051 } 1052 1053 1054 static u_int16_t 1055 AscReadLramWord(iot, ioh, addr) 1056 bus_space_tag_t iot; 1057 bus_space_handle_t ioh; 1058 u_int16_t addr; 1059 { 1060 1061 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1062 return (ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 1063 } 1064 1065 1066 static void 1067 AscWriteLramWord(iot, ioh, addr, data) 1068 bus_space_tag_t iot; 1069 bus_space_handle_t ioh; 1070 u_int16_t addr; 1071 u_int16_t data; 1072 { 1073 1074 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1075 ASC_SET_CHIP_LRAM_DATA(iot, ioh, data); 1076 } 1077 1078 1079 static u_int32_t 1080 AscReadLramDWord(iot, ioh, addr) 1081 bus_space_tag_t iot; 1082 bus_space_handle_t ioh; 1083 u_int16_t addr; 1084 { 1085 u_int16_t low_word, hi_word; 1086 1087 1088 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1089 low_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1090 hi_word = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 1091 1092 return ((((u_int32_t) hi_word) << 16) | (u_int32_t) low_word); 1093 } 1094 1095 1096 static void 1097 AscWriteLramDWord(iot, ioh, addr, data) 1098 bus_space_tag_t iot; 1099 bus_space_handle_t ioh; 1100 u_int16_t addr; 1101 u_int32_t data; 1102 { 1103 1104 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 1105 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data & 0x0000FFFF)); 1106 ASC_SET_CHIP_LRAM_DATA(iot, ioh, (u_int16_t) (data >> 16)); 1107 } 1108 1109 1110 static void 1111 AscMemWordSetLram(iot, ioh, s_addr, s_words, count) 1112 bus_space_tag_t iot; 1113 bus_space_handle_t ioh; 1114 u_int16_t s_addr; 1115 u_int16_t s_words; 1116 int count; 1117 { 1118 int i; 1119 1120 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1121 for (i = 0; i < count; i++) 1122 ASC_SET_CHIP_LRAM_DATA(iot, ioh, s_words); 1123 } 1124 1125 1126 static void 1127 AscMemWordCopyToLram(iot, ioh, s_addr, s_buffer, words) 1128 bus_space_tag_t iot; 1129 bus_space_handle_t ioh; 1130 u_int16_t s_addr; 1131 u_int16_t *s_buffer; 1132 int words; 1133 { 1134 int i; 1135 1136 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1137 for (i = 0; i < words; i++, s_buffer++) 1138 ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, *s_buffer); 1139 } 1140 1141 1142 static void 1143 AscMemWordCopyFromLram(iot, ioh, s_addr, s_buffer, words) 1144 bus_space_tag_t iot; 1145 bus_space_handle_t ioh; 1146 u_int16_t s_addr; 1147 u_int16_t *s_buffer; 1148 int words; 1149 { 1150 int i; 1151 1152 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1153 for (i = 0; i < words; i++, s_buffer++) 1154 *s_buffer = ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh); 1155 } 1156 1157 1158 static void 1159 AscMemDWordCopyToLram(iot, ioh, s_addr, s_buffer, dwords) 1160 bus_space_tag_t iot; 1161 bus_space_handle_t ioh; 1162 u_int16_t s_addr; 1163 u_int32_t *s_buffer; 1164 int dwords; 1165 { 1166 int i; 1167 u_int32_t *pw; 1168 1169 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, s_addr); 1170 1171 pw = s_buffer; 1172 for (i = 0; i < dwords; i++, pw++) { 1173 ASC_SET_CHIP_LRAM_DATA(iot, ioh, LO_WORD(*pw)); 1174 DELAY(1); 1175 ASC_SET_CHIP_LRAM_DATA(iot, ioh, HI_WORD(*pw)); 1176 } 1177 } 1178 1179 1180 static u_int32_t 1181 AscMemSumLramWord(iot, ioh, s_addr, words) 1182 bus_space_tag_t iot; 1183 bus_space_handle_t ioh; 1184 u_int16_t s_addr; 1185 int words; 1186 { 1187 u_int32_t sum = 0L; 1188 u_int16_t i; 1189 1190 1191 for (i = 0; i < words; i++, s_addr += 2) 1192 sum += AscReadLramWord(iot, ioh, s_addr); 1193 1194 return (sum); 1195 } 1196 1197 1198 static int 1199 AscTestExternalLram(iot, ioh) 1200 bus_space_tag_t iot; 1201 bus_space_handle_t ioh; 1202 { 1203 u_int16_t q_addr; 1204 u_int16_t saved_word; 1205 int retval; 1206 1207 1208 retval = 0; 1209 q_addr = ASC_QNO_TO_QADDR(241); 1210 saved_word = AscReadLramWord(iot, ioh, q_addr); 1211 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1212 ASC_SET_CHIP_LRAM_DATA(iot, ioh, 0x55AA); 1213 DvcSleepMilliSecond(10); 1214 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, q_addr); 1215 1216 if (ASC_GET_CHIP_LRAM_DATA(iot, ioh) == 0x55AA) { 1217 retval = 1; 1218 AscWriteLramWord(iot, ioh, q_addr, saved_word); 1219 } 1220 return (retval); 1221 } 1222 1223 1224 /******************************************************************************/ 1225 /* MicroCode routines */ 1226 /******************************************************************************/ 1227 1228 1229 static u_int16_t 1230 AscInitMicroCodeVar(sc) 1231 ASC_SOFTC *sc; 1232 { 1233 bus_space_tag_t iot = sc->sc_iot; 1234 bus_space_handle_t ioh = sc->sc_ioh; 1235 u_int32_t phy_addr; 1236 int i; 1237 1238 1239 for (i = 0; i <= ASC_MAX_TID; i++) 1240 ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, i, 1241 sc->sdtr_period_offset[i]); 1242 1243 AscInitQLinkVar(sc); 1244 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, sc->disc_enable); 1245 AscWriteLramByte(iot, ioh, ASCV_HOSTSCSI_ID_B, 1246 ASC_TID_TO_TARGET_ID(sc->chip_scsi_id)); 1247 1248 if ((phy_addr = AscGetOnePhyAddr(sc, sc->overrun_buf, 1249 ASC_OVERRUN_BSIZE)) == 0L) { 1250 return (0); 1251 } else { 1252 phy_addr = (phy_addr & 0xFFFFFFF8ul) + 8; 1253 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_PADDR_D, phy_addr); 1254 AscWriteLramDWord(iot, ioh, ASCV_OVERRUN_BSIZE_D, 1255 ASC_OVERRUN_BSIZE - 8); 1256 } 1257 1258 sc->mcode_date = AscReadLramWord(iot, ioh, ASCV_MC_DATE_W); 1259 sc->mcode_version = AscReadLramWord(iot, ioh, ASCV_MC_VER_W); 1260 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 1261 1262 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) { 1263 return (0); 1264 } 1265 if (AscStartChip(iot, ioh) != 1) { 1266 return (0); 1267 } 1268 return (1); 1269 } 1270 1271 1272 static u_int32_t 1273 AscLoadMicroCode(iot, ioh, s_addr, mcode_buf, mcode_size) 1274 bus_space_tag_t iot; 1275 bus_space_handle_t ioh; 1276 u_int16_t s_addr; 1277 u_int16_t *mcode_buf; 1278 u_int16_t mcode_size; 1279 { 1280 u_int32_t chksum; 1281 u_int16_t mcode_word_size; 1282 u_int16_t mcode_chksum; 1283 1284 mcode_word_size = mcode_size >> 1; 1285 /* clear board memory */ 1286 AscMemWordSetLram(iot, ioh, s_addr, 0, mcode_word_size); 1287 /* copy uCode to board memory */ 1288 AscMemWordCopyToLram(iot, ioh, s_addr, mcode_buf, mcode_word_size); 1289 chksum = AscMemSumLramWord(iot, ioh, s_addr, mcode_word_size); 1290 mcode_chksum = AscMemSumLramWord(iot, ioh, ASC_CODE_SEC_BEG, 1291 ((mcode_size - s_addr - ASC_CODE_SEC_BEG) >> 1)); 1292 AscWriteLramWord(iot, ioh, ASCV_MCODE_CHKSUM_W, mcode_chksum); 1293 AscWriteLramWord(iot, ioh, ASCV_MCODE_SIZE_W, mcode_size); 1294 1295 return (chksum); 1296 } 1297 1298 1299 static u_int32_t 1300 AscGetOnePhyAddr(sc, buf_addr, buf_size) 1301 ASC_SOFTC *sc; 1302 u_int8_t *buf_addr; 1303 u_int32_t buf_size; 1304 { 1305 ASC_MIN_SG_HEAD sg_head; 1306 1307 sg_head.entry_cnt = ASC_MIN_SG_LIST; 1308 if (AscGetSGList(sc, buf_addr, buf_size, (ASC_SG_HEAD *) & sg_head) != 1309 buf_size) { 1310 return (0L); 1311 } 1312 if (sg_head.entry_cnt > 1) { 1313 return (0L); 1314 } 1315 return (sg_head.sg_list[0].addr); 1316 } 1317 1318 1319 static u_int32_t 1320 AscGetSGList(sc, buf_addr, buf_len, asc_sg_head_ptr) 1321 ASC_SOFTC *sc; 1322 u_int8_t *buf_addr; 1323 u_int32_t buf_len; 1324 ASC_SG_HEAD *asc_sg_head_ptr; 1325 { 1326 u_int32_t buf_size; 1327 1328 buf_size = buf_len; 1329 asc_sg_head_ptr->entry_cnt = 1; 1330 asc_sg_head_ptr->sg_list[0].addr = (u_int32_t) buf_addr; 1331 asc_sg_head_ptr->sg_list[0].bytes = buf_size; 1332 1333 return (buf_size); 1334 } 1335 1336 1337 /******************************************************************************/ 1338 /* EEProm routines */ 1339 /******************************************************************************/ 1340 1341 1342 static int 1343 AscWriteEEPCmdReg(iot, ioh, cmd_reg) 1344 bus_space_tag_t iot; 1345 bus_space_handle_t ioh; 1346 u_int8_t cmd_reg; 1347 { 1348 u_int8_t read_back; 1349 int retry; 1350 1351 retry = 0; 1352 1353 while (TRUE) { 1354 ASC_SET_CHIP_EEP_CMD(iot, ioh, cmd_reg); 1355 DvcSleepMilliSecond(1); 1356 read_back = ASC_GET_CHIP_EEP_CMD(iot, ioh); 1357 if (read_back == cmd_reg) 1358 return (1); 1359 1360 if (retry++ > ASC_EEP_MAX_RETRY) 1361 return (0); 1362 } 1363 } 1364 1365 1366 static int 1367 AscWriteEEPDataReg(iot, ioh, data_reg) 1368 bus_space_tag_t iot; 1369 bus_space_handle_t ioh; 1370 u_int16_t data_reg; 1371 { 1372 u_int16_t read_back; 1373 int retry; 1374 1375 retry = 0; 1376 while (TRUE) { 1377 ASC_SET_CHIP_EEP_DATA(iot, ioh, data_reg); 1378 DvcSleepMilliSecond(1); 1379 read_back = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1380 if (read_back == data_reg) 1381 return (1); 1382 1383 if (retry++ > ASC_EEP_MAX_RETRY) 1384 return (0); 1385 } 1386 } 1387 1388 1389 static void 1390 AscWaitEEPRead(void) 1391 { 1392 1393 DvcSleepMilliSecond(1); 1394 } 1395 1396 1397 static void 1398 AscWaitEEPWrite(void) 1399 { 1400 1401 DvcSleepMilliSecond(1); 1402 } 1403 1404 1405 static u_int16_t 1406 AscReadEEPWord(iot, ioh, addr) 1407 bus_space_tag_t iot; 1408 bus_space_handle_t ioh; 1409 u_int8_t addr; 1410 { 1411 u_int16_t read_wval; 1412 u_int8_t cmd_reg; 1413 1414 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1415 AscWaitEEPRead(); 1416 cmd_reg = addr | ASC_EEP_CMD_READ; 1417 AscWriteEEPCmdReg(iot, ioh, cmd_reg); 1418 AscWaitEEPRead(); 1419 read_wval = ASC_GET_CHIP_EEP_DATA(iot, ioh); 1420 AscWaitEEPRead(); 1421 1422 return (read_wval); 1423 } 1424 1425 1426 static u_int16_t 1427 AscWriteEEPWord(iot, ioh, addr, word_val) 1428 bus_space_tag_t iot; 1429 bus_space_handle_t ioh; 1430 u_int8_t addr; 1431 u_int16_t word_val; 1432 { 1433 u_int16_t read_wval; 1434 1435 read_wval = AscReadEEPWord(iot, ioh, addr); 1436 if (read_wval != word_val) { 1437 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_ABLE); 1438 AscWaitEEPRead(); 1439 AscWriteEEPDataReg(iot, ioh, word_val); 1440 AscWaitEEPRead(); 1441 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE | addr); 1442 AscWaitEEPWrite(); 1443 AscWriteEEPCmdReg(iot, ioh, ASC_EEP_CMD_WRITE_DISABLE); 1444 AscWaitEEPRead(); 1445 return (AscReadEEPWord(iot, ioh, addr)); 1446 } 1447 return (read_wval); 1448 } 1449 1450 1451 static u_int16_t 1452 AscGetEEPConfig(iot, ioh, cfg_buf, bus_type) 1453 bus_space_tag_t iot; 1454 bus_space_handle_t ioh; 1455 ASCEEP_CONFIG *cfg_buf; 1456 u_int16_t bus_type; 1457 { 1458 u_int16_t wval; 1459 u_int16_t sum; 1460 u_int16_t *wbuf; 1461 int cfg_beg; 1462 int cfg_end; 1463 int s_addr; 1464 int isa_pnp_wsize; 1465 1466 1467 wbuf = (u_int16_t *) cfg_buf; 1468 sum = 0; 1469 isa_pnp_wsize = 0; 1470 1471 for (s_addr = 0; s_addr < (2 + isa_pnp_wsize); s_addr++, wbuf++) { 1472 wval = AscReadEEPWord(iot, ioh, s_addr); 1473 sum += wval; 1474 *wbuf = wval; 1475 } 1476 1477 if (bus_type & ASC_IS_VL) { 1478 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1479 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1480 } else { 1481 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1482 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1483 } 1484 1485 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1486 wval = AscReadEEPWord(iot, ioh, s_addr); 1487 sum += wval; 1488 *wbuf = wval; 1489 } 1490 1491 *wbuf = AscReadEEPWord(iot, ioh, s_addr); 1492 1493 return (sum); 1494 } 1495 1496 1497 static int 1498 AscSetEEPConfig(iot, ioh, cfg_buf, bus_type) 1499 bus_space_tag_t iot; 1500 bus_space_handle_t ioh; 1501 ASCEEP_CONFIG *cfg_buf; 1502 u_int16_t bus_type; 1503 { 1504 int retry; 1505 int n_error; 1506 1507 retry = 0; 1508 while (TRUE) { 1509 if ((n_error = AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type)) == 0) 1510 break; 1511 1512 if (++retry > ASC_EEP_MAX_RETRY) 1513 break; 1514 } 1515 1516 return (n_error); 1517 } 1518 1519 1520 static int 1521 AscSetEEPConfigOnce(iot, ioh, cfg_buf, bus_type) 1522 bus_space_tag_t iot; 1523 bus_space_handle_t ioh; 1524 ASCEEP_CONFIG *cfg_buf; 1525 u_int16_t bus_type; 1526 { 1527 int n_error; 1528 u_int16_t *wbuf; 1529 u_int16_t sum; 1530 int s_addr; 1531 int cfg_beg; 1532 int cfg_end; 1533 1534 wbuf = (u_int16_t *) cfg_buf; 1535 n_error = 0; 1536 sum = 0; 1537 1538 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1539 sum += *wbuf; 1540 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1541 n_error++; 1542 } 1543 1544 if (bus_type & ASC_IS_VL) { 1545 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 1546 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 1547 } else { 1548 cfg_beg = ASC_EEP_DVC_CFG_BEG; 1549 cfg_end = ASC_EEP_MAX_DVC_ADDR; 1550 } 1551 1552 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 1553 sum += *wbuf; 1554 if (*wbuf != AscWriteEEPWord(iot, ioh, s_addr, *wbuf)) 1555 n_error++; 1556 } 1557 1558 *wbuf = sum; 1559 if (sum != AscWriteEEPWord(iot, ioh, s_addr, sum)) 1560 n_error++; 1561 1562 wbuf = (u_int16_t *) cfg_buf; 1563 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 1564 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1565 n_error++; 1566 } 1567 1568 for (s_addr = cfg_beg; s_addr <= cfg_end; s_addr++, wbuf++) { 1569 if (*wbuf != AscReadEEPWord(iot, ioh, s_addr)) 1570 n_error++; 1571 } 1572 1573 return (n_error); 1574 } 1575 1576 1577 #ifdef ASC_DEBUG 1578 static void 1579 AscPrintEEPConfig(eep_config, chksum) 1580 ASCEEP_CONFIG *eep_config; 1581 u_int16_t chksum; 1582 { 1583 printf("---- ASC EEprom settings ----\n"); 1584 printf("cfg_lsw = 0x%x\n", eep_config->cfg_lsw); 1585 printf("cfg_msw = 0x%x\n", eep_config->cfg_msw); 1586 printf("init_sdtr = 0x%x\n", eep_config->init_sdtr); 1587 printf("disc_enable = 0x%x\n", eep_config->disc_enable); 1588 printf("use_cmd_qng = %d\n", eep_config->use_cmd_qng); 1589 printf("start_motor = 0x%x\n", eep_config->start_motor); 1590 printf("max_total_qng = 0x%x\n", eep_config->max_total_qng); 1591 printf("max_tag_qng = 0x%x\n", eep_config->max_tag_qng); 1592 printf("bios_scan = 0x%x\n", eep_config->bios_scan); 1593 printf("power_up_wait = 0x%x\n", eep_config->power_up_wait); 1594 printf("no_scam = %d\n", eep_config->no_scam); 1595 printf("chip_scsi_id = %d\n", eep_config->chip_scsi_id); 1596 printf("isa_dma_speed = %d\n", eep_config->isa_dma_speed); 1597 printf("cntl = 0x%x\n", eep_config->cntl); 1598 #if BYTE_ORDER == BIG_ENDIAN 1599 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[1]); 1600 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[0]); 1601 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[3]); 1602 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[2]); 1603 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[5]); 1604 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[4]); 1605 #else 1606 printf("adapter_info[0] = 0x%x\n", eep_config->adapter_info[0]); 1607 printf("adapter_info[1] = 0x%x\n", eep_config->adapter_info[1]); 1608 printf("adapter_info[2] = 0x%x\n", eep_config->adapter_info[2]); 1609 printf("adapter_info[3] = 0x%x\n", eep_config->adapter_info[3]); 1610 printf("adapter_info[4] = 0x%x\n", eep_config->adapter_info[4]); 1611 printf("adapter_info[5] = 0x%x\n", eep_config->adapter_info[5]); 1612 #endif 1613 printf("checksum = 0x%x\n", eep_config->chksum); 1614 printf("calculated checksum = 0x%x\n", chksum); 1615 printf("-----------------------------\n"); 1616 } 1617 #endif 1618 1619 1620 /******************************************************************************/ 1621 /* Interrupt routines */ 1622 /******************************************************************************/ 1623 1624 1625 int 1626 AscISR(sc) 1627 ASC_SOFTC *sc; 1628 { 1629 bus_space_tag_t iot = sc->sc_iot; 1630 bus_space_handle_t ioh = sc->sc_ioh; 1631 u_int16_t chipstat; 1632 u_int16_t saved_ram_addr; 1633 u_int8_t ctrl_reg; 1634 u_int8_t saved_ctrl_reg; 1635 int int_pending; 1636 int status; 1637 u_int8_t host_flag; 1638 1639 1640 int_pending = FALSE; 1641 1642 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); 1643 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | 1644 ASC_CC_SINGLE_STEP | ASC_CC_DIAG | ASC_CC_TEST)); 1645 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1646 if (chipstat & ASC_CSW_SCSI_RESET_LATCH) { 1647 if (!(sc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 1648 int_pending = TRUE; 1649 sc->sdtr_done = 0; 1650 saved_ctrl_reg &= (u_int8_t) (~ASC_CC_HALT); 1651 1652 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_SCSI_RESET_ACTIVE); 1653 1654 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_CHIP_RESET | ASC_CC_HALT)); 1655 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1656 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1657 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1658 chipstat = ASC_GET_CHIP_STATUS(iot, ioh); 1659 } 1660 } 1661 saved_ram_addr = ASC_GET_CHIP_LRAM_ADDR(iot, ioh); 1662 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 1663 (u_int8_t) (~ASC_HOST_FLAG_IN_ISR); 1664 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 1665 (host_flag | ASC_HOST_FLAG_IN_ISR)); 1666 1667 if ((chipstat & ASC_CSW_INT_PENDING) || (int_pending)) { 1668 AscAckInterrupt(iot, ioh); 1669 int_pending = TRUE; 1670 1671 if ((chipstat & ASC_CSW_HALTED) && 1672 (ctrl_reg & ASC_CC_SINGLE_STEP)) { 1673 AscIsrChipHalted(sc); 1674 saved_ctrl_reg &= ~ASC_CC_HALT; 1675 } else { 1676 if (sc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) { 1677 while (((status = AscIsrQDone(sc)) & 0x01) != 0); 1678 } else { 1679 do { 1680 if ((status = AscIsrQDone(sc)) == 1) 1681 break; 1682 } while (status == 0x11); 1683 } 1684 1685 if (status & 0x80) 1686 int_pending = -1; 1687 } 1688 } 1689 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 1690 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, saved_ram_addr); 1691 ASC_SET_CHIP_CONTROL(iot, ioh, saved_ctrl_reg); 1692 1693 return (1); 1694 /* return(int_pending); */ 1695 } 1696 1697 1698 static int 1699 AscIsrQDone(sc) 1700 ASC_SOFTC *sc; 1701 { 1702 u_int8_t next_qp; 1703 u_int8_t n_q_used; 1704 u_int8_t sg_list_qp; 1705 u_int8_t sg_queue_cnt; 1706 u_int8_t q_cnt; 1707 u_int8_t done_q_tail; 1708 u_int8_t tid_no; 1709 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1710 ASC_SCSI_BIT_ID_TYPE target_id; 1711 bus_space_tag_t iot = sc->sc_iot; 1712 bus_space_handle_t ioh = sc->sc_ioh; 1713 u_int16_t q_addr; 1714 u_int16_t sg_q_addr; 1715 u_int8_t cur_target_qng; 1716 ASC_QDONE_INFO scsiq_buf; 1717 ASC_QDONE_INFO *scsiq; 1718 ASC_ISR_CALLBACK asc_isr_callback; 1719 1720 1721 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 1722 n_q_used = 1; 1723 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 1724 done_q_tail = ASC_GET_VAR_DONE_QTAIL(iot, ioh); 1725 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 1726 next_qp = AscReadLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_FWD)); 1727 1728 if (next_qp != ASC_QLINK_END) { 1729 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, next_qp); 1730 q_addr = ASC_QNO_TO_QADDR(next_qp); 1731 sg_queue_cnt = _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, 1732 sc->max_dma_count); 1733 AscWriteLramByte(iot, ioh, (q_addr + ASC_SCSIQ_B_STATUS), 1734 (scsiq->q_status & ~(ASC_QS_READY | ASC_QS_ABORTED))); 1735 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 1736 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 1737 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { 1738 sg_q_addr = q_addr; 1739 sg_list_qp = next_qp; 1740 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 1741 sg_list_qp = AscReadLramByte(iot, ioh, 1742 sg_q_addr + ASC_SCSIQ_B_FWD); 1743 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 1744 if (sg_list_qp == ASC_QLINK_END) { 1745 AscSetLibErrorCode(sc, ASCQ_ERR_SG_Q_LINKS); 1746 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1747 scsiq->d3.host_stat = ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED; 1748 panic("AscIsrQDone: Corrupted SG list encountered"); 1749 } 1750 AscWriteLramByte(iot, ioh, 1751 sg_q_addr + ASC_SCSIQ_B_STATUS, ASC_QS_FREE); 1752 } 1753 n_q_used = sg_queue_cnt + 1; 1754 ASC_PUT_VAR_DONE_QTAIL(iot, ioh, sg_list_qp); 1755 } 1756 if (sc->queue_full_or_busy & target_id) { 1757 cur_target_qng = AscReadLramByte(iot, ioh, 1758 ASC_QADR_BEG + scsiq->d2.target_ix); 1759 1760 if (cur_target_qng < sc->max_dvc_qng[tid_no]) { 1761 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1762 scsi_busy &= ~target_id; 1763 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1764 sc->queue_full_or_busy &= ~target_id; 1765 } 1766 } 1767 if (sc->cur_total_qng >= n_q_used) { 1768 sc->cur_total_qng -= n_q_used; 1769 if (sc->cur_dvc_qng[tid_no] != 0) { 1770 sc->cur_dvc_qng[tid_no]--; 1771 } 1772 } else { 1773 AscSetLibErrorCode(sc, ASCQ_ERR_CUR_QNG); 1774 scsiq->d3.done_stat = ASC_QD_WITH_ERROR; 1775 panic("AscIsrQDone: Attempting to free more queues than are active"); 1776 } 1777 1778 if ((adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == 0UL) || 1779 ((scsiq->q_status & ASC_QS_ABORTED) != 0)) { 1780 return (0x11); 1781 } else if (scsiq->q_status == ASC_QS_DONE) { 1782 scsiq->remain_bytes += scsiq->extra_bytes; 1783 1784 if (scsiq->d3.done_stat == ASC_QD_WITH_ERROR) { 1785 if (scsiq->d3.host_stat == ASC_QHSTA_M_DATA_OVER_RUN) { 1786 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { 1787 scsiq->d3.done_stat = ASC_QD_NO_ERROR; 1788 scsiq->d3.host_stat = ASC_QHSTA_NO_ERROR; 1789 } 1790 } else if (scsiq->d3.host_stat == ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 1791 AscStopChip(iot, ioh); 1792 ASC_SET_CHIP_CONTROL(iot, ioh, (ASC_CC_SCSI_RESET | ASC_CC_HALT)); 1793 DvcDelayNanoSecond(60000); 1794 ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); 1795 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_CLR_SCSI_RESET_INT); 1796 ASC_SET_CHIP_STATUS(iot, ioh, 0); 1797 ASC_SET_CHIP_CONTROL(iot, ioh, 0); 1798 } 1799 } 1800 (*asc_isr_callback) (sc, scsiq); 1801 1802 return (1); 1803 } else { 1804 AscSetLibErrorCode(sc, ASCQ_ERR_Q_STATUS); 1805 panic("AscIsrQDone: completed scsiq with unknown status"); 1806 1807 return (0x80); 1808 } 1809 } 1810 return (0); 1811 } 1812 1813 1814 /* 1815 * handle all the conditions that may halt the board 1816 * waiting us to intervene 1817 */ 1818 static void 1819 AscIsrChipHalted(sc) 1820 ASC_SOFTC *sc; 1821 { 1822 bus_space_tag_t iot = sc->sc_iot; 1823 bus_space_handle_t ioh = sc->sc_ioh; 1824 EXT_MSG out_msg; 1825 u_int16_t int_halt_code; 1826 u_int16_t halt_q_addr; 1827 u_int8_t halt_qp; 1828 u_int8_t target_ix; 1829 u_int8_t tag_code; 1830 u_int8_t q_status; 1831 u_int8_t q_cntl; 1832 u_int8_t tid_no; 1833 u_int8_t cur_dvc_qng; 1834 u_int8_t asyn_sdtr; 1835 u_int8_t scsi_status; 1836 u_int8_t sdtr_data; 1837 ASC_SCSI_BIT_ID_TYPE scsi_busy; 1838 ASC_SCSI_BIT_ID_TYPE target_id; 1839 1840 1841 int_halt_code = AscReadLramWord(iot, ioh, ASCV_HALTCODE_W); 1842 1843 halt_qp = AscReadLramByte(iot, ioh, ASCV_CURCDB_B); 1844 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 1845 target_ix = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TARGET_IX); 1846 q_cntl = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL); 1847 tid_no = ASC_TIX_TO_TID(target_ix); 1848 target_id = ASC_TID_TO_TARGET_ID(tid_no); 1849 1850 if (sc->pci_fix_asyn_xfer & target_id) { 1851 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 1852 } else { 1853 asyn_sdtr = 0; 1854 } 1855 1856 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 1857 if (sc->pci_fix_asyn_xfer & target_id) { 1858 AscSetChipSDTR(iot, ioh, 0, tid_no); 1859 sc->sdtr_data[tid_no] = 0; 1860 } 1861 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1862 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 1863 if (sc->pci_fix_asyn_xfer & target_id) { 1864 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1865 sc->sdtr_data[tid_no] = asyn_sdtr; 1866 } 1867 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1868 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 1869 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, 1870 tid_no, asyn_sdtr); 1871 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1872 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 1873 q_cntl |= ASC_QC_REQ_SENSE; 1874 1875 if (sc->init_sdtr & target_id) { 1876 sc->sdtr_done &= ~target_id; 1877 1878 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 1879 q_cntl |= ASC_QC_MSG_OUT; 1880 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 1881 (sc->max_sdtr_index - 1)], 1882 (sdtr_data & ASC_SYN_MAX_OFFSET)); 1883 } 1884 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1885 1886 tag_code = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE); 1887 tag_code &= 0xDC; 1888 1889 if ((sc->pci_fix_asyn_xfer & target_id) && 1890 !(sc->pci_fix_asyn_xfer_always & target_id)) { 1891 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | 1892 ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 1893 } 1894 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_TAG_CODE, tag_code); 1895 1896 q_status = AscReadLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS); 1897 q_status |= ASC_QS_READY | ASC_QS_BUSY; 1898 1899 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_STATUS, q_status); 1900 1901 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1902 scsi_busy &= ~target_id; 1903 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1904 1905 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1906 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 1907 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGOUT_BEG, 1908 (u_int16_t *) & out_msg, sizeof(EXT_MSG) >> 1); 1909 1910 if ((out_msg.msg_type == MS_EXTEND) && 1911 (out_msg.msg_len == MS_SDTR_LEN) && 1912 (out_msg.msg_req == MS_SDTR_CODE)) { 1913 sc->init_sdtr &= ~target_id; 1914 sc->sdtr_done &= ~target_id; 1915 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 1916 sc->sdtr_data[tid_no] = asyn_sdtr; 1917 } 1918 q_cntl &= ~ASC_QC_MSG_OUT; 1919 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 1920 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1921 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 1922 scsi_status = AscReadLramByte(iot, ioh, 1923 halt_q_addr + ASC_SCSIQ_SCSI_STATUS); 1924 cur_dvc_qng = AscReadLramByte(iot, ioh, target_ix + ASC_QADR_BEG); 1925 1926 if ((cur_dvc_qng > 0) && (sc->cur_dvc_qng[tid_no] > 0)) { 1927 scsi_busy = AscReadLramByte(iot, ioh, ASCV_SCSIBUSY_B); 1928 scsi_busy |= target_id; 1929 AscWriteLramByte(iot, ioh, ASCV_SCSIBUSY_B, scsi_busy); 1930 sc->queue_full_or_busy |= target_id; 1931 1932 if (scsi_status == SS_QUEUE_FULL) { 1933 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 1934 cur_dvc_qng -= 1; 1935 sc->max_dvc_qng[tid_no] = cur_dvc_qng; 1936 1937 AscWriteLramByte(iot, ioh, 1938 tid_no + ASCV_MAX_DVC_QNG_BEG, cur_dvc_qng); 1939 1940 #if ASC_QUEUE_FLOW_CONTROL 1941 if ((sc->device[tid_no] != NULL) && 1942 (sc->device[tid_no]->queue_curr_depth > cur_dvc_qng)) { 1943 sc->device[tid_no]->queue_curr_depth = cur_dvc_qng; 1944 } 1945 #endif /* ASC_QUEUE_FLOW_CONTROL */ 1946 } 1947 } 1948 } 1949 AscWriteLramWord(iot, ioh, ASCV_HALTCODE_W, 0); 1950 } 1951 return; 1952 } 1953 1954 1955 static int 1956 AscWaitTixISRDone(sc, target_ix) 1957 ASC_SOFTC *sc; 1958 u_int8_t target_ix; 1959 { 1960 u_int8_t cur_req; 1961 u_int8_t tid_no; 1962 int i = 0; 1963 1964 tid_no = ASC_TIX_TO_TID(target_ix); 1965 while (i++ < 10) { 1966 if ((cur_req = sc->cur_dvc_qng[tid_no]) == 0) 1967 break; 1968 1969 DvcSleepMilliSecond(1000L); 1970 if (sc->cur_dvc_qng[tid_no] == cur_req) 1971 break; 1972 } 1973 return (1); 1974 } 1975 1976 static int 1977 AscWaitISRDone(sc) 1978 ASC_SOFTC *sc; 1979 { 1980 int tid; 1981 1982 for (tid = 0; tid <= ASC_MAX_TID; tid++) 1983 AscWaitTixISRDone(sc, ASC_TID_TO_TIX(tid)); 1984 1985 return (1); 1986 } 1987 1988 1989 static u_int8_t 1990 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, max_dma_count) 1991 bus_space_tag_t iot; 1992 bus_space_handle_t ioh; 1993 u_int16_t q_addr; 1994 ASC_QDONE_INFO *scsiq; 1995 u_int32_t max_dma_count; 1996 { 1997 u_int16_t _val; 1998 u_int8_t sg_queue_cnt; 1999 2000 AscGetQDoneInfo(iot, ioh, q_addr + ASC_SCSIQ_DONE_INFO_BEG, scsiq); 2001 2002 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2003 scsiq->q_status = LO_BYTE(_val); 2004 scsiq->q_no = HI_BYTE(_val); 2005 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL); 2006 scsiq->cntl = LO_BYTE(_val); 2007 sg_queue_cnt = HI_BYTE(_val); 2008 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN); 2009 scsiq->sense_len = LO_BYTE(_val); 2010 scsiq->extra_bytes = HI_BYTE(_val); 2011 scsiq->remain_bytes = AscReadLramWord(iot, ioh, 2012 q_addr + ASC_SCSIQ_DW_REMAIN_XFER_CNT); 2013 scsiq->remain_bytes &= max_dma_count; 2014 2015 return (sg_queue_cnt); 2016 } 2017 2018 2019 static void 2020 AscGetQDoneInfo(iot, ioh, addr, scsiq) 2021 bus_space_tag_t iot; 2022 bus_space_handle_t ioh; 2023 u_int16_t addr; 2024 ASC_QDONE_INFO *scsiq; 2025 { 2026 u_int16_t val; 2027 2028 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2029 2030 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2031 scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh)); 2032 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2033 scsiq->d2.target_ix = LO_BYTE(val); 2034 scsiq->d2.flag = HI_BYTE(val); 2035 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2036 scsiq->d2.cdb_len = LO_BYTE(val); 2037 scsiq->d2.tag_code = HI_BYTE(val); 2038 scsiq->d2.vm_id = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2039 2040 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2041 scsiq->d3.done_stat = LO_BYTE(val); 2042 scsiq->d3.host_stat = HI_BYTE(val); 2043 val = ASC_GET_CHIP_LRAM_DATA(iot, ioh); 2044 scsiq->d3.scsi_stat = LO_BYTE(val); 2045 scsiq->d3.scsi_msg = HI_BYTE(val); 2046 } 2047 2048 2049 static void 2050 AscToggleIRQAct(iot, ioh) 2051 bus_space_tag_t iot; 2052 bus_space_handle_t ioh; 2053 { 2054 2055 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_IRQ_ACT); 2056 ASC_SET_CHIP_STATUS(iot, ioh, 0); 2057 } 2058 2059 2060 static void 2061 AscDisableInterrupt(iot, ioh) 2062 bus_space_tag_t iot; 2063 bus_space_handle_t ioh; 2064 { 2065 u_int16_t cfg; 2066 2067 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2068 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg & (~ASC_CFG0_HOST_INT_ON)); 2069 } 2070 2071 2072 static void 2073 AscEnableInterrupt(iot, ioh) 2074 bus_space_tag_t iot; 2075 bus_space_handle_t ioh; 2076 { 2077 u_int16_t cfg; 2078 2079 cfg = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2080 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg | ASC_CFG0_HOST_INT_ON); 2081 } 2082 2083 2084 static u_int8_t 2085 AscGetChipIRQ(iot, ioh, bus_type) 2086 bus_space_tag_t iot; 2087 bus_space_handle_t ioh; 2088 u_int16_t bus_type; 2089 { 2090 u_int16_t cfg_lsw; 2091 u_int8_t chip_irq; 2092 2093 2094 if (bus_type & ASC_IS_EISA) { 2095 /* 2096 * cfg_lsw = AscGetEisaChipCfg(iot, ioh); chip_irq = 2097 * ((cfg_lsw >> 8) & 0x07) + 10; if((chip_irq == 13) || 2098 * (chip_irq > 15)) return (0); return(chip_irq); 2099 */ 2100 } 2101 if ((bus_type & ASC_IS_VL) != 0) { 2102 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2103 chip_irq = (cfg_lsw >> 2) & 0x07; 2104 if ((chip_irq == 0) || 2105 (chip_irq == 4) || 2106 (chip_irq == 7)) { 2107 return (0); 2108 } 2109 return (chip_irq + (ASC_MIN_IRQ_NO - 1)); 2110 } 2111 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh); 2112 chip_irq = (cfg_lsw >> 2) & 0x03; 2113 if (chip_irq == 3) 2114 chip_irq += 2; 2115 return (chip_irq + ASC_MIN_IRQ_NO); 2116 } 2117 2118 2119 static u_int8_t 2120 AscSetChipIRQ(iot, ioh, irq_no, bus_type) 2121 bus_space_tag_t iot; 2122 bus_space_handle_t ioh; 2123 u_int8_t irq_no; 2124 u_int16_t bus_type; 2125 { 2126 u_int16_t cfg_lsw; 2127 2128 2129 if (bus_type & ASC_IS_VL) { 2130 if (irq_no) { 2131 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) 2132 irq_no = 0; 2133 else 2134 irq_no -= ASC_MIN_IRQ_NO - 1; 2135 } 2136 2137 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE3; 2138 cfg_lsw |= 0x0010; 2139 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2140 AscToggleIRQAct(iot, ioh); 2141 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFE0; 2142 cfg_lsw |= (irq_no & 0x07) << 2; 2143 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2144 AscToggleIRQAct(iot, ioh); 2145 2146 return (AscGetChipIRQ(iot, ioh, bus_type)); 2147 } 2148 if (bus_type & ASC_IS_ISA) { 2149 if (irq_no == 15) 2150 irq_no -= 2; 2151 irq_no -= ASC_MIN_IRQ_NO; 2152 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFF3; 2153 cfg_lsw |= (irq_no & 0x03) << 2; 2154 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2155 2156 return (AscGetChipIRQ(iot, ioh, bus_type)); 2157 } 2158 return (0); 2159 } 2160 2161 2162 static void 2163 AscAckInterrupt(iot, ioh) 2164 bus_space_tag_t iot; 2165 bus_space_handle_t ioh; 2166 { 2167 u_int8_t host_flag; 2168 u_int8_t risc_flag; 2169 u_int16_t loop; 2170 2171 2172 loop = 0; 2173 do { 2174 risc_flag = AscReadLramByte(iot, ioh, ASCV_RISC_FLAG_B); 2175 if (loop++ > 0x7FFF) 2176 break; 2177 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 2178 2179 host_flag = AscReadLramByte(iot, ioh, ASCV_HOST_FLAG_B) & 2180 (~ASC_HOST_FLAG_ACK_INT); 2181 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, 2182 host_flag | ASC_HOST_FLAG_ACK_INT); 2183 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2184 2185 loop = 0; 2186 while (ASC_GET_CHIP_STATUS(iot, ioh) & ASC_CSW_INT_PENDING) { 2187 ASC_SET_CHIP_STATUS(iot, ioh, ASC_CIW_INT_ACK); 2188 if (loop++ > 3) 2189 break; 2190 } 2191 2192 AscWriteLramByte(iot, ioh, ASCV_HOST_FLAG_B, host_flag); 2193 } 2194 2195 2196 static u_int32_t 2197 AscGetMaxDmaCount(bus_type) 2198 u_int16_t bus_type; 2199 { 2200 if (bus_type & ASC_IS_ISA) 2201 return (ASC_MAX_ISA_DMA_COUNT); 2202 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 2203 return (ASC_MAX_VL_DMA_COUNT); 2204 return (ASC_MAX_PCI_DMA_COUNT); 2205 } 2206 2207 2208 static u_int16_t 2209 AscGetIsaDmaChannel(iot, ioh) 2210 bus_space_tag_t iot; 2211 bus_space_handle_t ioh; 2212 { 2213 u_int16_t channel; 2214 2215 channel = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0x0003; 2216 if (channel == 0x03) 2217 return (0); 2218 else if (channel == 0x00) 2219 return (7); 2220 return (channel + 4); 2221 } 2222 2223 2224 static u_int16_t 2225 AscSetIsaDmaChannel(iot, ioh, dma_channel) 2226 bus_space_tag_t iot; 2227 bus_space_handle_t ioh; 2228 u_int16_t dma_channel; 2229 { 2230 u_int16_t cfg_lsw; 2231 u_int8_t value; 2232 2233 if ((dma_channel >= 5) && (dma_channel <= 7)) { 2234 if (dma_channel == 7) 2235 value = 0x00; 2236 else 2237 value = dma_channel - 4; 2238 cfg_lsw = ASC_GET_CHIP_CFG_LSW(iot, ioh) & 0xFFFC; 2239 cfg_lsw |= value; 2240 ASC_SET_CHIP_CFG_LSW(iot, ioh, cfg_lsw); 2241 return (AscGetIsaDmaChannel(iot, ioh)); 2242 } 2243 return (0); 2244 } 2245 2246 2247 static u_int8_t 2248 AscGetIsaDmaSpeed(iot, ioh) 2249 bus_space_tag_t iot; 2250 bus_space_handle_t ioh; 2251 { 2252 u_int8_t speed_value; 2253 2254 AscSetBank(iot, ioh, 1); 2255 speed_value = ASC_READ_CHIP_DMA_SPEED(iot, ioh); 2256 speed_value &= 0x07; 2257 AscSetBank(iot, ioh, 0); 2258 return (speed_value); 2259 } 2260 2261 2262 static u_int8_t 2263 AscSetIsaDmaSpeed(iot, ioh, speed_value) 2264 bus_space_tag_t iot; 2265 bus_space_handle_t ioh; 2266 u_int8_t speed_value; 2267 { 2268 speed_value &= 0x07; 2269 AscSetBank(iot, ioh, 1); 2270 ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, speed_value); 2271 AscSetBank(iot, ioh, 0); 2272 return (AscGetIsaDmaSpeed(iot, ioh)); 2273 } 2274 2275 2276 /******************************************************************************/ 2277 /* Messages routines */ 2278 /******************************************************************************/ 2279 2280 2281 static void 2282 AscHandleExtMsgIn(sc, halt_q_addr, q_cntl, target_id, tid_no, asyn_sdtr) 2283 ASC_SOFTC *sc; 2284 u_int16_t halt_q_addr; 2285 u_int8_t q_cntl; 2286 ASC_SCSI_BIT_ID_TYPE target_id; 2287 int tid_no; 2288 u_int8_t asyn_sdtr; 2289 { 2290 bus_space_tag_t iot = sc->sc_iot; 2291 bus_space_handle_t ioh = sc->sc_ioh; 2292 EXT_MSG ext_msg; 2293 u_int8_t sdtr_data; 2294 int sdtr_accept; 2295 2296 2297 AscMemWordCopyFromLram(iot, ioh, ASCV_MSGIN_BEG, 2298 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2299 2300 if (ext_msg.msg_type == MS_EXTEND && 2301 ext_msg.msg_req == MS_SDTR_CODE && 2302 ext_msg.msg_len == MS_SDTR_LEN) { 2303 sdtr_accept = TRUE; 2304 2305 if (ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET) { 2306 sdtr_accept = FALSE; 2307 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 2308 } 2309 if ((ext_msg.xfer_period < 2310 sc->sdtr_period_tbl[sc->host_init_sdtr_index]) || 2311 (ext_msg.xfer_period > 2312 sc->sdtr_period_tbl[sc->max_sdtr_index])) { 2313 sdtr_accept = FALSE; 2314 ext_msg.xfer_period = sc->sdtr_period_tbl[sc->host_init_sdtr_index]; 2315 } 2316 if (sdtr_accept) { 2317 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2318 ext_msg.req_ack_offset); 2319 if (sdtr_data == 0xFF) { 2320 q_cntl |= ASC_QC_MSG_OUT; 2321 sc->init_sdtr &= ~target_id; 2322 sc->sdtr_done &= ~target_id; 2323 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2324 sc->sdtr_data[tid_no] = asyn_sdtr; 2325 } 2326 } 2327 if (ext_msg.req_ack_offset == 0) { 2328 q_cntl &= ~ASC_QC_MSG_OUT; 2329 sc->init_sdtr &= ~target_id; 2330 sc->sdtr_done &= ~target_id; 2331 AscSetChipSDTR(iot, ioh, asyn_sdtr, tid_no); 2332 } else { 2333 if (sdtr_accept && (q_cntl & ASC_QC_MSG_OUT)) { 2334 q_cntl &= ~ASC_QC_MSG_OUT; 2335 sc->sdtr_done |= target_id; 2336 sc->init_sdtr |= target_id; 2337 sc->pci_fix_asyn_xfer &= ~target_id; 2338 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2339 ext_msg.req_ack_offset); 2340 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2341 sc->sdtr_data[tid_no] = sdtr_data; 2342 } else { 2343 q_cntl |= ASC_QC_MSG_OUT; 2344 AscMsgOutSDTR(sc, ext_msg.xfer_period, 2345 ext_msg.req_ack_offset); 2346 sc->pci_fix_asyn_xfer &= ~target_id; 2347 sdtr_data = AscCalSDTRData(sc, ext_msg.xfer_period, 2348 ext_msg.req_ack_offset); 2349 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no); 2350 sc->sdtr_data[tid_no] = sdtr_data; 2351 sc->sdtr_done |= target_id; 2352 sc->init_sdtr |= target_id; 2353 } 2354 } 2355 } else if (ext_msg.msg_type == MS_EXTEND && 2356 ext_msg.msg_req == MS_WDTR_CODE && 2357 ext_msg.msg_len == MS_WDTR_LEN) { 2358 ext_msg.wdtr_width = 0; 2359 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2360 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2361 q_cntl |= ASC_QC_MSG_OUT; 2362 } else { 2363 ext_msg.msg_type = M1_MSG_REJECT; 2364 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2365 (u_int16_t *) & ext_msg, sizeof(EXT_MSG) >> 1); 2366 q_cntl |= ASC_QC_MSG_OUT; 2367 } 2368 2369 AscWriteLramByte(iot, ioh, halt_q_addr + ASC_SCSIQ_B_CNTL, q_cntl); 2370 } 2371 2372 2373 static u_int8_t 2374 AscMsgOutSDTR(sc, sdtr_period, sdtr_offset) 2375 ASC_SOFTC *sc; 2376 u_int8_t sdtr_period; 2377 u_int8_t sdtr_offset; 2378 { 2379 bus_space_tag_t iot = sc->sc_iot; 2380 bus_space_handle_t ioh = sc->sc_ioh; 2381 EXT_MSG sdtr_buf; 2382 u_int8_t sdtr_period_index; 2383 2384 2385 sdtr_buf.msg_type = MS_EXTEND; 2386 sdtr_buf.msg_len = MS_SDTR_LEN; 2387 sdtr_buf.msg_req = MS_SDTR_CODE; 2388 sdtr_buf.xfer_period = sdtr_period; 2389 sdtr_offset &= ASC_SYN_MAX_OFFSET; 2390 sdtr_buf.req_ack_offset = sdtr_offset; 2391 if ((sdtr_period_index = AscGetSynPeriodIndex(sc, sdtr_period)) <= 2392 sc->max_sdtr_index) { 2393 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2394 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2395 return ((sdtr_period_index << 4) | sdtr_offset); 2396 } else { 2397 sdtr_buf.req_ack_offset = 0; 2398 AscMemWordCopyToLram(iot, ioh, ASCV_MSGOUT_BEG, 2399 (u_int16_t *) & sdtr_buf, sizeof(EXT_MSG) >> 1); 2400 return (0); 2401 } 2402 } 2403 2404 2405 /******************************************************************************/ 2406 /* SDTR routines */ 2407 /******************************************************************************/ 2408 2409 2410 static void 2411 AscSetChipSDTR(iot, ioh, sdtr_data, tid_no) 2412 bus_space_tag_t iot; 2413 bus_space_handle_t ioh; 2414 u_int8_t sdtr_data; 2415 u_int8_t tid_no; 2416 { 2417 AscSetChipSynRegAtID(iot, ioh, tid_no, sdtr_data); 2418 AscWriteLramByte(iot, ioh, tid_no + ASCV_SDTR_DONE_BEG, sdtr_data); 2419 } 2420 2421 2422 static u_int8_t 2423 AscCalSDTRData(sc, sdtr_period, syn_offset) 2424 ASC_SOFTC *sc; 2425 u_int8_t sdtr_period; 2426 u_int8_t syn_offset; 2427 { 2428 u_int8_t byte; 2429 u_int8_t sdtr_period_ix; 2430 2431 sdtr_period_ix = AscGetSynPeriodIndex(sc, sdtr_period); 2432 if (sdtr_period_ix > sc->max_sdtr_index) 2433 return (0xFF); 2434 2435 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 2436 return (byte); 2437 } 2438 2439 2440 static u_int8_t 2441 AscGetSynPeriodIndex(sc, syn_time) 2442 ASC_SOFTC *sc; 2443 u_int8_t syn_time; 2444 { 2445 u_int8_t *period_table; 2446 int max_index; 2447 int min_index; 2448 int i; 2449 2450 period_table = sc->sdtr_period_tbl; 2451 max_index = sc->max_sdtr_index; 2452 min_index = sc->host_init_sdtr_index; 2453 if ((syn_time <= period_table[max_index])) { 2454 for (i = min_index; i < (max_index - 1); i++) { 2455 if (syn_time <= period_table[i]) 2456 return (i); 2457 } 2458 2459 return (max_index); 2460 } else 2461 return (max_index + 1); 2462 } 2463 2464 2465 /******************************************************************************/ 2466 /* Queue routines */ 2467 /******************************************************************************/ 2468 2469 /* 2470 * Send a command to the board 2471 */ 2472 int 2473 AscExeScsiQueue(sc, scsiq) 2474 ASC_SOFTC *sc; 2475 ASC_SCSI_Q *scsiq; 2476 { 2477 bus_space_tag_t iot = sc->sc_iot; 2478 bus_space_handle_t ioh = sc->sc_ioh; 2479 ASC_SG_HEAD *sg_head = scsiq->sg_head; 2480 int retval; 2481 int n_q_required; 2482 int disable_syn_offset_one_fix; 2483 int i; 2484 u_int32_t addr; 2485 u_int16_t sg_entry_cnt = 0; 2486 u_int16_t sg_entry_cnt_minus_one = 0; 2487 u_int8_t target_ix; 2488 u_int8_t tid_no; 2489 u_int8_t sdtr_data; 2490 u_int8_t extra_bytes; 2491 u_int8_t scsi_cmd; 2492 u_int32_t data_cnt; 2493 2494 2495 scsiq->q1.q_no = 0; 2496 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) 2497 scsiq->q1.extra_bytes = 0; 2498 2499 retval = ASC_BUSY; 2500 target_ix = scsiq->q2.target_ix; 2501 tid_no = ASC_TIX_TO_TID(target_ix); 2502 n_q_required = 1; 2503 2504 if (scsiq->cdbptr[0] == SCSICMD_RequestSense) 2505 if ((sc->init_sdtr & scsiq->q1.target_id) != 0) { 2506 sc->sdtr_done &= ~scsiq->q1.target_id; 2507 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2508 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[(sdtr_data >> 4) & 2509 (sc->max_sdtr_index - 1)], 2510 sdtr_data & ASC_SYN_MAX_OFFSET); 2511 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); 2512 } 2513 /* 2514 * if there is just one segment into S/G list then 2515 * map it as it was a single request, filling 2516 * data_addr and data_cnt of ASC_SCSIQ structure. 2517 */ 2518 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2519 sg_entry_cnt = sg_head->entry_cnt; 2520 2521 if (sg_entry_cnt < 1) 2522 panic("AscExeScsiQueue: Queue with QC_SG_HEAD set but %d segs.", 2523 sg_entry_cnt); 2524 2525 if (sg_entry_cnt > ASC_MAX_SG_LIST) 2526 panic("AscExeScsiQueue: Queue with too many segs."); 2527 2528 if (sg_entry_cnt == 1) { 2529 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2530 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2531 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); 2532 } 2533 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 2534 } 2535 scsi_cmd = scsiq->cdbptr[0]; 2536 disable_syn_offset_one_fix = FALSE; 2537 if ((sc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 2538 !(sc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 2539 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { 2540 data_cnt = 0; 2541 for (i = 0; i < sg_entry_cnt; i++) 2542 data_cnt += sg_head->sg_list[i].bytes; 2543 } else { 2544 data_cnt = scsiq->q1.data_cnt; 2545 } 2546 2547 if (data_cnt != 0ul) { 2548 if (data_cnt < 512ul) { 2549 disable_syn_offset_one_fix = TRUE; 2550 } else { 2551 if (scsi_cmd == SCSICMD_Inquiry || 2552 scsi_cmd == SCSICMD_RequestSense || 2553 scsi_cmd == SCSICMD_ReadCapacity || 2554 scsi_cmd == SCSICMD_ReadTOC || 2555 scsi_cmd == SCSICMD_ModeSelect6 || 2556 scsi_cmd == SCSICMD_ModeSense6 || 2557 scsi_cmd == SCSICMD_ModeSelect10 || 2558 scsi_cmd == SCSICMD_ModeSense10) { 2559 disable_syn_offset_one_fix = TRUE; 2560 } 2561 } 2562 } 2563 } 2564 if (disable_syn_offset_one_fix) { 2565 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2566 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 2567 ASC_TAG_FLAG_DISABLE_DISCONNECT); 2568 } else { 2569 scsiq->q2.tag_code &= 0x23; 2570 } 2571 2572 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { 2573 if (sc->bug_fix_cntl) { 2574 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2575 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2576 addr = sg_head->sg_list[sg_entry_cnt_minus_one].addr + 2577 sg_head->sg_list[sg_entry_cnt_minus_one].bytes; 2578 extra_bytes = addr & 0x0003; 2579 if ((extra_bytes != 0) && 2580 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2581 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2582 scsiq->q1.extra_bytes = extra_bytes; 2583 sg_head->sg_list[sg_entry_cnt_minus_one].bytes -= 2584 extra_bytes; 2585 } 2586 } 2587 } 2588 } 2589 sg_head->entry_to_copy = sg_head->entry_cnt; 2590 n_q_required = AscSgListToQueue(sg_entry_cnt); 2591 if ((AscGetNumOfFreeQueue(sc, target_ix, n_q_required) >= n_q_required) 2592 || ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2593 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2594 } 2595 } else { 2596 if (sc->bug_fix_cntl) { 2597 if (sc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 2598 if ((scsi_cmd == SCSICMD_Read6) || (scsi_cmd == SCSICMD_Read10)) { 2599 addr = scsiq->q1.data_addr + scsiq->q1.data_cnt; 2600 extra_bytes = addr & 0x0003; 2601 if ((extra_bytes != 0) && 2602 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0)) { 2603 if ((scsiq->q1.data_cnt & 0x01FF) == 0) { 2604 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES; 2605 scsiq->q1.data_cnt -= extra_bytes; 2606 scsiq->q1.extra_bytes = extra_bytes; 2607 } 2608 } 2609 } 2610 } 2611 } 2612 n_q_required = 1; 2613 if ((AscGetNumOfFreeQueue(sc, target_ix, 1) >= 1) || 2614 ((scsiq->q1.cntl & ASC_QC_URGENT) != 0)) { 2615 retval = AscSendScsiQueue(sc, scsiq, n_q_required); 2616 } 2617 } 2618 2619 return (retval); 2620 } 2621 2622 2623 static int 2624 AscSendScsiQueue(sc, scsiq, n_q_required) 2625 ASC_SOFTC *sc; 2626 ASC_SCSI_Q *scsiq; 2627 u_int8_t n_q_required; 2628 { 2629 bus_space_tag_t iot = sc->sc_iot; 2630 bus_space_handle_t ioh = sc->sc_ioh; 2631 u_int8_t free_q_head; 2632 u_int8_t next_qp; 2633 u_int8_t tid_no; 2634 u_int8_t target_ix; 2635 int retval; 2636 2637 2638 target_ix = scsiq->q2.target_ix; 2639 tid_no = ASC_TIX_TO_TID(target_ix); 2640 retval = ASC_BUSY; 2641 free_q_head = ASC_GET_VAR_FREE_QHEAD(iot, ioh); 2642 2643 if ((next_qp = AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_q_required)) 2644 != ASC_QLINK_END) { 2645 if (n_q_required > 1) { 2646 sc->last_q_shortage = 0; 2647 scsiq->sg_head->queue_cnt = n_q_required - 1; 2648 } 2649 scsiq->q1.q_no = free_q_head; 2650 2651 if ((retval = AscPutReadySgListQueue(sc, scsiq, free_q_head)) == ASC_NOERROR) { 2652 ASC_PUT_VAR_FREE_QHEAD(iot, ioh, next_qp); 2653 sc->cur_total_qng += n_q_required; 2654 sc->cur_dvc_qng[tid_no]++; 2655 } 2656 } 2657 return (retval); 2658 } 2659 2660 2661 static int 2662 AscPutReadySgListQueue(sc, scsiq, q_no) 2663 ASC_SOFTC *sc; 2664 ASC_SCSI_Q *scsiq; 2665 u_int8_t q_no; 2666 { 2667 bus_space_tag_t iot = sc->sc_iot; 2668 bus_space_handle_t ioh = sc->sc_ioh; 2669 int retval; 2670 int i; 2671 ASC_SG_HEAD *sg_head; 2672 ASC_SG_LIST_Q scsi_sg_q; 2673 u_int32_t saved_data_addr; 2674 u_int32_t saved_data_cnt; 2675 u_int16_t sg_list_dwords; 2676 u_int16_t sg_index; 2677 u_int16_t sg_entry_cnt; 2678 u_int16_t q_addr; 2679 u_int8_t next_qp; 2680 2681 2682 saved_data_addr = scsiq->q1.data_addr; 2683 saved_data_cnt = scsiq->q1.data_cnt; 2684 2685 if ((sg_head = scsiq->sg_head) != 0) { 2686 scsiq->q1.data_addr = sg_head->sg_list[0].addr; 2687 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes; 2688 sg_entry_cnt = sg_head->entry_cnt - 1; 2689 if (sg_entry_cnt != 0) { 2690 q_addr = ASC_QNO_TO_QADDR(q_no); 2691 sg_index = 1; 2692 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 2693 scsi_sg_q.sg_head_qp = q_no; 2694 scsi_sg_q.cntl = ASC_QCSG_SG_XFER_LIST; 2695 2696 for (i = 0; i < sg_head->queue_cnt; i++) { 2697 scsi_sg_q.seq_no = i + 1; 2698 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 2699 sg_list_dwords = ASC_SG_LIST_PER_Q * 2; 2700 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 2701 if (i == 0) { 2702 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q; 2703 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q; 2704 } else { 2705 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 2706 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1; 2707 } 2708 } else { 2709 scsi_sg_q.cntl |= ASC_QCSG_SG_XFER_END; 2710 sg_list_dwords = sg_entry_cnt << 1; 2711 if (i == 0) { 2712 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 2713 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt; 2714 } else { 2715 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 2716 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 2717 } 2718 2719 sg_entry_cnt = 0; 2720 } 2721 2722 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2723 scsi_sg_q.q_no = next_qp; 2724 q_addr = ASC_QNO_TO_QADDR(next_qp); 2725 2726 /* 2727 * Tell the board how many entries are in the S/G list 2728 */ 2729 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 2730 (u_int16_t *) & scsi_sg_q, 2731 sizeof(ASC_SG_LIST_Q) >> 1); 2732 /* 2733 * Tell the board the addresses of the S/G list segments 2734 */ 2735 AscMemDWordCopyToLram(iot, ioh, q_addr + ASC_SGQ_LIST_BEG, 2736 (u_int32_t *) & sg_head->sg_list[sg_index], 2737 sg_list_dwords); 2738 sg_index += ASC_SG_LIST_PER_Q; 2739 } 2740 } 2741 } 2742 retval = AscPutReadyQueue(sc, scsiq, q_no); 2743 scsiq->q1.data_addr = saved_data_addr; 2744 scsiq->q1.data_cnt = saved_data_cnt; 2745 return (retval); 2746 } 2747 2748 2749 static int 2750 AscPutReadyQueue(sc, scsiq, q_no) 2751 ASC_SOFTC *sc; 2752 ASC_SCSI_Q *scsiq; 2753 u_int8_t q_no; 2754 { 2755 bus_space_tag_t iot = sc->sc_iot; 2756 bus_space_handle_t ioh = sc->sc_ioh; 2757 u_int16_t q_addr; 2758 u_int8_t tid_no; 2759 u_int8_t sdtr_data; 2760 u_int8_t syn_period_ix; 2761 u_int8_t syn_offset; 2762 2763 2764 if (((sc->init_sdtr & scsiq->q1.target_id) != 0) && 2765 ((sc->sdtr_done & scsiq->q1.target_id) == 0)) { 2766 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 2767 sdtr_data = ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, tid_no); 2768 syn_period_ix = (sdtr_data >> 4) & (sc->max_sdtr_index - 1); 2769 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 2770 AscMsgOutSDTR(sc, sc->sdtr_period_tbl[syn_period_ix], syn_offset); 2771 scsiq->q1.cntl |= ASC_QC_MSG_OUT; 2772 } 2773 q_addr = ASC_QNO_TO_QADDR(q_no); 2774 2775 if ((scsiq->q1.target_id & sc->use_tagged_qng) == 0) { 2776 scsiq->q2.tag_code &= ~M2_QTAG_MSG_SIMPLE; 2777 } 2778 scsiq->q1.status = ASC_QS_FREE; 2779 AscMemWordCopyToLram(iot, ioh, q_addr + ASC_SCSIQ_CDB_BEG, 2780 (u_int16_t *) scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 2781 2782 AscPutSCSIQ(iot, ioh, q_addr + ASC_SCSIQ_CPY_BEG, scsiq); 2783 2784 /* 2785 * Let's start the command 2786 */ 2787 AscWriteLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 2788 (scsiq->q1.q_no << 8) | ASC_QS_READY); 2789 2790 return (ASC_NOERROR); 2791 } 2792 2793 2794 static void 2795 AscPutSCSIQ(iot, ioh, addr, scsiq) 2796 bus_space_tag_t iot; 2797 bus_space_handle_t ioh; 2798 u_int16_t addr; 2799 ASC_SCSI_Q *scsiq; 2800 { 2801 u_int16_t val; 2802 2803 2804 ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr); 2805 2806 /* ASC_SCSIQ_1 */ 2807 val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt); 2808 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2809 val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun); 2810 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2811 val = LO_WORD(scsiq->q1.data_addr); 2812 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2813 val = HI_WORD(scsiq->q1.data_addr); 2814 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2815 val = LO_WORD(scsiq->q1.data_cnt); 2816 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2817 val = HI_WORD(scsiq->q1.data_cnt); 2818 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2819 val = LO_WORD(scsiq->q1.sense_addr); 2820 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2821 val = HI_WORD(scsiq->q1.sense_addr); 2822 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2823 val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes); 2824 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2825 2826 /* ASC_SCSIQ_2 */ 2827 val = LO_WORD(scsiq->q2.ccb_ptr); 2828 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2829 val = HI_WORD(scsiq->q2.ccb_ptr); 2830 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2831 val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag); 2832 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2833 val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code); 2834 ASC_SET_CHIP_LRAM_DATA(iot, ioh, val); 2835 ASC_SET_CHIP_LRAM_DATA(iot, ioh, scsiq->q2.vm_id); 2836 } 2837 2838 2839 static int 2840 AscSgListToQueue(sg_list) 2841 int sg_list; 2842 { 2843 int n_sg_list_qs; 2844 2845 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 2846 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 2847 n_sg_list_qs++; 2848 2849 return (n_sg_list_qs + 1); 2850 } 2851 2852 2853 static u_int 2854 AscGetNumOfFreeQueue(sc, target_ix, n_qs) 2855 ASC_SOFTC *sc; 2856 u_int8_t target_ix; 2857 u_int8_t n_qs; 2858 { 2859 u_int cur_used_qs; 2860 u_int cur_free_qs; 2861 2862 2863 if (n_qs == 1) { 2864 cur_used_qs = sc->cur_total_qng + 2865 sc->last_q_shortage + 2866 ASC_MIN_FREE_Q; 2867 } else { 2868 cur_used_qs = sc->cur_total_qng + ASC_MIN_FREE_Q; 2869 } 2870 2871 if ((cur_used_qs + n_qs) <= sc->max_total_qng) { 2872 cur_free_qs = sc->max_total_qng - cur_used_qs; 2873 return (cur_free_qs); 2874 } 2875 if (n_qs > 1) 2876 if ((n_qs > sc->last_q_shortage) && 2877 (n_qs <= (sc->max_total_qng - ASC_MIN_FREE_Q))) { 2878 sc->last_q_shortage = n_qs; 2879 } 2880 return (0); 2881 } 2882 2883 2884 static u_int8_t 2885 AscAllocFreeQueue(iot, ioh, free_q_head) 2886 bus_space_tag_t iot; 2887 bus_space_handle_t ioh; 2888 u_int8_t free_q_head; 2889 { 2890 u_int16_t q_addr; 2891 u_int8_t next_qp; 2892 u_int8_t q_status; 2893 2894 2895 q_addr = ASC_QNO_TO_QADDR(free_q_head); 2896 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2897 next_qp = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_FWD); 2898 if (((q_status & ASC_QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 2899 return (next_qp); 2900 2901 return (ASC_QLINK_END); 2902 } 2903 2904 2905 static u_int8_t 2906 AscAllocMultipleFreeQueue(iot, ioh, free_q_head, n_free_q) 2907 bus_space_tag_t iot; 2908 bus_space_handle_t ioh; 2909 u_int8_t free_q_head; 2910 u_int8_t n_free_q; 2911 { 2912 u_int8_t i; 2913 2914 for (i = 0; i < n_free_q; i++) { 2915 free_q_head = AscAllocFreeQueue(iot, ioh, free_q_head); 2916 if (free_q_head == ASC_QLINK_END) 2917 break; 2918 } 2919 2920 return (free_q_head); 2921 } 2922 2923 2924 static int 2925 AscStopQueueExe(iot, ioh) 2926 bus_space_tag_t iot; 2927 bus_space_handle_t ioh; 2928 { 2929 int count = 0; 2930 2931 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) == 0) { 2932 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_REQ_RISC_STOP); 2933 do { 2934 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) & 2935 ASC_STOP_ACK_RISC_STOP) 2936 return (1); 2937 2938 DvcSleepMilliSecond(100); 2939 } while (count++ < 20); 2940 } 2941 return (0); 2942 } 2943 2944 2945 static void 2946 AscStartQueueExe(iot, ioh) 2947 bus_space_tag_t iot; 2948 bus_space_handle_t ioh; 2949 { 2950 2951 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) 2952 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, 0); 2953 } 2954 2955 2956 static void 2957 AscCleanUpBusyQueue(iot, ioh) 2958 bus_space_tag_t iot; 2959 bus_space_handle_t ioh; 2960 { 2961 int count = 0; 2962 u_int8_t stop_code; 2963 2964 2965 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 2966 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_BUSY_Q); 2967 do { 2968 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 2969 if ((stop_code & ASC_STOP_CLEAN_UP_BUSY_Q) == 0) 2970 break; 2971 2972 DvcSleepMilliSecond(100); 2973 } while (count++ < 20); 2974 } 2975 } 2976 2977 2978 static int 2979 _AscWaitQDone(iot, ioh, scsiq) 2980 bus_space_tag_t iot; 2981 bus_space_handle_t ioh; 2982 ASC_SCSI_Q *scsiq; 2983 { 2984 u_int16_t q_addr; 2985 u_int8_t q_status; 2986 int count = 0; 2987 2988 while (scsiq->q1.q_no == 0); 2989 2990 q_addr = ASC_QNO_TO_QADDR(scsiq->q1.q_no); 2991 do { 2992 q_status = AscReadLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS); 2993 DvcSleepMilliSecond(100L); 2994 if (count++ > 30) 2995 return (0); 2996 2997 } while ((q_status & ASC_QS_READY) != 0); 2998 2999 return (1); 3000 } 3001 3002 3003 static int 3004 AscCleanUpDiscQueue(iot, ioh) 3005 bus_space_tag_t iot; 3006 bus_space_handle_t ioh; 3007 { 3008 int count; 3009 u_int8_t stop_code; 3010 3011 count = 0; 3012 if (AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B) != 0) { 3013 AscWriteLramByte(iot, ioh, ASCV_STOP_CODE_B, ASC_STOP_CLEAN_UP_DISC_Q); 3014 do { 3015 stop_code = AscReadLramByte(iot, ioh, ASCV_STOP_CODE_B); 3016 if ((stop_code & ASC_STOP_CLEAN_UP_DISC_Q) == 0) 3017 break; 3018 3019 DvcSleepMilliSecond(100); 3020 } while (count++ < 20); 3021 } 3022 return (1); 3023 } 3024 3025 3026 /******************************************************************************/ 3027 /* Abort and Reset CCB routines */ 3028 /******************************************************************************/ 3029 3030 3031 int 3032 AscAbortCCB(sc, ccb) 3033 ASC_SOFTC *sc; 3034 ADV_CCB *ccb; 3035 { 3036 bus_space_tag_t iot = sc->sc_iot; 3037 bus_space_handle_t ioh = sc->sc_ioh; 3038 int retval; 3039 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3040 3041 3042 retval = -1; 3043 saved_unit_not_ready = sc->unit_not_ready; 3044 sc->unit_not_ready = 0xFF; 3045 AscWaitISRDone(sc); 3046 if (AscStopQueueExe(iot, ioh) == 1) { 3047 if (AscRiscHaltedAbortCCB(sc, ccb) == 1) { 3048 retval = 1; 3049 AscCleanUpBusyQueue(iot, ioh); 3050 AscStartQueueExe(iot, ioh); 3051 } else { 3052 retval = 0; 3053 AscStartQueueExe(iot, ioh); 3054 } 3055 } 3056 sc->unit_not_ready = saved_unit_not_ready; 3057 3058 return (retval); 3059 } 3060 3061 3062 static int 3063 AscRiscHaltedAbortCCB(sc, ccb) 3064 ASC_SOFTC *sc; 3065 ADV_CCB *ccb; 3066 { 3067 bus_space_tag_t iot = sc->sc_iot; 3068 bus_space_handle_t ioh = sc->sc_ioh; 3069 u_int16_t q_addr; 3070 u_int8_t q_no; 3071 ASC_QDONE_INFO scsiq_buf; 3072 ASC_QDONE_INFO *scsiq; 3073 ASC_ISR_CALLBACK asc_isr_callback; 3074 int last_int_level; 3075 3076 3077 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3078 last_int_level = DvcEnterCritical(); 3079 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3080 3081 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3082 q_addr = ASC_QNO_TO_QADDR(q_no); 3083 scsiq->d2.ccb_ptr = AscReadLramDWord(iot, ioh, 3084 q_addr + ASC_SCSIQ_D_CCBPTR); 3085 if (adv_ccb_phys_kv(sc, scsiq->d2.ccb_ptr) == ccb) { 3086 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3087 if (((scsiq->q_status & ASC_QS_READY) != 0) 3088 && ((scsiq->q_status & ASC_QS_ABORTED) == 0) 3089 && ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3090 scsiq->q_status |= ASC_QS_ABORTED; 3091 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3092 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3093 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3094 scsiq->q_status); 3095 (*asc_isr_callback) (sc, scsiq); 3096 return (1); 3097 } 3098 } 3099 } 3100 3101 DvcLeaveCritical(last_int_level); 3102 return (0); 3103 } 3104 3105 3106 static int 3107 AscRiscHaltedAbortTIX(sc, target_ix) 3108 ASC_SOFTC *sc; 3109 u_int8_t target_ix; 3110 { 3111 bus_space_tag_t iot = sc->sc_iot; 3112 bus_space_handle_t ioh = sc->sc_ioh; 3113 u_int16_t q_addr; 3114 u_int8_t q_no; 3115 ASC_QDONE_INFO scsiq_buf; 3116 ASC_QDONE_INFO *scsiq; 3117 ASC_ISR_CALLBACK asc_isr_callback; 3118 int last_int_level; 3119 3120 3121 asc_isr_callback = (ASC_ISR_CALLBACK) sc->isr_callback; 3122 last_int_level = DvcEnterCritical(); 3123 scsiq = (ASC_QDONE_INFO *) & scsiq_buf; 3124 for (q_no = ASC_MIN_ACTIVE_QNO; q_no <= sc->max_total_qng; q_no++) { 3125 q_addr = ASC_QNO_TO_QADDR(q_no); 3126 _AscCopyLramScsiDoneQ(iot, ioh, q_addr, scsiq, sc->max_dma_count); 3127 if (((scsiq->q_status & ASC_QS_READY) != 0) && 3128 ((scsiq->q_status & ASC_QS_ABORTED) == 0) && 3129 ((scsiq->cntl & ASC_QCSG_SG_XFER_LIST) == 0)) { 3130 if (scsiq->d2.target_ix == target_ix) { 3131 scsiq->q_status |= ASC_QS_ABORTED; 3132 scsiq->d3.done_stat = ASC_QD_ABORTED_BY_HOST; 3133 AscWriteLramDWord(iot, ioh, q_addr + ASC_SCSIQ_D_CCBPTR, 0L); 3134 AscWriteLramByte(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS, 3135 scsiq->q_status); 3136 (*asc_isr_callback) (sc, scsiq); 3137 } 3138 } 3139 } 3140 DvcLeaveCritical(last_int_level); 3141 return (1); 3142 } 3143 3144 3145 /* 3146 * AscResetDevice calls _AscWaitQDone which requires interrupt enabled, 3147 * so we cannot use this function with the actual NetBSD SCSI layer 3148 * because at boot time interrupts are disabled. 3149 */ 3150 int 3151 AscResetDevice(sc, target_ix) 3152 ASC_SOFTC *sc; 3153 u_char target_ix; 3154 { 3155 bus_space_tag_t iot = sc->sc_iot; 3156 bus_space_handle_t ioh = sc->sc_ioh; 3157 int retval; 3158 u_int8_t tid_no; 3159 ASC_SCSI_BIT_ID_TYPE target_id; 3160 int i; 3161 ASC_SCSI_REQ_Q scsiq_buf; 3162 ASC_SCSI_REQ_Q *scsiq; 3163 u_int8_t *buf; 3164 ASC_SCSI_BIT_ID_TYPE saved_unit_not_ready; 3165 3166 3167 tid_no = ASC_TIX_TO_TID(target_ix); 3168 target_id = ASC_TID_TO_TARGET_ID(tid_no); 3169 saved_unit_not_ready = sc->unit_not_ready; 3170 sc->unit_not_ready = target_id; 3171 retval = ASC_ERROR; 3172 3173 AscWaitTixISRDone(sc, target_ix); 3174 3175 if (AscStopQueueExe(iot, ioh) == 1) { 3176 if (AscRiscHaltedAbortTIX(sc, target_ix) == 1) { 3177 AscCleanUpBusyQueue(iot, ioh); 3178 AscStartQueueExe(iot, ioh); 3179 AscWaitTixISRDone(sc, target_ix); 3180 retval = ASC_NOERROR; 3181 scsiq = (ASC_SCSI_REQ_Q *) & scsiq_buf; 3182 buf = (u_char *) & scsiq_buf; 3183 for (i = 0; i < sizeof(ASC_SCSI_REQ_Q); i++) 3184 *buf++ = 0x00; 3185 scsiq->q1.status = (u_char) ASC_QS_READY; 3186 scsiq->q2.cdb_len = 6; 3187 scsiq->q2.tag_code = M2_QTAG_MSG_SIMPLE; 3188 scsiq->q1.target_id = target_id; 3189 scsiq->q2.target_ix = ASC_TIDLUN_TO_IX(tid_no, 0); 3190 scsiq->cdbptr = scsiq->cdb; 3191 scsiq->q1.cntl = ASC_QC_NO_CALLBACK | ASC_QC_MSG_OUT | ASC_QC_URGENT; 3192 AscWriteLramByte(iot, ioh, ASCV_MSGOUT_BEG, M1_BUS_DVC_RESET); 3193 sc->unit_not_ready &= ~target_id; 3194 sc->sdtr_done |= target_id; 3195 if (AscExeScsiQueue(sc, (ASC_SCSI_Q *) scsiq) == ASC_NOERROR) { 3196 sc->unit_not_ready = target_id; 3197 DvcSleepMilliSecond(1000); 3198 _AscWaitQDone(iot, ioh, (ASC_SCSI_Q *) scsiq); 3199 if (AscStopQueueExe(iot, ioh) == ASC_NOERROR) { 3200 AscCleanUpDiscQueue(iot, ioh); 3201 AscStartQueueExe(iot, ioh); 3202 if (sc->pci_fix_asyn_xfer & target_id) 3203 AscSetRunChipSynRegAtID(iot, ioh, tid_no, 3204 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3205 AscWaitTixISRDone(sc, target_ix); 3206 } 3207 } else 3208 retval = ASC_BUSY; 3209 sc->sdtr_done &= ~target_id; 3210 } else { 3211 retval = ASC_ERROR; 3212 AscStartQueueExe(iot, ioh); 3213 } 3214 } 3215 sc->unit_not_ready = saved_unit_not_ready; 3216 return (retval); 3217 } 3218 3219 3220 int 3221 AscResetBus(sc) 3222 ASC_SOFTC *sc; 3223 { 3224 bus_space_tag_t iot = sc->sc_iot; 3225 bus_space_handle_t ioh = sc->sc_ioh; 3226 int retval; 3227 int i; 3228 3229 3230 sc->unit_not_ready = 0xFF; 3231 retval = ASC_NOERROR; 3232 3233 AscWaitISRDone(sc); 3234 AscStopQueueExe(iot, ioh); 3235 sc->sdtr_done = 0; 3236 AscResetChipAndScsiBus(iot, ioh); 3237 DvcSleepMilliSecond((u_long) ((u_int16_t) sc->scsi_reset_wait * 1000)); 3238 AscReInitLram(sc); 3239 for (i = 0; i <= ASC_MAX_TID; i++) { 3240 sc->cur_dvc_qng[i] = 0; 3241 if (sc->pci_fix_asyn_xfer & (ASC_SCSI_BIT_ID_TYPE) (0x01 << i)) 3242 AscSetChipSynRegAtID(iot, ioh, i, ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3243 } 3244 3245 ASC_SET_PC_ADDR(iot, ioh, ASC_MCODE_START_ADDR); 3246 if (ASC_GET_PC_ADDR(iot, ioh) != ASC_MCODE_START_ADDR) 3247 retval = ASC_ERROR; 3248 3249 if (AscStartChip(iot, ioh) == 0) 3250 retval = ASC_ERROR; 3251 3252 AscStartQueueExe(iot, ioh); 3253 sc->unit_not_ready = 0; 3254 sc->queue_full_or_busy = 0; 3255 return (retval); 3256 } 3257 3258 3259 /******************************************************************************/ 3260 /* Error Handling routines */ 3261 /******************************************************************************/ 3262 3263 3264 static int 3265 AscSetLibErrorCode(sc, err_code) 3266 ASC_SOFTC *sc; 3267 u_int16_t err_code; 3268 { 3269 /* 3270 * if(sc->err_code == 0) { sc->err_code = err_code; 3271 */ AscWriteLramWord(sc->sc_iot, sc->sc_ioh, ASCV_ASCDVC_ERR_CODE_W, 3272 err_code); 3273 /* 3274 * } 3275 */ 3276 return (err_code); 3277 } 3278 3279 3280 /******************************************************************************/ 3281 /* Handle bugged borads routines */ 3282 /******************************************************************************/ 3283 3284 3285 void 3286 AscInquiryHandling(sc, tid_no, inq) 3287 ASC_SOFTC *sc; 3288 u_int8_t tid_no; 3289 ASC_SCSI_INQUIRY *inq; 3290 { 3291 bus_space_tag_t iot = sc->sc_iot; 3292 bus_space_handle_t ioh = sc->sc_ioh; 3293 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no); 3294 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng; 3295 3296 3297 orig_init_sdtr = sc->init_sdtr; 3298 orig_use_tagged_qng = sc->use_tagged_qng; 3299 3300 sc->init_sdtr &= ~tid_bit; 3301 sc->can_tagged_qng &= ~tid_bit; 3302 sc->use_tagged_qng &= ~tid_bit; 3303 3304 if (inq->byte3.rsp_data_fmt >= 2 || inq->byte2.ansi_apr_ver >= 2) { 3305 if ((sc->sdtr_enable & tid_bit) && inq->byte7.Sync) 3306 sc->init_sdtr |= tid_bit; 3307 3308 if ((sc->cmd_qng_enabled & tid_bit) && inq->byte7.CmdQue) 3309 if (AscTagQueuingSafe(inq)) { 3310 sc->use_tagged_qng |= tid_bit; 3311 sc->can_tagged_qng |= tid_bit; 3312 } 3313 } 3314 if (orig_use_tagged_qng != sc->use_tagged_qng) { 3315 AscWriteLramByte(iot, ioh, ASCV_DISC_ENABLE_B, 3316 sc->disc_enable); 3317 AscWriteLramByte(iot, ioh, ASCV_USE_TAGGED_QNG_B, 3318 sc->use_tagged_qng); 3319 AscWriteLramByte(iot, ioh, ASCV_CAN_TAGGED_QNG_B, 3320 sc->can_tagged_qng); 3321 3322 sc->max_dvc_qng[tid_no] = 3323 sc->max_tag_qng[tid_no]; 3324 AscWriteLramByte(iot, ioh, ASCV_MAX_DVC_QNG_BEG + tid_no, 3325 sc->max_dvc_qng[tid_no]); 3326 } 3327 if (orig_init_sdtr != sc->init_sdtr) 3328 AscAsyncFix(sc, tid_no, inq); 3329 } 3330 3331 3332 static int 3333 AscTagQueuingSafe(inq) 3334 ASC_SCSI_INQUIRY *inq; 3335 { 3336 if ((inq->add_len >= 32) && 3337 (AscCompareString(inq->vendor_id, "QUANTUM XP34301", 15) == 0) && 3338 (AscCompareString(inq->product_rev_level, "1071", 4) == 0)) { 3339 return 0; 3340 } 3341 return 1; 3342 } 3343 3344 3345 static void 3346 AscAsyncFix(sc, tid_no, inq) 3347 ASC_SOFTC *sc; 3348 u_int8_t tid_no; 3349 ASC_SCSI_INQUIRY *inq; 3350 { 3351 u_int8_t dvc_type; 3352 ASC_SCSI_BIT_ID_TYPE tid_bits; 3353 3354 3355 dvc_type = inq->byte0.peri_dvc_type; 3356 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no); 3357 3358 if (sc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) { 3359 if (!(sc->init_sdtr & tid_bits)) { 3360 if ((dvc_type == SCSI_TYPE_CDROM) && 3361 (AscCompareString(inq->vendor_id, "HP ", 3) == 0)) { 3362 sc->pci_fix_asyn_xfer_always |= tid_bits; 3363 } 3364 sc->pci_fix_asyn_xfer |= tid_bits; 3365 if ((dvc_type == SCSI_TYPE_PROC) || 3366 (dvc_type == SCSI_TYPE_SCANNER)) { 3367 sc->pci_fix_asyn_xfer &= ~tid_bits; 3368 } 3369 if ((dvc_type == SCSI_TYPE_SASD) && 3370 (AscCompareString(inq->vendor_id, "TANDBERG", 8) == 0) && 3371 (AscCompareString(inq->product_id, " TDC 36", 7) == 0)) { 3372 sc->pci_fix_asyn_xfer &= ~tid_bits; 3373 } 3374 if ((dvc_type == SCSI_TYPE_SASD) && 3375 (AscCompareString(inq->vendor_id, "WANGTEK ", 8) == 0)) { 3376 sc->pci_fix_asyn_xfer &= ~tid_bits; 3377 } 3378 if ((dvc_type == SCSI_TYPE_CDROM) && 3379 (AscCompareString(inq->vendor_id, "NEC ", 8) == 0) && 3380 (AscCompareString(inq->product_id, "CD-ROM DRIVE ", 16) == 0)) { 3381 sc->pci_fix_asyn_xfer &= ~tid_bits; 3382 } 3383 if ((dvc_type == SCSI_TYPE_CDROM) && 3384 (AscCompareString(inq->vendor_id, "YAMAHA", 6) == 0) && 3385 (AscCompareString(inq->product_id, "CDR400", 6) == 0)) { 3386 sc->pci_fix_asyn_xfer &= ~tid_bits; 3387 } 3388 if (sc->pci_fix_asyn_xfer & tid_bits) { 3389 AscSetRunChipSynRegAtID(sc->sc_iot, sc->sc_ioh, tid_no, 3390 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 3391 } 3392 } 3393 } 3394 } 3395 3396 3397 /******************************************************************************/ 3398 /* Miscellaneous routines */ 3399 /******************************************************************************/ 3400 3401 3402 static int 3403 AscCompareString(str1, str2, len) 3404 u_char *str1; 3405 u_char *str2; 3406 int len; 3407 { 3408 int i; 3409 int diff; 3410 3411 for (i = 0; i < len; i++) { 3412 diff = (int) (str1[i] - str2[i]); 3413 if (diff != 0) 3414 return (diff); 3415 } 3416 3417 return (0); 3418 } 3419 3420 3421 /******************************************************************************/ 3422 /* Device oriented routines */ 3423 /******************************************************************************/ 3424 3425 3426 static int 3427 DvcEnterCritical(void) 3428 { 3429 int s; 3430 3431 s = splbio(); 3432 return (s); 3433 } 3434 3435 3436 static void 3437 DvcLeaveCritical(s) 3438 int s; 3439 { 3440 3441 splx(s); 3442 } 3443 3444 3445 static void 3446 DvcSleepMilliSecond(n) 3447 u_int32_t n; 3448 { 3449 3450 DELAY(n * 1000); 3451 } 3452 3453 #ifdef UNUSED 3454 static void 3455 DvcDelayMicroSecond(n) 3456 u_int32_t n; 3457 { 3458 3459 DELAY(n); 3460 } 3461 #endif 3462 3463 static void 3464 DvcDelayNanoSecond(n) 3465 u_int32_t n; 3466 { 3467 3468 DELAY((n + 999) / 1000); 3469 } 3470