xref: /netbsd-src/sys/dev/i2c/spdmem_i2c.c (revision a02f62015bc67db27d46dce620454668f6a1869b)
1*a02f6201Spgoyette /* $NetBSD: spdmem_i2c.c,v 1.26 2022/03/30 00:06:50 pgoyette Exp $ */
2d41a3cefSpgoyette 
3d41a3cefSpgoyette /*
4d41a3cefSpgoyette  * Copyright (c) 2007 Nicolas Joly
5d41a3cefSpgoyette  * Copyright (c) 2007 Paul Goyette
6d41a3cefSpgoyette  * Copyright (c) 2007 Tobias Nygren
75fcead8fSmlelstv  * Copyright (c) 2015 Michael van Elst
8d41a3cefSpgoyette  * All rights reserved.
9d41a3cefSpgoyette  *
10d41a3cefSpgoyette  * Redistribution and use in source and binary forms, with or without
11d41a3cefSpgoyette  * modification, are permitted provided that the following conditions
12d41a3cefSpgoyette  * are met:
13d41a3cefSpgoyette  * 1. Redistributions of source code must retain the above copyright
14d41a3cefSpgoyette  *    notice, this list of conditions and the following disclaimer.
15d41a3cefSpgoyette  * 2. Redistributions in binary form must reproduce the above copyright
16d41a3cefSpgoyette  *    notice, this list of conditions and the following disclaimer in the
17d41a3cefSpgoyette  *    documentation and/or other materials provided with the distribution.
18d41a3cefSpgoyette  * 3. The name of the author may not be used to endorse or promote products
19d41a3cefSpgoyette  *    derived from this software without specific prior written permission.
20d41a3cefSpgoyette  *
21d41a3cefSpgoyette  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS
22d41a3cefSpgoyette  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23d41a3cefSpgoyette  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24d41a3cefSpgoyette  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25d41a3cefSpgoyette  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26d41a3cefSpgoyette  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27d41a3cefSpgoyette  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28d41a3cefSpgoyette  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29d41a3cefSpgoyette  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30d41a3cefSpgoyette  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31d41a3cefSpgoyette  * POSSIBILITY OF SUCH DAMAGE.
32d41a3cefSpgoyette  */
33d41a3cefSpgoyette 
34d41a3cefSpgoyette /*
35d41a3cefSpgoyette  * Serial Presence Detect (SPD) memory identification
365fcead8fSmlelstv  *
375fcead8fSmlelstv  * JEDEC standard No. 21-C
385fcead8fSmlelstv  * JEDEC document 4_01_06R24
395fcead8fSmlelstv  * - Definitions of the EE1004-v 4 Kbit Serial Presence Detect EEPROM [...]
40d41a3cefSpgoyette  */
41d41a3cefSpgoyette 
42d41a3cefSpgoyette #include <sys/cdefs.h>
43*a02f6201Spgoyette __KERNEL_RCSID(0, "$NetBSD: spdmem_i2c.c,v 1.26 2022/03/30 00:06:50 pgoyette Exp $");
44d41a3cefSpgoyette 
45d41a3cefSpgoyette #include <sys/param.h>
46d41a3cefSpgoyette #include <sys/device.h>
47d41a3cefSpgoyette #include <sys/endian.h>
48e3bc45f1Spgoyette #include <sys/module.h>
49d41a3cefSpgoyette #include <sys/sysctl.h>
50d41a3cefSpgoyette #include <machine/bswap.h>
51d41a3cefSpgoyette 
52d41a3cefSpgoyette #include <dev/i2c/i2cvar.h>
53d41a3cefSpgoyette #include <dev/ic/spdmemreg.h>
54d41a3cefSpgoyette #include <dev/ic/spdmemvar.h>
55d41a3cefSpgoyette 
56d41a3cefSpgoyette /* Constants for matching i2c bus address */
575fcead8fSmlelstv #define SPDMEM_I2C_ADDRMASK 0xfff8
58d41a3cefSpgoyette #define SPDMEM_I2C_ADDR     0x50
595fcead8fSmlelstv #define SPDCTL_I2C_ADDR     0x30
605fcead8fSmlelstv 
615fcead8fSmlelstv /* set write protection */
625fcead8fSmlelstv #define SPDCTL_SWP0         (SPDCTL_I2C_ADDR + 1)
635fcead8fSmlelstv #define SPDCTL_SWP1         (SPDCTL_I2C_ADDR + 4)
645fcead8fSmlelstv #define SPDCTL_SWP2         (SPDCTL_I2C_ADDR + 5)
655fcead8fSmlelstv #define SPDCTL_SWP3         (SPDCTL_I2C_ADDR + 0)
665fcead8fSmlelstv 
675fcead8fSmlelstv /* clear write protections */
685fcead8fSmlelstv #define SPDCTL_CWP          (SPDCTL_I2C_ADDR + 3)
695fcead8fSmlelstv 
705fcead8fSmlelstv /* read protection status */
715fcead8fSmlelstv #define SPDCTL_RPS0         (SPDCTL_I2C_ADDR + 1)
725fcead8fSmlelstv #define SPDCTL_RPS1         (SPDCTL_I2C_ADDR + 4)
735fcead8fSmlelstv #define SPDCTL_RPS2         (SPDCTL_I2C_ADDR + 5)
745fcead8fSmlelstv #define SPDCTL_RPS3         (SPDCTL_I2C_ADDR + 0)
755fcead8fSmlelstv 
765fcead8fSmlelstv /* select page address */
775fcead8fSmlelstv #define SPDCTL_SPA0         (SPDCTL_I2C_ADDR + 6)
785fcead8fSmlelstv #define SPDCTL_SPA1         (SPDCTL_I2C_ADDR + 7)
795fcead8fSmlelstv 
805fcead8fSmlelstv /* read page address */
815fcead8fSmlelstv #define SPDCTL_RPA          (SPDCTL_I2C_ADDR + 6)
82d41a3cefSpgoyette 
83d41a3cefSpgoyette struct spdmem_i2c_softc {
84d41a3cefSpgoyette 	struct spdmem_softc sc_base;
85d41a3cefSpgoyette 	i2c_tag_t sc_tag;
865fcead8fSmlelstv 	i2c_addr_t sc_addr; /* EEPROM */
875fcead8fSmlelstv 	i2c_addr_t sc_page0;
885fcead8fSmlelstv 	i2c_addr_t sc_page1;
89d41a3cefSpgoyette };
90d41a3cefSpgoyette 
91bc91867bSmsaitoh static int  spdmem_reset_page(struct spdmem_i2c_softc *);
92d41a3cefSpgoyette static int  spdmem_i2c_match(device_t, cfdata_t, void *);
93d41a3cefSpgoyette static void spdmem_i2c_attach(device_t, device_t, void *);
94e3bc45f1Spgoyette static int  spdmem_i2c_detach(device_t, int);
95e3bc45f1Spgoyette 
96e3bc45f1Spgoyette CFATTACH_DECL_NEW(spdmem_iic, sizeof(struct spdmem_i2c_softc),
97e3bc45f1Spgoyette     spdmem_i2c_match, spdmem_i2c_attach, spdmem_i2c_detach, NULL);
98d41a3cefSpgoyette 
99be9c8c17Smsaitoh static int spdmem_i2c_read(struct spdmem_softc *, uint16_t, uint8_t *);
100d41a3cefSpgoyette 
101d41a3cefSpgoyette static int
spdmem_reset_page(struct spdmem_i2c_softc * sc)102bc91867bSmsaitoh spdmem_reset_page(struct spdmem_i2c_softc *sc)
103bc91867bSmsaitoh {
104bc91867bSmsaitoh 	uint8_t reg, byte0, byte2;
1058ea6ee8aSpgoyette 	static uint8_t dummy = 0;
106bc91867bSmsaitoh 	int rv;
107bc91867bSmsaitoh 
108bc91867bSmsaitoh 	reg = 0;
109bc91867bSmsaitoh 
11077c8c4e6Smlelstv 	rv = iic_acquire_bus(sc->sc_tag, 0);
11177c8c4e6Smlelstv 	if (rv)
11277c8c4e6Smlelstv 		return rv;
113bc91867bSmsaitoh 
114bc91867bSmsaitoh 	/*
115bc91867bSmsaitoh 	 * Try to read byte 0 and 2. If it failed, it's not spdmem or a device
116bc91867bSmsaitoh 	 * doesn't exist at the address.
117bc91867bSmsaitoh 	 */
118bc91867bSmsaitoh 	rv = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, &reg, 1,
1197c3bc3baSthorpej 	    &byte0, 1, 0);
120f45c2bb4Smsaitoh 	if (rv != 0)
121f45c2bb4Smsaitoh 		goto error;
122f45c2bb4Smsaitoh 
123401cbd3cSmsaitoh 	reg = 2;
1242317530aSmsaitoh 	rv = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, &reg, 1,
1257c3bc3baSthorpej 	    &byte2, 1, 0);
126bc91867bSmsaitoh 	if (rv != 0)
127bc91867bSmsaitoh 		goto error;
128bc91867bSmsaitoh 
129bc91867bSmsaitoh 	/*
130bc91867bSmsaitoh 	 * Quirk for BIOSes that leave page 1 of a 4kbit EEPROM selected.
131bc91867bSmsaitoh 	 *
132bc91867bSmsaitoh 	 * byte0 is the length, byte2 is the memory type. Both of them should
133bc91867bSmsaitoh 	 * not be zero. If zero, the current page might be 1 (DDR4 and newer).
134bc91867bSmsaitoh 	 * If page 1 is selected, offset 0 can be 0 (Module Characteristics
135bc91867bSmsaitoh 	 * (Energy backup is not available)) and also offset 2 can be 0
136bc91867bSmsaitoh 	 * (Megabytes, and a part of Capacity digits).
137bc91867bSmsaitoh 	 *
138bc91867bSmsaitoh 	 * Note: The encoding of byte0 is vary in memory type, so we check
139bc91867bSmsaitoh 	 * just with zero to be simple.
140bc91867bSmsaitoh 	 *
141bc91867bSmsaitoh 	 * Try to see if we are not at page 0. If it's not, select page 0.
142bc91867bSmsaitoh 	 */
143bc91867bSmsaitoh 	if ((byte0 == 0) || (byte2 == 0)) {
144bc91867bSmsaitoh 		/*
145bc91867bSmsaitoh 		 * Note that SDCTL_RPA is the same as sc->sc_page0(SPDCTL_SPA0)
146bc91867bSmsaitoh 		 * Write is SPA0, read is RPA.
147bc91867bSmsaitoh 		 *
148bc91867bSmsaitoh 		 * This call returns 0 on page 0 and returns -1 on page 1.
149bc91867bSmsaitoh 		 * I don't know whether our icc_exec()'s API is good or not.
150bc91867bSmsaitoh 		 */
151bc91867bSmsaitoh 		rv = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_page0,
1527c3bc3baSthorpej 		    &reg, 1, &dummy, 1, 0);
153bc91867bSmsaitoh 		if (rv != 0) {
154bc91867bSmsaitoh 			/*
155bc91867bSmsaitoh 			 * The possibilities are:
156bc91867bSmsaitoh 			 * a) page 1 is selected.
157bc91867bSmsaitoh 			 * b) The device doesn't support page select and
158bc91867bSmsaitoh 			 *    it's not a SPD ROM.
159bc91867bSmsaitoh 			 * Is there no way to distinguish them now?
160bc91867bSmsaitoh 			 */
161bc91867bSmsaitoh 			rv = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP,
1627c3bc3baSthorpej 			    sc->sc_page0, &reg, 1, &dummy, 1, 0);
163bc91867bSmsaitoh 			if (rv == 0) {
164bc91867bSmsaitoh 				aprint_debug("Page 1 was selected. Page 0 is "
165bc91867bSmsaitoh 				    "selected now.\n");
166bc91867bSmsaitoh 			} else {
167bc91867bSmsaitoh 				aprint_debug("Failed to select page 0. This "
168bc91867bSmsaitoh 				    "device isn't SPD ROM\n");
169bc91867bSmsaitoh 			}
170bc91867bSmsaitoh 		} else {
171bc91867bSmsaitoh 			/* This device isn't SPD ROM */
172bc91867bSmsaitoh 			rv = -1;
173bc91867bSmsaitoh 		}
174bc91867bSmsaitoh 	}
175bc91867bSmsaitoh error:
176bc91867bSmsaitoh 	iic_release_bus(sc->sc_tag, 0);
177bc91867bSmsaitoh 
178bc91867bSmsaitoh 	return rv;
179bc91867bSmsaitoh }
180bc91867bSmsaitoh 
1817079c61cSjakllsch static const struct device_compatible_entry compat_data[] = {
1827246a945Sthorpej 	{ .compat = "atmel,spd" },
1837246a945Sthorpej 	{ .compat = "i2c-at34c02" },
18418f3098cSthorpej 	DEVICE_COMPAT_EOL
1857079c61cSjakllsch };
1867079c61cSjakllsch 
187bc91867bSmsaitoh static int
spdmem_i2c_match(device_t parent,cfdata_t match,void * aux)188d41a3cefSpgoyette spdmem_i2c_match(device_t parent, cfdata_t match, void *aux)
189d41a3cefSpgoyette {
190d41a3cefSpgoyette 	struct i2c_attach_args *ia = aux;
191d41a3cefSpgoyette 	struct spdmem_i2c_softc sc;
1927079c61cSjakllsch 	int match_result;
1937079c61cSjakllsch 
1947079c61cSjakllsch 	if (iic_use_direct_match(ia, match, compat_data, &match_result))
1957079c61cSjakllsch 		return match_result;
196d41a3cefSpgoyette 
197aa41e992Sthorpej 	/*
198aa41e992Sthorpej 	 * XXXJRT
199aa41e992Sthorpej 	 * Should do this with "compatible" strings.  There are also
200aa41e992Sthorpej 	 * other problems with this "match" routine.  Specifically, if
201aa41e992Sthorpej 	 * we are doing direct-config, we know the device is already
202aa41e992Sthorpej 	 * there aren't do need to probe.  I'll leave the logic for
203aa41e992Sthorpej 	 * now and let someone who knows better clean it later.
204aa41e992Sthorpej 	 */
205aa41e992Sthorpej 
206d41a3cefSpgoyette 	if (ia->ia_name) {
207d41a3cefSpgoyette 		/* add other names as we find more firmware variations */
20806792457Snakayama 		if (strcmp(ia->ia_name, "dimm-spd") &&
20906792457Snakayama 		    strcmp(ia->ia_name, "dimm"))
210d41a3cefSpgoyette 			return 0;
211d41a3cefSpgoyette 	}
212d41a3cefSpgoyette 
213d41a3cefSpgoyette 	/* only do this lame test when not using direct config */
214d41a3cefSpgoyette 	if (ia->ia_name == NULL) {
215d41a3cefSpgoyette 		if ((ia->ia_addr & SPDMEM_I2C_ADDRMASK) != SPDMEM_I2C_ADDR)
216d41a3cefSpgoyette 			return 0;
217d41a3cefSpgoyette 	}
218d41a3cefSpgoyette 
219d41a3cefSpgoyette 	sc.sc_tag = ia->ia_tag;
220d41a3cefSpgoyette 	sc.sc_addr = ia->ia_addr;
2215fcead8fSmlelstv 	sc.sc_page0 = SPDCTL_SPA0;
2225fcead8fSmlelstv 	sc.sc_page1 = SPDCTL_SPA1;
223d41a3cefSpgoyette 	sc.sc_base.sc_read = spdmem_i2c_read;
224d41a3cefSpgoyette 
225bc91867bSmsaitoh 	/* Check the bank and reset to the page 0 */
226bc91867bSmsaitoh 	if (spdmem_reset_page(&sc) != 0)
227bc91867bSmsaitoh 		return 0;
228bc91867bSmsaitoh 
229aa41e992Sthorpej 	if (spdmem_common_probe(&sc.sc_base)) {
230aa41e992Sthorpej 		return ia->ia_name ? I2C_MATCH_DIRECT_SPECIFIC
231aa41e992Sthorpej 				   : I2C_MATCH_ADDRESS_AND_PROBE;
232aa41e992Sthorpej 	}
233aa41e992Sthorpej 	return 0;
234d41a3cefSpgoyette }
235d41a3cefSpgoyette 
236d41a3cefSpgoyette static void
spdmem_i2c_attach(device_t parent,device_t self,void * aux)237d41a3cefSpgoyette spdmem_i2c_attach(device_t parent, device_t self, void *aux)
238d41a3cefSpgoyette {
239d41a3cefSpgoyette 	struct spdmem_i2c_softc *sc = device_private(self);
240d41a3cefSpgoyette 	struct i2c_attach_args *ia = aux;
241d41a3cefSpgoyette 
242d41a3cefSpgoyette 	sc->sc_tag = ia->ia_tag;
243d41a3cefSpgoyette 	sc->sc_addr = ia->ia_addr;
2445fcead8fSmlelstv 	sc->sc_page0 = SPDCTL_SPA0;
2455fcead8fSmlelstv 	sc->sc_page1 = SPDCTL_SPA1;
246d41a3cefSpgoyette 	sc->sc_base.sc_read = spdmem_i2c_read;
247d41a3cefSpgoyette 
248d41a3cefSpgoyette 	if (!pmf_device_register(self, NULL, NULL))
249d41a3cefSpgoyette 		aprint_error_dev(self, "couldn't establish power handler\n");
250d41a3cefSpgoyette 
251d41a3cefSpgoyette 	spdmem_common_attach(&sc->sc_base, self);
252d41a3cefSpgoyette }
253d41a3cefSpgoyette 
254e3bc45f1Spgoyette static int
spdmem_i2c_detach(device_t self,int flags)255e3bc45f1Spgoyette spdmem_i2c_detach(device_t self, int flags)
256e3bc45f1Spgoyette {
257e3bc45f1Spgoyette 	struct spdmem_i2c_softc *sc = device_private(self);
258e3bc45f1Spgoyette 
259e3bc45f1Spgoyette 	pmf_device_deregister(self);
260e3bc45f1Spgoyette 
261e3bc45f1Spgoyette 	return spdmem_common_detach(&sc->sc_base, self);
262e3bc45f1Spgoyette }
263e3bc45f1Spgoyette 
264be9c8c17Smsaitoh static int
spdmem_i2c_read(struct spdmem_softc * softc,uint16_t addr,uint8_t * val)265be9c8c17Smsaitoh spdmem_i2c_read(struct spdmem_softc *softc, uint16_t addr, uint8_t *val)
266d41a3cefSpgoyette {
267be9c8c17Smsaitoh 	uint8_t reg;
268d41a3cefSpgoyette 	struct spdmem_i2c_softc *sc = (struct spdmem_i2c_softc *)softc;
2695fcead8fSmlelstv 	static uint8_t dummy = 0;
270be9c8c17Smsaitoh 	int rv;
2715fcead8fSmlelstv 
2725fcead8fSmlelstv 	reg = addr & 0xff;
273d41a3cefSpgoyette 
27477c8c4e6Smlelstv 	rv = iic_acquire_bus(sc->sc_tag, 0);
27577c8c4e6Smlelstv 	if (rv)
27677c8c4e6Smlelstv 		return rv;
2775fcead8fSmlelstv 
2785fcead8fSmlelstv 	if (addr & 0x100) {
279be9c8c17Smsaitoh 		rv = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_page1,
2807c3bc3baSthorpej 		    &dummy, 1, &dummy, 1, 0);
281be9c8c17Smsaitoh 		rv |= iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr,
2827c3bc3baSthorpej 		    &reg, 1, val, 1, 0);
283be9c8c17Smsaitoh 		rv |= iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP,
2847c3bc3baSthorpej 		    sc->sc_page0, &dummy, 1, &dummy, 1, 0);
2855fcead8fSmlelstv 	} else {
286be9c8c17Smsaitoh 		rv = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr,
2877c3bc3baSthorpej 		    &reg, 1, val, 1, 0);
2885fcead8fSmlelstv 	}
2895fcead8fSmlelstv 
290d41a3cefSpgoyette 	iic_release_bus(sc->sc_tag, 0);
291d41a3cefSpgoyette 
292be9c8c17Smsaitoh 	return rv;
293d41a3cefSpgoyette }
294e3bc45f1Spgoyette 
295*a02f6201Spgoyette MODULE(MODULE_CLASS_DRIVER, spdmem, "iic");
296e3bc45f1Spgoyette 
297e3bc45f1Spgoyette #ifdef _MODULE
298e3bc45f1Spgoyette #include "ioconf.c"
299e3bc45f1Spgoyette #endif
300e3bc45f1Spgoyette 
301e3bc45f1Spgoyette static int
spdmem_modcmd(modcmd_t cmd,void * opaque)302e3bc45f1Spgoyette spdmem_modcmd(modcmd_t cmd, void *opaque)
303e3bc45f1Spgoyette {
304e3bc45f1Spgoyette 	int error = 0;
305865357bdSpgoyette #ifdef _MODULE
306865357bdSpgoyette 	static struct sysctllog *spdmem_sysctl_clog;
307865357bdSpgoyette #endif
308e3bc45f1Spgoyette 
309e3bc45f1Spgoyette 	switch (cmd) {
310e3bc45f1Spgoyette 	case MODULE_CMD_INIT:
311e3bc45f1Spgoyette #ifdef _MODULE
312e3bc45f1Spgoyette 		error = config_init_component(cfdriver_ioconf_spdmem,
313e3bc45f1Spgoyette 		    cfattach_ioconf_spdmem, cfdata_ioconf_spdmem);
314e3bc45f1Spgoyette #endif
315e3bc45f1Spgoyette 		return error;
316e3bc45f1Spgoyette 	case MODULE_CMD_FINI:
317e3bc45f1Spgoyette #ifdef _MODULE
318e3bc45f1Spgoyette 		error = config_fini_component(cfdriver_ioconf_spdmem,
319e3bc45f1Spgoyette 		    cfattach_ioconf_spdmem, cfdata_ioconf_spdmem);
320865357bdSpgoyette 		sysctl_teardown(&spdmem_sysctl_clog);
321e3bc45f1Spgoyette #endif
322e3bc45f1Spgoyette 		return error;
323e3bc45f1Spgoyette 	default:
324e3bc45f1Spgoyette 		return ENOTTY;
325e3bc45f1Spgoyette 	}
326e3bc45f1Spgoyette }
327