xref: /netbsd-src/sys/dev/acpi/qcomgpio.c (revision ace0f69009ee04a58cbf8f36db48999a6d788a31)
1*ace0f690Sriastradh /* $NetBSD: qcomgpio.c,v 1.8 2024/12/17 22:05:21 riastradh Exp $ */
2532c83a9Sjmcneill 
3532c83a9Sjmcneill /*-
4532c83a9Sjmcneill  * Copyright (c) 2024 The NetBSD Foundation, Inc.
5532c83a9Sjmcneill  * All rights reserved.
6532c83a9Sjmcneill  *
7532c83a9Sjmcneill  * This code is derived from software contributed to The NetBSD Foundation
8532c83a9Sjmcneill  * by Jared McNeill <jmcneill@invisible.ca>.
9532c83a9Sjmcneill  *
10532c83a9Sjmcneill  * Redistribution and use in source and binary forms, with or without
11532c83a9Sjmcneill  * modification, are permitted provided that the following conditions
12532c83a9Sjmcneill  * are met:
13532c83a9Sjmcneill  * 1. Redistributions of source code must retain the above copyright
14532c83a9Sjmcneill  *    notice, this list of conditions and the following disclaimer.
15532c83a9Sjmcneill  * 2. Redistributions in binary form must reproduce the above copyright
16532c83a9Sjmcneill  *    notice, this list of conditions and the following disclaimer in the
17532c83a9Sjmcneill  *    documentation and/or other materials provided with the distribution.
18532c83a9Sjmcneill  *
19532c83a9Sjmcneill  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20532c83a9Sjmcneill  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21532c83a9Sjmcneill  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22532c83a9Sjmcneill  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23532c83a9Sjmcneill  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24532c83a9Sjmcneill  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25532c83a9Sjmcneill  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26532c83a9Sjmcneill  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27532c83a9Sjmcneill  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28532c83a9Sjmcneill  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29532c83a9Sjmcneill  * POSSIBILITY OF SUCH DAMAGE.
30532c83a9Sjmcneill  */
31532c83a9Sjmcneill 
32532c83a9Sjmcneill #include <sys/cdefs.h>
33*ace0f690Sriastradh __KERNEL_RCSID(0, "$NetBSD: qcomgpio.c,v 1.8 2024/12/17 22:05:21 riastradh Exp $");
34532c83a9Sjmcneill 
35532c83a9Sjmcneill #include <sys/param.h>
3619ff6633Sriastradh #include <sys/types.h>
3719ff6633Sriastradh 
38532c83a9Sjmcneill #include <sys/bus.h>
39532c83a9Sjmcneill #include <sys/cpu.h>
40532c83a9Sjmcneill #include <sys/device.h>
4119ff6633Sriastradh #include <sys/evcnt.h>
42532c83a9Sjmcneill #include <sys/gpio.h>
43532c83a9Sjmcneill #include <sys/kmem.h>
44532c83a9Sjmcneill #include <sys/mutex.h>
4519ff6633Sriastradh #include <sys/queue.h>
46532c83a9Sjmcneill 
47532c83a9Sjmcneill #include <dev/acpi/acpi_event.h>
48532c83a9Sjmcneill #include <dev/acpi/acpi_gpio.h>
4919ff6633Sriastradh #include <dev/acpi/acpi_intr.h>
5019ff6633Sriastradh #include <dev/acpi/acpireg.h>
5119ff6633Sriastradh #include <dev/acpi/acpivar.h>
52532c83a9Sjmcneill #include <dev/acpi/qcomgpioreg.h>
53532c83a9Sjmcneill 
54532c83a9Sjmcneill #include <dev/gpio/gpiovar.h>
55532c83a9Sjmcneill 
56532c83a9Sjmcneill typedef enum {
57532c83a9Sjmcneill 	QCOMGPIO_X1E,
58532c83a9Sjmcneill } qcomgpio_type;
59532c83a9Sjmcneill 
6054896b62Sjmcneill struct qcomgpio_reserved {
6154896b62Sjmcneill 	int	start;
6254896b62Sjmcneill 	int	count;
6354896b62Sjmcneill };
6454896b62Sjmcneill 
65532c83a9Sjmcneill struct qcomgpio_config {
6654896b62Sjmcneill 	struct qcomgpio_reserved *reserved;
6754896b62Sjmcneill 	u_int	num_reserved;
68576d7ed0Sjmcneill 	u_int	*pdc_filter;
69576d7ed0Sjmcneill 	u_int	num_pdc_filter;
70532c83a9Sjmcneill };
71532c83a9Sjmcneill 
72532c83a9Sjmcneill struct qcomgpio_intr_handler {
73532c83a9Sjmcneill 	int	(*ih_func)(void *);
74532c83a9Sjmcneill 	void	*ih_arg;
75532c83a9Sjmcneill 	int	ih_pin;
76fcf6608cSjmcneill 	int	ih_type;
77db0db25dSjmcneill 	struct evcnt ih_evcnt;
78db0db25dSjmcneill 	char	ih_name[16];
79532c83a9Sjmcneill 	LIST_ENTRY(qcomgpio_intr_handler) ih_list;
80532c83a9Sjmcneill };
81532c83a9Sjmcneill 
82575554bdSjmcneill struct qcomgpio_pdcmap {
83575554bdSjmcneill 	int	pm_pin;
84575554bdSjmcneill 	u_int	pm_irq;
85575554bdSjmcneill };
86575554bdSjmcneill 
87532c83a9Sjmcneill struct qcomgpio_softc {
88532c83a9Sjmcneill 	device_t			sc_dev;
89532c83a9Sjmcneill 	device_t			sc_gpiodev;
90532c83a9Sjmcneill 	bus_space_handle_t		sc_bsh;
91532c83a9Sjmcneill 	bus_space_tag_t			sc_bst;
92532c83a9Sjmcneill 	const struct qcomgpio_config	*sc_config;
93532c83a9Sjmcneill 	struct gpio_chipset_tag		sc_gc;
94532c83a9Sjmcneill 	gpio_pin_t			*sc_pins;
95575554bdSjmcneill 	u_int				sc_npins;
96532c83a9Sjmcneill 	LIST_HEAD(, qcomgpio_intr_handler) sc_intrs;
97532c83a9Sjmcneill 	kmutex_t			sc_lock;
98575554bdSjmcneill 
99575554bdSjmcneill 	struct qcomgpio_pdcmap		*sc_pdcmap;
100575554bdSjmcneill 	u_int				sc_npdcmap;
101532c83a9Sjmcneill };
102532c83a9Sjmcneill 
103532c83a9Sjmcneill #define RD4(sc, reg)		\
104532c83a9Sjmcneill 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
105532c83a9Sjmcneill #define WR4(sc, reg, val)	\
106532c83a9Sjmcneill 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
107532c83a9Sjmcneill 
108532c83a9Sjmcneill static int	qcomgpio_match(device_t, cfdata_t, void *);
109532c83a9Sjmcneill static void	qcomgpio_attach(device_t, device_t, void *);
110532c83a9Sjmcneill 
11154896b62Sjmcneill static bool	qcomgpio_pin_reserved(struct qcomgpio_softc *, int);
112532c83a9Sjmcneill static int	qcomgpio_pin_read(void *, int);
113532c83a9Sjmcneill static void	qcomgpio_pin_write(void *, int, int);
114532c83a9Sjmcneill static void	qcomgpio_pin_ctl(void *, int, int);
115532c83a9Sjmcneill static void *	qcomgpio_intr_establish(void *, int, int, int,
116532c83a9Sjmcneill 		    int (*)(void *), void *);
117532c83a9Sjmcneill static void	qcomgpio_intr_disestablish(void *, void *);
118532c83a9Sjmcneill static bool	qcomgpio_intr_str(void *, int, int, char *, size_t);
119532c83a9Sjmcneill static void	qcomgpio_intr_mask(void *, void *);
120532c83a9Sjmcneill static void	qcomgpio_intr_unmask(void *, void *);
121532c83a9Sjmcneill 
122575554bdSjmcneill static u_int	qcomgpio_acpi_num_pins(device_t, ACPI_HANDLE);
123575554bdSjmcneill static void	qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *,
124575554bdSjmcneill 		    ACPI_HANDLE);
125fcf6608cSjmcneill static int	qcomgpio_acpi_translate(void *, ACPI_RESOURCE_GPIO *, void **);
126532c83a9Sjmcneill static void	qcomgpio_register_event(void *, struct acpi_event *,
127532c83a9Sjmcneill 		    ACPI_RESOURCE_GPIO *);
128532c83a9Sjmcneill static int	qcomgpio_intr(void *);
129532c83a9Sjmcneill 
130532c83a9Sjmcneill CFATTACH_DECL_NEW(qcomgpio, sizeof(struct qcomgpio_softc),
131532c83a9Sjmcneill     qcomgpio_match, qcomgpio_attach, NULL, NULL);
132532c83a9Sjmcneill 
133575554bdSjmcneill static UINT8 qcomgpio_gpio_dsm_uuid[ACPI_UUID_LENGTH] = {
134575554bdSjmcneill 	0xa4, 0xb2, 0xb9, 0x98, 0x63, 0x16, 0x5f, 0x4a,
135575554bdSjmcneill 	0x82, 0xf2, 0xc6, 0xc9, 0x9a, 0x39, 0x47, 0x26
136575554bdSjmcneill };
137575554bdSjmcneill #define QCOMGPIO_GPIO_DSM_REV		0
138575554bdSjmcneill #define QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS	2
139575554bdSjmcneill 
140575554bdSjmcneill static UINT8 qcomgpio_pdc_dsm_uuid[ACPI_UUID_LENGTH] = {
141575554bdSjmcneill 	0xd4, 0x0f, 0x1b, 0x92, 0x7c, 0x56, 0xa0, 0x43,
142575554bdSjmcneill 	0xbb, 0x14, 0x26, 0x48, 0xf7, 0xb2, 0xa1, 0x8c
143575554bdSjmcneill };
144575554bdSjmcneill #define QCOMGPIO_PDC_DSM_REV		0
145575554bdSjmcneill #define QCOMGPIO_PDC_DSM_FUNC_CIPR	2
146fcf6608cSjmcneill 
14754896b62Sjmcneill static struct qcomgpio_reserved qcomgpio_x1e_reserved[] = {
14854896b62Sjmcneill 	{ .start = 34, .count = 2 },
14954896b62Sjmcneill 	{ .start = 44, .count = 4 },
15054896b62Sjmcneill 	{ .start = 72, .count = 2 },
15154896b62Sjmcneill 	{ .start = 238, .count = 1 },
15254896b62Sjmcneill };
15354896b62Sjmcneill 
154576d7ed0Sjmcneill static int qcomgpio_x1e_pdc_filter[] = {
155576d7ed0Sjmcneill 	0x140,	/* Interrupt storm due to missing SMI support. */
156576d7ed0Sjmcneill };
157576d7ed0Sjmcneill 
158532c83a9Sjmcneill static struct qcomgpio_config qcomgpio_x1e_config = {
15954896b62Sjmcneill 	.reserved = qcomgpio_x1e_reserved,
16054896b62Sjmcneill 	.num_reserved = __arraycount(qcomgpio_x1e_reserved),
161576d7ed0Sjmcneill 	.pdc_filter = qcomgpio_x1e_pdc_filter,
162576d7ed0Sjmcneill 	.num_pdc_filter = __arraycount(qcomgpio_x1e_pdc_filter),
163532c83a9Sjmcneill };
164532c83a9Sjmcneill 
165532c83a9Sjmcneill static const struct device_compatible_entry compat_data[] = {
166532c83a9Sjmcneill 	{ .compat = "QCOM0C0C",	.data = &qcomgpio_x1e_config },
167532c83a9Sjmcneill 	DEVICE_COMPAT_EOL
168532c83a9Sjmcneill };
169532c83a9Sjmcneill 
170532c83a9Sjmcneill static int
171532c83a9Sjmcneill qcomgpio_match(device_t parent, cfdata_t cf, void *aux)
172532c83a9Sjmcneill {
173532c83a9Sjmcneill 	struct acpi_attach_args *aa = aux;
174532c83a9Sjmcneill 
175532c83a9Sjmcneill 	return acpi_compatible_match(aa, compat_data);
176532c83a9Sjmcneill }
177532c83a9Sjmcneill 
178532c83a9Sjmcneill static void
179532c83a9Sjmcneill qcomgpio_attach(device_t parent, device_t self, void *aux)
180532c83a9Sjmcneill {
181532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = device_private(self);
182532c83a9Sjmcneill 	struct acpi_attach_args *aa = aux;
183532c83a9Sjmcneill 	struct gpiobus_attach_args gba;
184532c83a9Sjmcneill 	ACPI_HANDLE hdl = aa->aa_node->ad_handle;
185532c83a9Sjmcneill 	struct acpi_resources res;
186532c83a9Sjmcneill 	struct acpi_mem *mem;
187532c83a9Sjmcneill 	struct acpi_irq *irq;
188532c83a9Sjmcneill 	ACPI_STATUS rv;
189575554bdSjmcneill 	int error, pin, n;
190532c83a9Sjmcneill 	void *ih;
191532c83a9Sjmcneill 
192532c83a9Sjmcneill 	sc->sc_dev = self;
193532c83a9Sjmcneill 	sc->sc_config = acpi_compatible_lookup(aa, compat_data)->data;
194532c83a9Sjmcneill 	sc->sc_bst = aa->aa_memt;
195532c83a9Sjmcneill 	KASSERT(sc->sc_config != NULL);
196532c83a9Sjmcneill 	LIST_INIT(&sc->sc_intrs);
197532c83a9Sjmcneill 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
198532c83a9Sjmcneill 
199532c83a9Sjmcneill 	rv = acpi_resource_parse(sc->sc_dev, hdl, "_CRS",
200532c83a9Sjmcneill 	    &res, &acpi_resource_parse_ops_default);
201532c83a9Sjmcneill 	if (ACPI_FAILURE(rv)) {
202532c83a9Sjmcneill 		return;
203532c83a9Sjmcneill 	}
204532c83a9Sjmcneill 
205532c83a9Sjmcneill 	mem = acpi_res_mem(&res, 0);
206532c83a9Sjmcneill 	if (mem == NULL) {
207532c83a9Sjmcneill 		aprint_error_dev(self, "couldn't find mem resource\n");
208532c83a9Sjmcneill 		goto done;
209532c83a9Sjmcneill 	}
210532c83a9Sjmcneill 
211532c83a9Sjmcneill 	irq = acpi_res_irq(&res, 0);
212532c83a9Sjmcneill 	if (irq == NULL) {
213532c83a9Sjmcneill 		aprint_error_dev(self, "couldn't find irq resource\n");
214532c83a9Sjmcneill 		goto done;
215532c83a9Sjmcneill 	}
216532c83a9Sjmcneill 
217532c83a9Sjmcneill 	error = bus_space_map(sc->sc_bst, mem->ar_base, mem->ar_length, 0,
218532c83a9Sjmcneill 	    &sc->sc_bsh);
219532c83a9Sjmcneill 	if (error) {
220532c83a9Sjmcneill 		aprint_error_dev(self, "couldn't map registers\n");
221532c83a9Sjmcneill 		goto done;
222532c83a9Sjmcneill 	}
223532c83a9Sjmcneill 
224575554bdSjmcneill 	sc->sc_npdcmap = res.ar_nirq;
225575554bdSjmcneill 	sc->sc_pdcmap = kmem_zalloc(sizeof(*sc->sc_pdcmap) * sc->sc_npdcmap,
226575554bdSjmcneill 	    KM_SLEEP);
227575554bdSjmcneill 	for (n = 0; n < sc->sc_npdcmap; n++) {
228575554bdSjmcneill 		sc->sc_pdcmap[n].pm_irq = acpi_res_irq(&res, n)->ar_irq;
229575554bdSjmcneill 		sc->sc_pdcmap[n].pm_pin = -1;
230575554bdSjmcneill 		aprint_debug_dev(self, "IRQ resource %u -> %#x\n",
231575554bdSjmcneill 		    n, sc->sc_pdcmap[n].pm_irq);
232575554bdSjmcneill 	}
233575554bdSjmcneill 	qcomgpio_acpi_fill_pdcmap(sc, hdl);
234575554bdSjmcneill 
235575554bdSjmcneill 	sc->sc_npins = qcomgpio_acpi_num_pins(self, hdl);
236575554bdSjmcneill 	if (sc->sc_npins == 0) {
237575554bdSjmcneill 		aprint_error_dev(self, "couldn't determine pin count!\n");
238575554bdSjmcneill 		goto done;
239575554bdSjmcneill 	}
240575554bdSjmcneill 	sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * sc->sc_npins,
241575554bdSjmcneill 	    KM_SLEEP);
242575554bdSjmcneill 	for (pin = 0; pin < sc->sc_npins; pin++) {
24354896b62Sjmcneill 		sc->sc_pins[pin].pin_caps = qcomgpio_pin_reserved(sc, pin) ?
24454896b62Sjmcneill 		    0 : (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
245532c83a9Sjmcneill 		sc->sc_pins[pin].pin_num = pin;
246532c83a9Sjmcneill 		sc->sc_pins[pin].pin_intrcaps =
247532c83a9Sjmcneill 		    GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE |
248532c83a9Sjmcneill 		    GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_HIGH_LEVEL |
249532c83a9Sjmcneill 		    GPIO_INTR_LOW_LEVEL | GPIO_INTR_MPSAFE;
250532c83a9Sjmcneill 	}
251532c83a9Sjmcneill 
252532c83a9Sjmcneill 	sc->sc_gc.gp_cookie = sc;
253532c83a9Sjmcneill 	sc->sc_gc.gp_pin_read = qcomgpio_pin_read;
254532c83a9Sjmcneill 	sc->sc_gc.gp_pin_write = qcomgpio_pin_write;
255532c83a9Sjmcneill 	sc->sc_gc.gp_pin_ctl = qcomgpio_pin_ctl;
256532c83a9Sjmcneill 	sc->sc_gc.gp_intr_establish = qcomgpio_intr_establish;
257532c83a9Sjmcneill 	sc->sc_gc.gp_intr_disestablish = qcomgpio_intr_disestablish;
258532c83a9Sjmcneill 	sc->sc_gc.gp_intr_str = qcomgpio_intr_str;
259532c83a9Sjmcneill 	sc->sc_gc.gp_intr_mask = qcomgpio_intr_mask;
260532c83a9Sjmcneill 	sc->sc_gc.gp_intr_unmask = qcomgpio_intr_unmask;
261532c83a9Sjmcneill 
262532c83a9Sjmcneill 	rv = acpi_event_create_gpio(self, hdl, qcomgpio_register_event, sc);
263532c83a9Sjmcneill 	if (ACPI_FAILURE(rv)) {
264532c83a9Sjmcneill 		if (rv != AE_NOT_FOUND) {
265532c83a9Sjmcneill 			aprint_error_dev(self, "failed to create events: %s\n",
266532c83a9Sjmcneill 			    AcpiFormatException(rv));
267532c83a9Sjmcneill 		}
268532c83a9Sjmcneill 		goto done;
269532c83a9Sjmcneill 	}
270532c83a9Sjmcneill 
271532c83a9Sjmcneill 	ih = acpi_intr_establish(self, (uint64_t)(uintptr_t)hdl,
272532c83a9Sjmcneill 	    IPL_VM, false, qcomgpio_intr, sc, device_xname(self));
273532c83a9Sjmcneill 	if (ih == NULL) {
274532c83a9Sjmcneill 		aprint_error_dev(self, "couldn't establish interrupt\n");
275532c83a9Sjmcneill 		goto done;
276532c83a9Sjmcneill 	}
277532c83a9Sjmcneill 
278532c83a9Sjmcneill 	memset(&gba, 0, sizeof(gba));
279532c83a9Sjmcneill 	gba.gba_gc = &sc->sc_gc;
280532c83a9Sjmcneill 	gba.gba_pins = sc->sc_pins;
281575554bdSjmcneill 	gba.gba_npins = sc->sc_npins;
282532c83a9Sjmcneill 	sc->sc_gpiodev = config_found(self, &gba, gpiobus_print,
283532c83a9Sjmcneill 	    CFARGS(.iattr = "gpiobus"));
284532c83a9Sjmcneill 	if (sc->sc_gpiodev != NULL) {
285532c83a9Sjmcneill 		acpi_gpio_register(aa->aa_node, self,
286532c83a9Sjmcneill 		    qcomgpio_acpi_translate, sc);
287532c83a9Sjmcneill 	}
288532c83a9Sjmcneill 
289532c83a9Sjmcneill done:
290532c83a9Sjmcneill 	acpi_resource_cleanup(&res);
291532c83a9Sjmcneill }
292532c83a9Sjmcneill 
293575554bdSjmcneill static u_int
294575554bdSjmcneill qcomgpio_acpi_num_pins(device_t dev, ACPI_HANDLE hdl)
295575554bdSjmcneill {
296575554bdSjmcneill 	ACPI_STATUS rv;
297575554bdSjmcneill 	ACPI_INTEGER npins;
298575554bdSjmcneill 
299575554bdSjmcneill 	rv = acpi_dsm_integer(hdl, qcomgpio_gpio_dsm_uuid,
300575554bdSjmcneill 	    QCOMGPIO_GPIO_DSM_REV, QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS,
301575554bdSjmcneill 	    NULL, &npins);
302575554bdSjmcneill 	if (ACPI_FAILURE(rv)) {
303575554bdSjmcneill 		aprint_error_dev(dev, "GPIO _DSM failed: %s\n",
304575554bdSjmcneill 		    AcpiFormatException(rv));
305575554bdSjmcneill 		return 0;
306575554bdSjmcneill 	}
307575554bdSjmcneill 
308575554bdSjmcneill 	aprint_debug_dev(dev, "GPIO pin count: %u\n", (u_int)npins);
309575554bdSjmcneill 
310575554bdSjmcneill 	return (u_int)npins;
311575554bdSjmcneill }
312575554bdSjmcneill 
313575554bdSjmcneill static void
314575554bdSjmcneill qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *sc,
315575554bdSjmcneill     ACPI_HANDLE hdl)
316575554bdSjmcneill {
317575554bdSjmcneill 	ACPI_STATUS rv;
318575554bdSjmcneill 	ACPI_OBJECT *obj;
319576d7ed0Sjmcneill 	u_int n, filt;
320575554bdSjmcneill 
321575554bdSjmcneill 	rv = acpi_dsm_typed(hdl, qcomgpio_pdc_dsm_uuid,
322575554bdSjmcneill 	    QCOMGPIO_PDC_DSM_REV, QCOMGPIO_PDC_DSM_FUNC_CIPR,
323575554bdSjmcneill 	    NULL, ACPI_TYPE_PACKAGE, &obj);
324575554bdSjmcneill 	if (ACPI_FAILURE(rv)) {
325575554bdSjmcneill 		aprint_error_dev(sc->sc_dev, "PDC _DSM failed: %s\n",
326575554bdSjmcneill 		    AcpiFormatException(rv));
327575554bdSjmcneill 		return;
328575554bdSjmcneill 	}
329575554bdSjmcneill 
330575554bdSjmcneill 	for (n = 0; n < obj->Package.Count; n++) {
331575554bdSjmcneill 		ACPI_OBJECT *map = &obj->Package.Elements[n];
332576d7ed0Sjmcneill 		bool filter = false;
333575554bdSjmcneill 		u_int irq, pdc;
334575554bdSjmcneill 		int pin;
335575554bdSjmcneill 
336575554bdSjmcneill 		if (map->Type != ACPI_TYPE_PACKAGE ||
337575554bdSjmcneill 		    map->Package.Count < 3 ||
338575554bdSjmcneill 		    map->Package.Elements[0].Type != ACPI_TYPE_INTEGER ||
339575554bdSjmcneill 		    map->Package.Elements[1].Type != ACPI_TYPE_INTEGER ||
340575554bdSjmcneill 		    map->Package.Elements[2].Type != ACPI_TYPE_INTEGER) {
341575554bdSjmcneill 			continue;
342575554bdSjmcneill 		}
343575554bdSjmcneill 
344575554bdSjmcneill 		irq = (u_int)map->Package.Elements[2].Integer.Value;
345575554bdSjmcneill 		pin = (int)map->Package.Elements[1].Integer.Value;
346575554bdSjmcneill 		for (pdc = 0; pdc < sc->sc_npdcmap; pdc++) {
347575554bdSjmcneill 			if (sc->sc_pdcmap[pdc].pm_irq == irq) {
348576d7ed0Sjmcneill 				for (filt = 0;
349576d7ed0Sjmcneill 				     filt < sc->sc_config->num_pdc_filter;
350576d7ed0Sjmcneill 		     		     filt++) {
351576d7ed0Sjmcneill 					if (sc->sc_config->pdc_filter[filt] ==
352576d7ed0Sjmcneill 					    pdc * 64) {
353576d7ed0Sjmcneill 						filter = true;
354575554bdSjmcneill 						break;
355575554bdSjmcneill 					}
356575554bdSjmcneill 				}
357576d7ed0Sjmcneill 
358576d7ed0Sjmcneill 				if (!filter) {
359576d7ed0Sjmcneill 					sc->sc_pdcmap[pdc].pm_pin = pin;
360576d7ed0Sjmcneill 				}
361576d7ed0Sjmcneill 				break;
362576d7ed0Sjmcneill 			}
363576d7ed0Sjmcneill 		}
364576d7ed0Sjmcneill 
365575554bdSjmcneill 		aprint_debug_dev(sc->sc_dev,
366576d7ed0Sjmcneill 		    "PDC irq %#x -> pin %d%s%s\n", irq, pin,
367576d7ed0Sjmcneill 		    filter ? " (filtered)" : "",
368575554bdSjmcneill 		    pdc == sc->sc_npdcmap ? " (unused)" : "");
369575554bdSjmcneill 	}
370575554bdSjmcneill 
371575554bdSjmcneill 	ACPI_FREE(obj);
372575554bdSjmcneill }
373575554bdSjmcneill 
374532c83a9Sjmcneill static int
375fcf6608cSjmcneill qcomgpio_acpi_translate(void *priv, ACPI_RESOURCE_GPIO *gpio, void **gpiop)
376532c83a9Sjmcneill {
377532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = priv;
378575554bdSjmcneill 	const ACPI_INTEGER vpin = gpio->PinTable[0];
379575554bdSjmcneill 	int pin = -1;
380532c83a9Sjmcneill 
381575554bdSjmcneill 	if (vpin < sc->sc_npins) {
382575554bdSjmcneill 		/* Virtual pin number is 1:1 mapping with hardware. */
383575554bdSjmcneill 		pin = vpin;
384575554bdSjmcneill 	} else if (vpin / 64 < sc->sc_npdcmap) {
385575554bdSjmcneill 		/* Translate the virtual pin number to a hardware pin. */
386575554bdSjmcneill 		pin = sc->sc_pdcmap[vpin / 64].pm_pin;
387575554bdSjmcneill 	}
388532c83a9Sjmcneill 
389575554bdSjmcneill 	aprint_debug_dev(sc->sc_dev, "translate %#lx -> %u\n", vpin, pin);
390532c83a9Sjmcneill 
391532c83a9Sjmcneill 	if (gpiop != NULL) {
392532c83a9Sjmcneill 		if (sc->sc_gpiodev != NULL) {
393532c83a9Sjmcneill 			*gpiop = device_private(sc->sc_gpiodev);
394532c83a9Sjmcneill 		} else {
395532c83a9Sjmcneill 			device_printf(sc->sc_dev,
396575554bdSjmcneill 			    "no gpiodev for pin %#lx -> %u\n", vpin, pin);
397575554bdSjmcneill 			pin = -1;
398532c83a9Sjmcneill 		}
399532c83a9Sjmcneill 	}
400532c83a9Sjmcneill 
401575554bdSjmcneill 	return pin;
402532c83a9Sjmcneill }
403532c83a9Sjmcneill 
404532c83a9Sjmcneill static int
405532c83a9Sjmcneill qcomgpio_acpi_event(void *priv)
406532c83a9Sjmcneill {
407532c83a9Sjmcneill 	struct acpi_event * const ev = priv;
408532c83a9Sjmcneill 
409532c83a9Sjmcneill 	acpi_event_notify(ev);
410532c83a9Sjmcneill 
411532c83a9Sjmcneill 	return 1;
412532c83a9Sjmcneill }
413532c83a9Sjmcneill 
414532c83a9Sjmcneill static void
415532c83a9Sjmcneill qcomgpio_register_event(void *priv, struct acpi_event *ev,
416532c83a9Sjmcneill     ACPI_RESOURCE_GPIO *gpio)
417532c83a9Sjmcneill {
418532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = priv;
419532c83a9Sjmcneill 	int irqmode;
420532c83a9Sjmcneill 	void *ih;
421532c83a9Sjmcneill 
422fcf6608cSjmcneill 	const int pin = qcomgpio_acpi_translate(sc, gpio, NULL);
423532c83a9Sjmcneill 
424532c83a9Sjmcneill 	if (pin < 0) {
425532c83a9Sjmcneill 		aprint_error_dev(sc->sc_dev,
426532c83a9Sjmcneill 		    "ignoring event for pin %#x (out of range)\n",
427532c83a9Sjmcneill 		    gpio->PinTable[0]);
428532c83a9Sjmcneill 		return;
429532c83a9Sjmcneill 	}
430532c83a9Sjmcneill 
431532c83a9Sjmcneill 	if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) {
432532c83a9Sjmcneill 		irqmode = gpio->Polarity == ACPI_ACTIVE_HIGH ?
433532c83a9Sjmcneill 		    GPIO_INTR_HIGH_LEVEL : GPIO_INTR_LOW_LEVEL;
434532c83a9Sjmcneill 	} else {
435532c83a9Sjmcneill 		KASSERT(gpio->Triggering == ACPI_EDGE_SENSITIVE);
436532c83a9Sjmcneill 		if (gpio->Polarity == ACPI_ACTIVE_LOW) {
437532c83a9Sjmcneill 			irqmode = GPIO_INTR_NEG_EDGE;
438532c83a9Sjmcneill 		} else if (gpio->Polarity == ACPI_ACTIVE_HIGH) {
439532c83a9Sjmcneill 			irqmode = GPIO_INTR_POS_EDGE;
440532c83a9Sjmcneill 		} else {
441532c83a9Sjmcneill 			KASSERT(gpio->Polarity == ACPI_ACTIVE_BOTH);
442532c83a9Sjmcneill 			irqmode = GPIO_INTR_DOUBLE_EDGE;
443532c83a9Sjmcneill 		}
444532c83a9Sjmcneill 	}
445532c83a9Sjmcneill 
446532c83a9Sjmcneill 	ih = qcomgpio_intr_establish(sc, pin, IPL_VM, irqmode,
447532c83a9Sjmcneill 	    qcomgpio_acpi_event, ev);
448532c83a9Sjmcneill 	if (ih == NULL) {
449532c83a9Sjmcneill 		aprint_error_dev(sc->sc_dev,
450532c83a9Sjmcneill 		    "couldn't register event for pin %#x\n",
451532c83a9Sjmcneill 		    gpio->PinTable[0]);
452fcf6608cSjmcneill 		return;
453fcf6608cSjmcneill 	}
454fcf6608cSjmcneill 	if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) {
455fcf6608cSjmcneill 		acpi_event_set_intrcookie(ev, ih);
456532c83a9Sjmcneill 	}
457532c83a9Sjmcneill }
458532c83a9Sjmcneill 
45954896b62Sjmcneill static bool
46054896b62Sjmcneill qcomgpio_pin_reserved(struct qcomgpio_softc *sc, int pin)
46154896b62Sjmcneill {
46254896b62Sjmcneill 	u_int n;
46354896b62Sjmcneill 
46454896b62Sjmcneill 	for (n = 0; n < sc->sc_config->num_reserved; n++) {
46554896b62Sjmcneill 		if (pin >= sc->sc_config->reserved[n].start &&
46654896b62Sjmcneill 		    pin < sc->sc_config->reserved[n].start +
46754896b62Sjmcneill 			  sc->sc_config->reserved[n].count) {
46854896b62Sjmcneill 			return true;
46954896b62Sjmcneill 		}
47054896b62Sjmcneill 	}
47154896b62Sjmcneill 
47254896b62Sjmcneill 	return false;
47354896b62Sjmcneill }
47454896b62Sjmcneill 
475532c83a9Sjmcneill static int
476532c83a9Sjmcneill qcomgpio_pin_read(void *priv, int pin)
477532c83a9Sjmcneill {
478532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = priv;
479532c83a9Sjmcneill 	uint32_t val;
480532c83a9Sjmcneill 
481575554bdSjmcneill 	if (pin < 0 || pin >= sc->sc_npins) {
482532c83a9Sjmcneill 		return 0;
483532c83a9Sjmcneill 	}
484fcf6608cSjmcneill 	if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_INPUT) == 0) {
485fcf6608cSjmcneill 		return 0;
486fcf6608cSjmcneill 	}
487532c83a9Sjmcneill 
488532c83a9Sjmcneill 	val = RD4(sc, TLMM_GPIO_IN_OUT(pin));
489532c83a9Sjmcneill 	return (val & TLMM_GPIO_IN_OUT_GPIO_IN) != 0;
490532c83a9Sjmcneill }
491532c83a9Sjmcneill 
492532c83a9Sjmcneill static void
493532c83a9Sjmcneill qcomgpio_pin_write(void *priv, int pin, int pinval)
494532c83a9Sjmcneill {
495532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = priv;
496532c83a9Sjmcneill 	uint32_t val;
497532c83a9Sjmcneill 
498575554bdSjmcneill 	if (pin < 0 || pin >= sc->sc_npins) {
499532c83a9Sjmcneill 		return;
500532c83a9Sjmcneill 	}
501fcf6608cSjmcneill 	if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_OUTPUT) == 0) {
502fcf6608cSjmcneill 		return;
503fcf6608cSjmcneill 	}
504532c83a9Sjmcneill 
505532c83a9Sjmcneill 	val = RD4(sc, TLMM_GPIO_IN_OUT(pin));
506532c83a9Sjmcneill 	if (pinval) {
507532c83a9Sjmcneill 		val |= TLMM_GPIO_IN_OUT_GPIO_OUT;
508532c83a9Sjmcneill 	} else {
509532c83a9Sjmcneill 		val &= ~TLMM_GPIO_IN_OUT_GPIO_OUT;
510532c83a9Sjmcneill 	}
511532c83a9Sjmcneill 	WR4(sc, TLMM_GPIO_IN_OUT(pin), val);
512532c83a9Sjmcneill }
513532c83a9Sjmcneill 
514532c83a9Sjmcneill static void
515532c83a9Sjmcneill qcomgpio_pin_ctl(void *priv, int pin, int flags)
516532c83a9Sjmcneill {
517532c83a9Sjmcneill 	/* Nothing to do here, as firmware has already configured pins. */
518532c83a9Sjmcneill }
519532c83a9Sjmcneill 
520532c83a9Sjmcneill static void *
521532c83a9Sjmcneill qcomgpio_intr_establish(void *priv, int pin, int ipl, int irqmode,
522532c83a9Sjmcneill     int (*func)(void *), void *arg)
523532c83a9Sjmcneill {
524532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = priv;
525532c83a9Sjmcneill 	struct qcomgpio_intr_handler *qih, *qihp;
526532c83a9Sjmcneill 	uint32_t dect, pol;
527532c83a9Sjmcneill 	uint32_t val;
528532c83a9Sjmcneill 
529575554bdSjmcneill 	if (pin < 0 || pin >= sc->sc_npins) {
530532c83a9Sjmcneill 		return NULL;
531532c83a9Sjmcneill 	}
532532c83a9Sjmcneill 	if (ipl != IPL_VM) {
533532c83a9Sjmcneill 		device_printf(sc->sc_dev, "%s: only IPL_VM supported\n",
534532c83a9Sjmcneill 		    __func__);
535532c83a9Sjmcneill 		return NULL;
536532c83a9Sjmcneill 	}
537532c83a9Sjmcneill 
538532c83a9Sjmcneill 	qih = kmem_alloc(sizeof(*qih), KM_SLEEP);
539532c83a9Sjmcneill 	qih->ih_func = func;
540532c83a9Sjmcneill 	qih->ih_arg = arg;
541532c83a9Sjmcneill 	qih->ih_pin = pin;
542fcf6608cSjmcneill 	qih->ih_type = (irqmode & GPIO_INTR_LEVEL_MASK) != 0 ?
543fcf6608cSjmcneill 	    IST_LEVEL : IST_EDGE;
544db0db25dSjmcneill 	snprintf(qih->ih_name, sizeof(qih->ih_name), "pin %d", pin);
545532c83a9Sjmcneill 
546532c83a9Sjmcneill 	mutex_enter(&sc->sc_lock);
547532c83a9Sjmcneill 
548532c83a9Sjmcneill 	LIST_FOREACH(qihp, &sc->sc_intrs, ih_list) {
549532c83a9Sjmcneill 		if (qihp->ih_pin == qih->ih_pin) {
550532c83a9Sjmcneill 			mutex_exit(&sc->sc_lock);
551532c83a9Sjmcneill 			kmem_free(qih, sizeof(*qih));
552532c83a9Sjmcneill 			device_printf(sc->sc_dev,
553532c83a9Sjmcneill 			    "%s: pin %d already establish\n", __func__, pin);
554532c83a9Sjmcneill 			return NULL;
555532c83a9Sjmcneill 		}
556532c83a9Sjmcneill 	}
557532c83a9Sjmcneill 
558532c83a9Sjmcneill 	LIST_INSERT_HEAD(&sc->sc_intrs, qih, ih_list);
559532c83a9Sjmcneill 
560532c83a9Sjmcneill 	if ((irqmode & GPIO_INTR_LEVEL_MASK) != 0) {
561532c83a9Sjmcneill 		dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL;
562532c83a9Sjmcneill 		pol = (irqmode & GPIO_INTR_HIGH_LEVEL) != 0 ?
563532c83a9Sjmcneill 		    TLMM_GPIO_INTR_CFG_INTR_POL_CTL : 0;
564532c83a9Sjmcneill 	} else {
565532c83a9Sjmcneill 		KASSERT((irqmode & GPIO_INTR_EDGE_MASK) != 0);
566532c83a9Sjmcneill 		if ((irqmode & GPIO_INTR_NEG_EDGE) != 0) {
567532c83a9Sjmcneill 			dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG;
568532c83a9Sjmcneill 			pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
569532c83a9Sjmcneill 		} else if ((irqmode & GPIO_INTR_POS_EDGE) != 0) {
570532c83a9Sjmcneill 			dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS;
571532c83a9Sjmcneill 			pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
572532c83a9Sjmcneill 		} else {
573532c83a9Sjmcneill 			KASSERT((irqmode & GPIO_INTR_DOUBLE_EDGE) != 0);
574532c83a9Sjmcneill 			dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH;
575532c83a9Sjmcneill 			pol = 0;
576532c83a9Sjmcneill 		}
577532c83a9Sjmcneill 	}
578532c83a9Sjmcneill 
579532c83a9Sjmcneill 	val = RD4(sc, TLMM_GPIO_INTR_CFG(pin));
580532c83a9Sjmcneill 	val &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK;
581532c83a9Sjmcneill 	val |= __SHIFTIN(dect, TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK);
582532c83a9Sjmcneill 	val &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
583532c83a9Sjmcneill 	val |= pol;
584532c83a9Sjmcneill 	val &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK;
585532c83a9Sjmcneill 	val |= __SHIFTIN(TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM,
586532c83a9Sjmcneill 	    TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK);
587532c83a9Sjmcneill 	val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
588532c83a9Sjmcneill 	val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE;
589532c83a9Sjmcneill 	WR4(sc, TLMM_GPIO_INTR_CFG(pin), val);
590532c83a9Sjmcneill 
591532c83a9Sjmcneill 	mutex_exit(&sc->sc_lock);
592532c83a9Sjmcneill 
593db0db25dSjmcneill 	evcnt_attach_dynamic(&qih->ih_evcnt, EVCNT_TYPE_INTR,
594db0db25dSjmcneill 	    NULL, device_xname(sc->sc_dev), qih->ih_name);
595db0db25dSjmcneill 
596532c83a9Sjmcneill 	return qih;
597532c83a9Sjmcneill }
598532c83a9Sjmcneill 
599532c83a9Sjmcneill static void
600532c83a9Sjmcneill qcomgpio_intr_disestablish(void *priv, void *ih)
601532c83a9Sjmcneill {
602532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = priv;
603532c83a9Sjmcneill 	struct qcomgpio_intr_handler *qih = ih;
604532c83a9Sjmcneill 	uint32_t val;
605532c83a9Sjmcneill 
606db0db25dSjmcneill 	evcnt_detach(&qih->ih_evcnt);
607db0db25dSjmcneill 
608532c83a9Sjmcneill 	mutex_enter(&sc->sc_lock);
609532c83a9Sjmcneill 
610532c83a9Sjmcneill 	LIST_REMOVE(qih, ih_list);
611532c83a9Sjmcneill 
612532c83a9Sjmcneill 	val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
613532c83a9Sjmcneill 	val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE;
614532c83a9Sjmcneill 	WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
615532c83a9Sjmcneill 
616532c83a9Sjmcneill 	mutex_exit(&sc->sc_lock);
617532c83a9Sjmcneill 
618532c83a9Sjmcneill 	kmem_free(qih, sizeof(*qih));
619532c83a9Sjmcneill }
620532c83a9Sjmcneill 
621532c83a9Sjmcneill static bool
622532c83a9Sjmcneill qcomgpio_intr_str(void *priv, int pin, int irqmode, char *buf, size_t buflen)
623532c83a9Sjmcneill {
624532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = priv;
625532c83a9Sjmcneill 	int rv;
626532c83a9Sjmcneill 
627532c83a9Sjmcneill 	rv = snprintf(buf, buflen, "%s pin %d", device_xname(sc->sc_dev), pin);
628532c83a9Sjmcneill 
629532c83a9Sjmcneill 	return rv < buflen;
630532c83a9Sjmcneill }
631532c83a9Sjmcneill 
632532c83a9Sjmcneill static void
633532c83a9Sjmcneill qcomgpio_intr_mask(void *priv, void *ih)
634532c83a9Sjmcneill {
635532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = priv;
636532c83a9Sjmcneill 	struct qcomgpio_intr_handler *qih = ih;
637532c83a9Sjmcneill 	uint32_t val;
638532c83a9Sjmcneill 
639532c83a9Sjmcneill 	val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
640fcf6608cSjmcneill 	if (qih->ih_type == IST_LEVEL) {
641fcf6608cSjmcneill 		val &= ~TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
642fcf6608cSjmcneill 	}
643532c83a9Sjmcneill 	val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE;
644532c83a9Sjmcneill 	WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
645532c83a9Sjmcneill }
646532c83a9Sjmcneill 
647532c83a9Sjmcneill static void
648532c83a9Sjmcneill qcomgpio_intr_unmask(void *priv, void *ih)
649532c83a9Sjmcneill {
650532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = priv;
651532c83a9Sjmcneill 	struct qcomgpio_intr_handler *qih = ih;
652532c83a9Sjmcneill 	uint32_t val;
653532c83a9Sjmcneill 
654532c83a9Sjmcneill 	val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
655fcf6608cSjmcneill 	if (qih->ih_type == IST_LEVEL) {
656fcf6608cSjmcneill 		val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
657fcf6608cSjmcneill 	}
658532c83a9Sjmcneill 	val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE;
659532c83a9Sjmcneill 	WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
660532c83a9Sjmcneill }
661532c83a9Sjmcneill 
662532c83a9Sjmcneill static int
663532c83a9Sjmcneill qcomgpio_intr(void *priv)
664532c83a9Sjmcneill {
665532c83a9Sjmcneill 	struct qcomgpio_softc * const sc = priv;
666532c83a9Sjmcneill 	struct qcomgpio_intr_handler *qih;
667532c83a9Sjmcneill 	int rv = 0;
668532c83a9Sjmcneill 
669532c83a9Sjmcneill 	mutex_enter(&sc->sc_lock);
670532c83a9Sjmcneill 
671532c83a9Sjmcneill 	LIST_FOREACH(qih, &sc->sc_intrs, ih_list) {
672532c83a9Sjmcneill 		const int pin = qih->ih_pin;
673532c83a9Sjmcneill 		uint32_t val;
674532c83a9Sjmcneill 
675532c83a9Sjmcneill 		val = RD4(sc, TLMM_GPIO_INTR_STATUS(pin));
676532c83a9Sjmcneill 		if ((val & TLMM_GPIO_INTR_STATUS_INTR_STATUS) != 0) {
677db0db25dSjmcneill 			qih->ih_evcnt.ev_count++;
678db0db25dSjmcneill 
679532c83a9Sjmcneill 			rv |= qih->ih_func(qih->ih_arg);
680532c83a9Sjmcneill 
681532c83a9Sjmcneill 			val &= ~TLMM_GPIO_INTR_STATUS_INTR_STATUS;
682532c83a9Sjmcneill 			WR4(sc, TLMM_GPIO_INTR_STATUS(pin), val);
683532c83a9Sjmcneill 		}
684532c83a9Sjmcneill 	}
685532c83a9Sjmcneill 
686532c83a9Sjmcneill 	mutex_exit(&sc->sc_lock);
687532c83a9Sjmcneill 
688532c83a9Sjmcneill 	return rv;
689532c83a9Sjmcneill }
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