1*6a602769Sragge /* $NetBSD: pte.h,v 1.24 2017/05/22 17:12:11 ragge Exp $ */
2d62187c0Scgd
38026fb53Sragge /*
48026fb53Sragge * Copyright (c) 1994 Ludd, University of Lule}, Sweden.
58026fb53Sragge * All rights reserved.
68026fb53Sragge *
78026fb53Sragge * Redistribution and use in source and binary forms, with or without
88026fb53Sragge * modification, are permitted provided that the following conditions
98026fb53Sragge * are met:
108026fb53Sragge * 1. Redistributions of source code must retain the above copyright
118026fb53Sragge * notice, this list of conditions and the following disclaimer.
128026fb53Sragge * 2. Redistributions in binary form must reproduce the above copyright
138026fb53Sragge * notice, this list of conditions and the following disclaimer in the
148026fb53Sragge * documentation and/or other materials provided with the distribution.
158026fb53Sragge *
168026fb53Sragge * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
178026fb53Sragge * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
188026fb53Sragge * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
198026fb53Sragge * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
208026fb53Sragge * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
218026fb53Sragge * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
228026fb53Sragge * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
238026fb53Sragge * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
248026fb53Sragge * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
258026fb53Sragge * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
268026fb53Sragge */
278026fb53Sragge
2843bbc0f5Sragge #ifndef _VAX_PTE_H_
2943bbc0f5Sragge #define _VAX_PTE_H_
308026fb53Sragge
315d668ff9Smycroft #ifndef _LOCORE
328026fb53Sragge /*
338026fb53Sragge * VAX page table entries
348026fb53Sragge */
358026fb53Sragge struct pte {
368026fb53Sragge unsigned int pg_pfn:21; /* Page Frame Number or 0 */
377ac8ee6fSragge unsigned int pg_illegal:2; /* Don't use this bits */
388026fb53Sragge unsigned int pg_sref:1; /* Help for ref simulation */
397ac8ee6fSragge unsigned int pg_w:1; /* Wired bit */
408026fb53Sragge unsigned int pg_z:1; /* Zero DIGITAL = 0 */
418026fb53Sragge unsigned int pg_m:1; /* Modify DIGITAL */
428026fb53Sragge unsigned int pg_prot:4; /* reserved at zero */
438026fb53Sragge unsigned int pg_v:1; /* valid bit */
448026fb53Sragge };
458026fb53Sragge
468026fb53Sragge
47d96cac4bSragge typedef struct pte pt_entry_t; /* Mach page table entry */
488026fb53Sragge
49023bdd2bSsimonb #endif /* _LOCORE */
508026fb53Sragge
518026fb53Sragge #define PG_V 0x80000000
528026fb53Sragge #define PG_NV 0x00000000
538026fb53Sragge #define PG_PROT 0x78000000
548026fb53Sragge #define PG_RW 0x20000000
558026fb53Sragge #define PG_KW 0x10000000
564fb1817eSragge #define PG_KR 0x18000000
57e7749341Sragge #define PG_URKW 0x70000000
588026fb53Sragge #define PG_RO 0x78000000
598026fb53Sragge #define PG_NONE 0x00000000
608026fb53Sragge #define PG_M 0x04000000
617ac8ee6fSragge #define PG_W 0x01000000
628026fb53Sragge #define PG_SREF 0x00800000
637ac8ee6fSragge #define PG_ILLEGAL 0x00600000
648026fb53Sragge #define PG_FRAME 0x001fffff
65373e7cc8Sragge #define PG_PFNUM(x) (((unsigned long)(x) & 0x3ffffe00) >> VAX_PGSHIFT)
668026fb53Sragge
675d668ff9Smycroft #ifndef _LOCORE
684fb1817eSragge extern pt_entry_t *Sysmap;
698026fb53Sragge /*
708026fb53Sragge * Kernel virtual address to page table entry and to physical address.
718026fb53Sragge */
728026fb53Sragge #endif
738026fb53Sragge
748293b121Sragge #ifdef __GNUC__
750e5be1dcSmatt #define kvtopte(va) kvtopte0((vaddr_t) (va))
760e5be1dcSmatt static inline struct pte *
kvtopte0(vaddr_t va)770e5be1dcSmatt kvtopte0(vaddr_t va)
780e5be1dcSmatt {
790e5be1dcSmatt struct pte *pt;
800e5be1dcSmatt #ifdef _RUMPKERNEL
810e5be1dcSmatt __asm(
820e5be1dcSmatt "extzv $9,$21,%1,%0\n\t"
830e5be1dcSmatt "moval %2[%0],%0\n\t"
840e5be1dcSmatt : "=r"(pt)
850e5be1dcSmatt : "g"(va), "o"(*Sysmap));
860e5be1dcSmatt #else
870e5be1dcSmatt __asm(
880e5be1dcSmatt "extzv $9,$21,%1,%0\n\t"
890e5be1dcSmatt "moval *Sysmap[%0],%0\n\t"
900e5be1dcSmatt : "=r"(pt)
910e5be1dcSmatt : "g"(va));
920e5be1dcSmatt #endif
930e5be1dcSmatt return pt;
940e5be1dcSmatt }
950e5be1dcSmatt
960e5be1dcSmatt #define kvtophys(va) kvtophys0((vaddr_t) (va))
970e5be1dcSmatt static inline paddr_t
kvtophys0(vaddr_t va)980e5be1dcSmatt kvtophys0(vaddr_t va)
990e5be1dcSmatt {
1000e5be1dcSmatt paddr_t pa;
1010e5be1dcSmatt #ifdef _RUMPKERNEL
1020e5be1dcSmatt __asm(
1030e5be1dcSmatt "extzv $9,$21,%1,%0\n\t"
1040e5be1dcSmatt "ashl $9,%2[%0],%0\n\t"
1050e5be1dcSmatt "insv %1,$0,$9,%0\n\t"
1060e5be1dcSmatt : "=&r"(pa)
1070e5be1dcSmatt : "g"(va), "o"(*Sysmap) : "cc");
1080e5be1dcSmatt #else
1090e5be1dcSmatt __asm(
1100e5be1dcSmatt "extzv $9,$21,%1,%0\n\t"
1110e5be1dcSmatt "ashl $9,*Sysmap[%0],%0\n\t"
1120e5be1dcSmatt "insv %1,$0,$9,%0\n\t"
1130e5be1dcSmatt : "=&r"(pa)
1140e5be1dcSmatt : "g"(va) : "cc");
1150e5be1dcSmatt #endif
1160e5be1dcSmatt return pa;
1170e5be1dcSmatt }
1188293b121Sragge #else /* __GNUC__ */
1198026fb53Sragge #define kvtophys(va) \
1202116915aSchs (((kvtopte(va))->pg_pfn << VAX_PGSHIFT) | ((paddr_t)(va) & VAX_PGOFSET))
1218293b121Sragge #define kvtopte(va) (&Sysmap[PG_PFNUM(va)])
1228293b121Sragge #endif /* __GNUC__ */
1231bc66055Sragge #define uvtopte(va, pcb) \
1242116915aSchs (((vaddr_t)va < 0x40000000) ? \
1252116915aSchs &(((pcb)->P0BR)[PG_PFNUM(va)]) : \
1262116915aSchs &(((pcb)->P1BR)[PG_PFNUM(va)]))
12743bbc0f5Sragge
12843bbc0f5Sragge #endif
129