1*32cded6cSdholland /* $NetBSD: memerr.h,v 1.4 2018/02/08 09:05:18 dholland Exp $ */ 2fa2d8c6eSgwr 3fa2d8c6eSgwr /* 4fa2d8c6eSgwr * Copyright (c) 1992, 1993 5fa2d8c6eSgwr * The Regents of the University of California. All rights reserved. 6fa2d8c6eSgwr * 7fa2d8c6eSgwr * This software was developed by the Computer Systems Engineering group 8fa2d8c6eSgwr * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9fa2d8c6eSgwr * contributed to Berkeley. 10fa2d8c6eSgwr * 11fa2d8c6eSgwr * All advertising materials mentioning features or use of this software 12fa2d8c6eSgwr * must display the following acknowledgement: 13fa2d8c6eSgwr * This product includes software developed by the University of 14fa2d8c6eSgwr * California, Lawrence Berkeley Laboratory. 15fa2d8c6eSgwr * 16fa2d8c6eSgwr * Redistribution and use in source and binary forms, with or without 17fa2d8c6eSgwr * modification, are permitted provided that the following conditions 18fa2d8c6eSgwr * are met: 19fa2d8c6eSgwr * 1. Redistributions of source code must retain the above copyright 20fa2d8c6eSgwr * notice, this list of conditions and the following disclaimer. 21fa2d8c6eSgwr * 2. Redistributions in binary form must reproduce the above copyright 22fa2d8c6eSgwr * notice, this list of conditions and the following disclaimer in the 23fa2d8c6eSgwr * documentation and/or other materials provided with the distribution. 24aad01611Sagc * 3. Neither the name of the University nor the names of its contributors 25fa2d8c6eSgwr * may be used to endorse or promote products derived from this software 26fa2d8c6eSgwr * without specific prior written permission. 27fa2d8c6eSgwr * 28fa2d8c6eSgwr * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29fa2d8c6eSgwr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30fa2d8c6eSgwr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31fa2d8c6eSgwr * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32fa2d8c6eSgwr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33fa2d8c6eSgwr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34fa2d8c6eSgwr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35fa2d8c6eSgwr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36fa2d8c6eSgwr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37fa2d8c6eSgwr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38fa2d8c6eSgwr * SUCH DAMAGE. 39fa2d8c6eSgwr * 40fa2d8c6eSgwr * @(#)memreg.h 8.1 (Berkeley) 6/11/93 41fa2d8c6eSgwr */ 42fa2d8c6eSgwr 43fa2d8c6eSgwr /* 44fa2d8c6eSgwr * Sun3 memory error register. 45fa2d8c6eSgwr * 46fa2d8c6eSgwr * All Sun3 memory systems use either parity checking or 47fa2d8c6eSgwr * Error Correction Coding (ECC). A memory error causes 48fa2d8c6eSgwr * the Memory Error Register (MER) to latch information 49fa2d8c6eSgwr * about the location and type of error, and if the MER 50fa2d8c6eSgwr * interrupt is enabled, generateds a level 7 interrupt. 51fa2d8c6eSgwr * The latched information persists (even if more errors 52fa2d8c6eSgwr * occur) until the MER is cleared by a write (at mer_er). 53fa2d8c6eSgwr */ 54fa2d8c6eSgwr 55fa2d8c6eSgwr 56fa2d8c6eSgwr struct memerr { 57fa2d8c6eSgwr volatile u_char me_csr; /* MER control/status reg. */ 58fa2d8c6eSgwr volatile u_char me__pad[3]; 59fa2d8c6eSgwr volatile u_int me_vaddr; 60fa2d8c6eSgwr }; 61fa2d8c6eSgwr 62fa2d8c6eSgwr /* 63fa2d8c6eSgwr * Bits in me_csr common between ECC/parity memory systems: 64fa2d8c6eSgwr */ 65fa2d8c6eSgwr #define ME_CSR_IPEND 0x80 /* (ro) error interrupt pending */ 66fa2d8c6eSgwr #define ME_CSR_IENA 0x40 /* (rw) error interrupt enable */ 67fa2d8c6eSgwr 68fa2d8c6eSgwr /* 69fa2d8c6eSgwr * Bits in me_csr on parity-checked memory system: 70fa2d8c6eSgwr */ 71fa2d8c6eSgwr #define ME_PAR_TEST 0x20 /* (rw) write inverse parity */ 72fa2d8c6eSgwr #define ME_PAR_CHECK 0x10 /* (rw) enable parity checking */ 73fa2d8c6eSgwr #define ME_PAR_ERR3 0x08 /* (ro) parity error in <24..31> */ 74fa2d8c6eSgwr #define ME_PAR_ERR2 0x04 /* (ro) parity error in <16..23> */ 75fa2d8c6eSgwr #define ME_PAR_ERR1 0x02 /* (ro) parity error in <8..15> */ 76fa2d8c6eSgwr #define ME_PAR_ERR0 0x01 /* (ro) parity error in <0..7> */ 77fa2d8c6eSgwr #define ME_PAR_EMASK 0x0F /* (ro) mask of above four */ 78fa2d8c6eSgwr #define ME_PAR_STR "\20\10IPEND\7IENA\6TEST\5CHK\4ERR3\3ERR2\2ERR1\1ERR0" 79fa2d8c6eSgwr 80fa2d8c6eSgwr /* 81fa2d8c6eSgwr * Bits in me_csr on an ECC memory system: 82fa2d8c6eSgwr */ 83fa2d8c6eSgwr #define ME_ECC_BUSLK 0x20 /* (rw) hold memory bus mastership */ 84fa2d8c6eSgwr #define ME_ECC_CE_ENA 0x10 /* (rw) enable CE recording */ 85fa2d8c6eSgwr #define ME_ECC_WBTMO 0x08 /* (ro) write-back timeout */ 86fa2d8c6eSgwr #define ME_ECC_WBERR 0x04 /* (ro) write-back error */ 87fa2d8c6eSgwr #define ME_ECC_UE 0x02 /* (ro) UE, uncorrectable error */ 88fa2d8c6eSgwr #define ME_ECC_CE 0x01 /* (ro) CE, correctable (single bit) error */ 89*32cded6cSdholland #define ME_ECC_EMASK 0x0F /* (ro) mask for some ECC error occurring */ 90fa2d8c6eSgwr #define ME_ECC_STR "\20\10IPEND\7IENA\6BUSLK\5CE_ENA\4TMOUT\3WBERR\2UE\1CE" 91fa2d8c6eSgwr 92