xref: /netbsd-src/sys/arch/sparc64/include/pmap.h (revision 07acc2d1697896679fc953ab69d727b894604483)
1*07acc2d1Smrg /*	$NetBSD: pmap.h,v 1.64 2020/09/06 10:48:21 mrg Exp $	*/
201e2e698Seeh 
301e2e698Seeh /*-
401e2e698Seeh  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
501e2e698Seeh  * Copyright (C) 1995, 1996 TooLs GmbH.
601e2e698Seeh  * All rights reserved.
701e2e698Seeh  *
801e2e698Seeh  * Redistribution and use in source and binary forms, with or without
901e2e698Seeh  * modification, are permitted provided that the following conditions
1001e2e698Seeh  * are met:
1101e2e698Seeh  * 1. Redistributions of source code must retain the above copyright
1201e2e698Seeh  *    notice, this list of conditions and the following disclaimer.
1301e2e698Seeh  * 2. Redistributions in binary form must reproduce the above copyright
1401e2e698Seeh  *    notice, this list of conditions and the following disclaimer in the
1501e2e698Seeh  *    documentation and/or other materials provided with the distribution.
1601e2e698Seeh  * 3. All advertising materials mentioning features or use of this software
1701e2e698Seeh  *    must display the following acknowledgement:
1801e2e698Seeh  *	This product includes software developed by TooLs GmbH.
1901e2e698Seeh  * 4. The name of TooLs GmbH may not be used to endorse or promote products
2001e2e698Seeh  *    derived from this software without specific prior written permission.
2101e2e698Seeh  *
2201e2e698Seeh  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
2301e2e698Seeh  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
2401e2e698Seeh  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
2501e2e698Seeh  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2601e2e698Seeh  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
2701e2e698Seeh  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
2801e2e698Seeh  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
2901e2e698Seeh  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
3001e2e698Seeh  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
3101e2e698Seeh  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3201e2e698Seeh  */
3301e2e698Seeh 
3401e2e698Seeh #ifndef	_MACHINE_PMAP_H_
3501e2e698Seeh #define	_MACHINE_PMAP_H_
3601e2e698Seeh 
3701e2e698Seeh #ifndef _LOCORE
3801e2e698Seeh #include <machine/pte.h>
3901e2e698Seeh #include <sys/queue.h>
40*07acc2d1Smrg struct vm_page;
41*07acc2d1Smrg #include <uvm/uvm_prot.h>
42*07acc2d1Smrg #include <uvm/uvm_pmap.h>
43f54a093eSchs #include <uvm/uvm_object.h>
44e27fd72eSpooka #ifdef _KERNEL
45e27fd72eSpooka #include <machine/cpuset.h>
4628626d96Spalle #ifdef SUN4V
47f4df0c24Snakayama #include <machine/hypervisor.h>
4828626d96Spalle #endif
49e27fd72eSpooka #endif
5001e2e698Seeh #endif
5101e2e698Seeh 
5201e2e698Seeh /*
5301e2e698Seeh  * This scheme uses 2-level page tables.
5401e2e698Seeh  *
5501e2e698Seeh  * While we're still in 32-bit mode we do the following:
5601e2e698Seeh  *
5701e2e698Seeh  *   offset:						13 bits
5801e2e698Seeh  * 1st level: 1024 64-bit TTEs in an 8K page for	10 bits
5901e2e698Seeh  * 2nd level: 512 32-bit pointers in the pmap for 	 9 bits
6001e2e698Seeh  *							-------
6101e2e698Seeh  * total:						32 bits
6201e2e698Seeh  *
63a465fdedSeeh  * In 64-bit mode the Spitfire and Blackbird CPUs support only
64a465fdedSeeh  * 44-bit virtual addresses.  All addresses between
65a465fdedSeeh  * 0x0000 07ff ffff ffff and 0xffff f800 0000 0000 are in the
66a465fdedSeeh  * "VA hole" and trap, so we don't have to track them.  However,
67a465fdedSeeh  * we do need to keep them in mind during PT walking.  If they
68a465fdedSeeh  * ever change the size of the address "hole" we need to rework
69a465fdedSeeh  * all the page table handling.
7001e2e698Seeh  *
7101e2e698Seeh  *   offset:						13 bits
7201e2e698Seeh  * 1st level: 1024 64-bit TTEs in an 8K page for	10 bits
7301e2e698Seeh  * 2nd level: 1024 64-bit pointers in an 8K page for 	10 bits
74a465fdedSeeh  * 3rd level: 1024 64-bit pointers in the segmap for 	10 bits
7501e2e698Seeh  *							-------
76a465fdedSeeh  * total:						43 bits
77a465fdedSeeh  *
78a465fdedSeeh  * Of course, this means for 32-bit spaces we always have a (practically)
79a465fdedSeeh  * wasted page for the segmap (only one entry used) and half a page wasted
80a465fdedSeeh  * for the page directory.  We still have need of one extra bit 8^(.
8101e2e698Seeh  */
8201e2e698Seeh 
83a465fdedSeeh #define HOLESHIFT	(43)
84a465fdedSeeh 
85c1d895baSheas #define PTSZ	(PAGE_SIZE/8)			/* page table entry */
86c1d895baSheas #define PDSZ	(PTSZ)				/* page directory */
87c1d895baSheas #define STSZ	(PTSZ)				/* psegs */
8801e2e698Seeh 
8901e2e698Seeh #define PTSHIFT		(13)
90a465fdedSeeh #define	PDSHIFT		(10+PTSHIFT)
91a465fdedSeeh #define STSHIFT		(10+PDSHIFT)
9201e2e698Seeh 
9301e2e698Seeh #define PTMASK		(PTSZ-1)
94a465fdedSeeh #define PDMASK		(PDSZ-1)
9501e2e698Seeh #define STMASK		(STSZ-1)
9601e2e698Seeh 
9701e2e698Seeh #ifndef _LOCORE
9801e2e698Seeh 
994073f873Smartin #ifdef _LP64
1004073f873Smartin int	sparc64_mmap_range_test(vaddr_t, vaddr_t);
1014073f873Smartin #define	MD_MMAP_RANGE_TEST(MINVA, MAXVA)	sparc64_mmap_range_test(MINVA, MAXVA)
1024073f873Smartin #endif
1034073f873Smartin 
10401e2e698Seeh /*
10501e2e698Seeh  * Support for big page sizes.  This maps the page size to the
10601e2e698Seeh  * page bits.
10701e2e698Seeh  */
10801e2e698Seeh struct page_size_map {
109d50f0c62Scdi 	uint64_t mask;
110d50f0c62Scdi 	uint64_t code;
1111fcd5ac5Smrg #if defined(DEBUG) || 1
112d50f0c62Scdi 	uint64_t use;
11301e2e698Seeh #endif
11401e2e698Seeh };
11501e2e698Seeh extern struct page_size_map page_size_map[];
11601e2e698Seeh 
11701e2e698Seeh /*
11801e2e698Seeh  * Pmap stuff
11901e2e698Seeh  */
12001e2e698Seeh 
121a465fdedSeeh #define va_to_seg(v)	(int)((((paddr_t)(v))>>STSHIFT)&STMASK)
122a465fdedSeeh #define va_to_dir(v)	(int)((((paddr_t)(v))>>PDSHIFT)&PDMASK)
123a465fdedSeeh #define va_to_pte(v)	(int)((((paddr_t)(v))>>PTSHIFT)&PTMASK)
12401e2e698Seeh 
125fbca096aSmrg #ifdef MULTIPROCESSOR
126fbca096aSmrg #define PMAP_LIST_MAXNUMCPU	CPUSET_MAXNUMCPU
127fbca096aSmrg #else
128fbca096aSmrg #define PMAP_LIST_MAXNUMCPU	1
129fbca096aSmrg #endif
130fbca096aSmrg 
13101e2e698Seeh struct pmap {
132881d12e6Sad 	unsigned int pm_refs;
133881d12e6Sad 	TAILQ_HEAD(, vm_page) pm_ptps;
134fbca096aSmrg 	LIST_ENTRY(pmap) pm_list[PMAP_LIST_MAXNUMCPU];	/* per cpu ctx used list */
1351ecf66dbSmartin 
1361ecf66dbSmartin 	struct pmap_statistics pm_stats;
1371ecf66dbSmartin 
138a9e7d15aSmartin 	/*
139a9e7d15aSmartin 	 * We record the context used on any cpu here. If the context
140a9e7d15aSmartin 	 * is actually present in the TLB, it will be the plain context
141a9e7d15aSmartin 	 * number. If the context is allocated, but has been flushed
142a9e7d15aSmartin 	 * from the tlb, the number will be negative.
143a9e7d15aSmartin 	 * If this pmap has no context allocated on that cpu, the entry
144a9e7d15aSmartin 	 * will be 0.
145a9e7d15aSmartin 	 */
146fbca096aSmrg 	int pm_ctx[PMAP_LIST_MAXNUMCPU];	/* Current context per cpu */
147f54a093eSchs 
148a465fdedSeeh 	/*
149a465fdedSeeh 	 * This contains 64-bit pointers to pages that contain
150a465fdedSeeh 	 * 1024 64-bit pointers to page tables.  All addresses
151a465fdedSeeh 	 * are physical.
152a465fdedSeeh 	 *
153a465fdedSeeh 	 * !!! Only touch this through pseg_get() and pseg_set() !!!
154a465fdedSeeh 	 */
155a2dd74edSeeh 	paddr_t pm_physaddr;	/* physical address of pm_segs */
156a465fdedSeeh 	int64_t *pm_segs;
15701e2e698Seeh };
15801e2e698Seeh 
15901e2e698Seeh /*
16001e2e698Seeh  * This comes from the PROM and is used to map prom entries.
16101e2e698Seeh  */
16201e2e698Seeh struct prom_map {
163d50f0c62Scdi 	uint64_t	vstart;
164d50f0c62Scdi 	uint64_t	vsize;
165d50f0c62Scdi 	uint64_t	tte;
16601e2e698Seeh };
16701e2e698Seeh 
1687a874cfdSmacallan #define PMAP_NC		0x001	/* Don't cache, set the E bit in the page */
1696492e81aSeeh #define PMAP_NVC	0x002	/* Don't enable the virtual cache */
1706492e81aSeeh #define PMAP_LITTLE	0x004	/* Map in little endian mode */
171f54a093eSchs /* Large page size hints --
172f54a093eSchs    we really should use another param to pmap_enter() */
1736492e81aSeeh #define PMAP_8K		0x000
1746492e81aSeeh #define PMAP_64K	0x008	/* Use 64K page */
1756492e81aSeeh #define PMAP_512K	0x010
1766492e81aSeeh #define PMAP_4M		0x018
1776492e81aSeeh #define PMAP_SZ_TO_TTE(x)	(((x)&0x018)<<58)
178f54a093eSchs /* If these bits are different in va's to the same PA
179f54a093eSchs    then there is an aliasing in the d$ */
180b062992fSpetrov #define VA_ALIAS_MASK   (1 << 13)
1817a874cfdSmacallan #define PMAP_WC		0x20	/* allow write combinimg */
18201e2e698Seeh 
18301e2e698Seeh #ifdef	_KERNEL
1841ecf66dbSmartin #ifdef PMAP_COUNT_DEBUG
1851ecf66dbSmartin /* diagnostic versions if PMAP_COUNT_DEBUG option is used */
186d0f8217fScdi int pmap_count_res(struct pmap *);
187d0f8217fScdi int pmap_count_wired(struct pmap *);
18801e2e698Seeh #define	pmap_resident_count(pm)		pmap_count_res((pm))
18959c12af6Schs #define	pmap_wired_count(pm)		pmap_count_wired((pm))
1901ecf66dbSmartin #else
1911ecf66dbSmartin #define	pmap_resident_count(pm)		((pm)->pm_stats.resident_count)
1921ecf66dbSmartin #define	pmap_wired_count(pm)		((pm)->pm_stats.wired_count)
1931ecf66dbSmartin #endif
1941ecf66dbSmartin 
195766a9b8cSeeh #define	pmap_phys_address(x)		(x)
196f54a093eSchs 
197f54a093eSchs void pmap_activate_pmap(struct pmap *);
198cec587ddSchs void pmap_update(struct pmap *);
199d0f8217fScdi void pmap_bootstrap(u_long, u_long);
2009c098a4bSmartin 
2012c1410f8Seeh /* make sure all page mappings are modulo 16K to prevent d$ aliasing */
2029c098a4bSmartin #define	PMAP_PREFER(fo, va, sz, td)	pmap_prefer((fo), (va), (td))
2039c098a4bSmartin static inline void
pmap_prefer(vaddr_t fo,vaddr_t * va,int td)2049c098a4bSmartin pmap_prefer(vaddr_t fo, vaddr_t *va, int td)
2059c098a4bSmartin {
2069c098a4bSmartin 	vaddr_t newva;
2079c098a4bSmartin 	vaddr_t m;
2089c098a4bSmartin 
2099c098a4bSmartin 	m = 2 * PAGE_SIZE;
2109c098a4bSmartin 	newva = (*va & ~(m - 1)) | (fo & (m - 1));
2119c098a4bSmartin 
2129c098a4bSmartin 	if (td) {
2139c098a4bSmartin 		if (newva > *va)
2149c098a4bSmartin 			newva -= m;
2159c098a4bSmartin 	} else {
2169c098a4bSmartin 		if (newva < *va)
2179c098a4bSmartin 			newva += m;
2189c098a4bSmartin 	}
2199c098a4bSmartin 	*va = newva;
2209c098a4bSmartin }
22101e2e698Seeh 
222400b7c8eSeeh #define	PMAP_GROWKERNEL         /* turn on pmap_growkernel interface */
223f54a093eSchs #define PMAP_NEED_PROCWR
224f54a093eSchs 
225f54a093eSchs void pmap_procwr(struct proc *, vaddr_t, size_t);
226400b7c8eSeeh 
22701e2e698Seeh /* SPARC specific? */
228d0f8217fScdi int             pmap_dumpsize(void);
22953524e44Schristos int             pmap_dumpmmu(int (*)(dev_t, daddr_t, void *, size_t),
230d0f8217fScdi                                  daddr_t);
231d0f8217fScdi int		pmap_pa_exists(paddr_t);
232d0f8217fScdi void		switchexit(struct lwp *, int);
233939df36eSchs void		pmap_kprotect(vaddr_t, vm_prot_t);
23401e2e698Seeh 
23589841bfdSmrg /* SPARC64 specific */
23689841bfdSmrg void		pmap_copy_page_phys(paddr_t, paddr_t);
23789841bfdSmrg void		pmap_zero_page_phys(paddr_t);
23889841bfdSmrg 
239f4d9eaa0Spalle #ifdef SUN4V
240f4d9eaa0Spalle /* sun4v specific */
241f4d9eaa0Spalle void		pmap_setup_intstack_sun4v(paddr_t);
24228626d96Spalle void		pmap_setup_tsb_sun4v(struct tsb_desc*);
243f4d9eaa0Spalle #endif
244f4d9eaa0Spalle 
2454c2e4320Scdi /* Installed physical memory, as discovered during bootstrap. */
2464c2e4320Scdi extern int phys_installed_size;
2474c2e4320Scdi extern struct mem_region *phys_installed;
2484c2e4320Scdi 
2495d7952a5Suebayasi #define	__HAVE_VM_PAGE_MD
2505d7952a5Suebayasi 
2515d7952a5Suebayasi /*
2525d7952a5Suebayasi  * For each struct vm_page, there is a list of all currently valid virtual
2535d7952a5Suebayasi  * mappings of that page.  An entry is a pv_entry_t.
2545d7952a5Suebayasi  */
2555d7952a5Suebayasi struct pmap;
2565d7952a5Suebayasi typedef struct pv_entry {
2575d7952a5Suebayasi 	struct pv_entry	*pv_next;	/* next pv_entry */
2585d7952a5Suebayasi 	struct pmap	*pv_pmap;	/* pmap where mapping lies */
2595d7952a5Suebayasi 	vaddr_t		pv_va;		/* virtual address for mapping */
2605d7952a5Suebayasi } *pv_entry_t;
2615d7952a5Suebayasi /* PV flags encoded in the low bits of the VA of the first pv_entry */
2625d7952a5Suebayasi 
2635d7952a5Suebayasi struct vm_page_md {
2645d7952a5Suebayasi 	struct pv_entry mdpg_pvh;
2655d7952a5Suebayasi };
2665d7952a5Suebayasi #define	VM_MDPAGE_INIT(pg)						\
2675d7952a5Suebayasi do {									\
2685d7952a5Suebayasi 	(pg)->mdpage.mdpg_pvh.pv_next = NULL;				\
2695d7952a5Suebayasi 	(pg)->mdpage.mdpg_pvh.pv_pmap = NULL;				\
2705d7952a5Suebayasi 	(pg)->mdpage.mdpg_pvh.pv_va = 0;				\
2715d7952a5Suebayasi } while (/*CONSTCOND*/0)
2725d7952a5Suebayasi 
27326737785Smrg #ifdef MULTIPROCESSOR
27426737785Smrg #define pmap_ctx_cpu(PM, C)	((PM)->pm_ctx[(C)])
27526737785Smrg #define pmap_ctx(PM)		pmap_ctx_cpu((PM), cpu_number())
27626737785Smrg #else
27726737785Smrg #define pmap_ctx(PM)		((PM)->pm_ctx[0])
27826737785Smrg #endif
27926737785Smrg 
28001e2e698Seeh #endif	/* _KERNEL */
28110516949Smrg 
282c51e03edSmartin #endif	/* _LOCORE */
28301e2e698Seeh #endif	/* _MACHINE_PMAP_H_ */
284