1*6238d5faSjnemeth /* $NetBSD: fdcreg.h,v 1.1 2006/10/06 08:44:59 jnemeth Exp $ */ 2*6238d5faSjnemeth 3*6238d5faSjnemeth /*- 4*6238d5faSjnemeth * Copyright (c) 1991 The Regents of the University of California. 5*6238d5faSjnemeth * All rights reserved. 6*6238d5faSjnemeth * 7*6238d5faSjnemeth * Redistribution and use in source and binary forms, with or without 8*6238d5faSjnemeth * modification, are permitted provided that the following conditions 9*6238d5faSjnemeth * are met: 10*6238d5faSjnemeth * 1. Redistributions of source code must retain the above copyright 11*6238d5faSjnemeth * notice, this list of conditions and the following disclaimer. 12*6238d5faSjnemeth * 2. Redistributions in binary form must reproduce the above copyright 13*6238d5faSjnemeth * notice, this list of conditions and the following disclaimer in the 14*6238d5faSjnemeth * documentation and/or other materials provided with the distribution. 15*6238d5faSjnemeth * 3. Neither the name of the University nor the names of its contributors 16*6238d5faSjnemeth * may be used to endorse or promote products derived from this software 17*6238d5faSjnemeth * without specific prior written permission. 18*6238d5faSjnemeth * 19*6238d5faSjnemeth * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20*6238d5faSjnemeth * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21*6238d5faSjnemeth * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22*6238d5faSjnemeth * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23*6238d5faSjnemeth * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24*6238d5faSjnemeth * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25*6238d5faSjnemeth * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26*6238d5faSjnemeth * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27*6238d5faSjnemeth * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28*6238d5faSjnemeth * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29*6238d5faSjnemeth * SUCH DAMAGE. 30*6238d5faSjnemeth * 31*6238d5faSjnemeth * @(#)fdreg.h 7.1 (Berkeley) 5/9/91 32*6238d5faSjnemeth */ 33*6238d5faSjnemeth 34*6238d5faSjnemeth /* 35*6238d5faSjnemeth * AT floppy controller registers and bitfields 36*6238d5faSjnemeth */ 37*6238d5faSjnemeth 38*6238d5faSjnemeth /* uses NEC765 controller */ 39*6238d5faSjnemeth #include <dev/ic/nec765reg.h> 40*6238d5faSjnemeth 41*6238d5faSjnemeth /* 42*6238d5faSjnemeth * Register offsets for the 82077 controller. 43*6238d5faSjnemeth */ 44*6238d5faSjnemeth #define FDREG77_STATUSA 0 45*6238d5faSjnemeth #define FDREG77_STATUSB 1 46*6238d5faSjnemeth #define FDREG77_DOR 2 /* Digital Output Register (R/W) */ 47*6238d5faSjnemeth #define FDREG77_TDR 3 /* Tape Control Register (R/W) */ 48*6238d5faSjnemeth #define FDREG77_MSR 4 /* Main Status Register (R) */ 49*6238d5faSjnemeth #define FDREG77_DRS 4 /* Data Rate Select Register (W) */ 50*6238d5faSjnemeth #define FDREG77_FIFO 5 /* Data (FIFO) register (R/W) */ 51*6238d5faSjnemeth #define FDREG77_DIR 7 /* Digital Input Register (R) */ 52*6238d5faSjnemeth #define FDREG77_CCR 7 /* Configuration Control (W) */ 53*6238d5faSjnemeth 54*6238d5faSjnemeth /* 55*6238d5faSjnemeth * Register offsets for the 82072 controller. 56*6238d5faSjnemeth */ 57*6238d5faSjnemeth #define FDREG72_MSR 0 /* Main Status Register (R) */ 58*6238d5faSjnemeth #define FDREG72_DRS 0 /* Data Rate Select Register (W) */ 59*6238d5faSjnemeth #define FDREG72_FIFO 1 /* Data (FIFO) register (R/W) */ 60*6238d5faSjnemeth 61*6238d5faSjnemeth 62*6238d5faSjnemeth /* Data Select Register bits */ 63*6238d5faSjnemeth #define DRS_RESET 0x80 64*6238d5faSjnemeth #define DRS_POWER 0x40 65*6238d5faSjnemeth #define DRS_PLL 0x20 66*6238d5faSjnemeth #define FDC_500KBPS 0x00 /* 500KBPS MFM drive transfer rate */ 67*6238d5faSjnemeth #define FDC_300KBPS 0x01 /* 300KBPS MFM drive transfer rate */ 68*6238d5faSjnemeth #define FDC_250KBPS 0x02 /* 250KBPS MFM drive transfer rate */ 69*6238d5faSjnemeth #define FDC_125KBPS 0x03 /* 125KBPS FM drive transfer rate */ 70*6238d5faSjnemeth 71*6238d5faSjnemeth /* Digital Output Register bits (modified on suns) */ 72*6238d5faSjnemeth #define FDO_DS 0x01 /* floppy device select (neg) */ 73*6238d5faSjnemeth #define FDO_FRST 0x04 /* floppy controller reset (neg) */ 74*6238d5faSjnemeth #define FDO_FDMAEN 0x08 /* enable floppy DMA and Interrupt */ 75*6238d5faSjnemeth #define FDO_MOEN(n) ((1 << n) << 4) /* motor enable */ 76*6238d5faSjnemeth #define FDO_DEN 0x40 /* Density select */ 77*6238d5faSjnemeth #define FDO_EJ 0x80 /* Eject disk */ 78*6238d5faSjnemeth 79*6238d5faSjnemeth /* Digital Input Register bits */ 80*6238d5faSjnemeth #define FDI_DCHG 0x80 /* diskette has been changed */ 81*6238d5faSjnemeth 82*6238d5faSjnemeth /* XXX - find a place for these... */ 83*6238d5faSjnemeth #define NE7CMD_CFG 0x13 84*6238d5faSjnemeth #define CFG_EIS 0x40 85*6238d5faSjnemeth #define CFG_EFIFO 0x20 86*6238d5faSjnemeth #define CFG_POLL 0x10 87*6238d5faSjnemeth #define CFG_THRHLD_MASK 0x0f 88*6238d5faSjnemeth 89*6238d5faSjnemeth #define NE7CMD_LOCK 0x14 90*6238d5faSjnemeth #define CFG_LOCK 0x80 91*6238d5faSjnemeth 92*6238d5faSjnemeth #define NE7CMD_MOTOR 0x0b 93*6238d5faSjnemeth #define MOTOR_ON 0x80 94*6238d5faSjnemeth 95*6238d5faSjnemeth #define NE7CMD_DUMPREG 0x0e 96*6238d5faSjnemeth #define NE7CMD_VERSION 0x10 97*6238d5faSjnemeth 98*6238d5faSjnemeth #define ST1_OVERRUN 0x10 99*6238d5faSjnemeth 100*6238d5faSjnemeth #define NE7_SPECIFY_NODMA 0x01 101