1*1daa1a7bSandvar /* $NetBSD: mmu.h,v 1.11 2022/02/23 21:54:40 andvar Exp $ */ 2780de330Such 3780de330Such /*- 4780de330Such * Copyright (c) 2002 The NetBSD Foundation, Inc. 5780de330Such * All rights reserved. 6780de330Such * 7780de330Such * This code is derived from software contributed to The NetBSD Foundation 8780de330Such * by UCHIYAMA Yasushi. 9780de330Such * 10780de330Such * Redistribution and use in source and binary forms, with or without 11780de330Such * modification, are permitted provided that the following conditions 12780de330Such * are met: 13780de330Such * 1. Redistributions of source code must retain the above copyright 14780de330Such * notice, this list of conditions and the following disclaimer. 15780de330Such * 2. Redistributions in binary form must reproduce the above copyright 16780de330Such * notice, this list of conditions and the following disclaimer in the 17780de330Such * documentation and/or other materials provided with the distribution. 18780de330Such * 19780de330Such * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20780de330Such * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21780de330Such * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22780de330Such * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23780de330Such * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24780de330Such * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25780de330Such * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26780de330Such * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27780de330Such * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28780de330Such * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29780de330Such * POSSIBILITY OF SUCH DAMAGE. 30780de330Such */ 31780de330Such 32780de330Such #ifndef _SH3_MMU_H_ 33780de330Such #define _SH3_MMU_H_ 34780de330Such 35780de330Such /* 36780de330Such * Initialize routines. 37bf93dc9bSuch * sh_mmu_init Assign function vector. Don't access hardware. 3825196f3eSuwe * Call as early as possible. 39780de330Such * sh_mmu_start Reset TLB entry, set default ASID, and start to 4025196f3eSuwe * translate addresses. 41780de330Such * Call after exception vector was installed. 42780de330Such * 43780de330Such * TLB access ops. 44*1daa1a7bSandvar * sh_tlb_invalidate_addr invalidate TLB entries for given 45780de330Such * virtual addr with ASID. 46780de330Such * sh_tlb_invalidate_asid invalidate TLB entries for given ASID. 47bf93dc9bSuch * sh_tlb_invalidate_all invalidate all non-wired TLB entries. 48bf93dc9bSuch * sh_tlb_set_asid set ASID. 49bf93dc9bSuch * sh_tlb_update load new PTE to TLB. 50780de330Such * 51780de330Such */ 52780de330Such 53bf93dc9bSuch void sh_mmu_init(void); 54bf93dc9bSuch void sh_mmu_information(void); 55bf93dc9bSuch void sh_tlb_set_asid(int); 5625196f3eSuwe 5725196f3eSuwe #ifdef SH3 5825196f3eSuwe void sh3_mmu_start(void); 59bf93dc9bSuch void sh3_tlb_invalidate_addr(int, vaddr_t); 60bf93dc9bSuch void sh3_tlb_invalidate_asid(int); 61bf93dc9bSuch void sh3_tlb_invalidate_all(void); 62970e24eeSuwe void sh3_tlb_update(int, vaddr_t, uint32_t); 6325196f3eSuwe #endif 6425196f3eSuwe 6525196f3eSuwe #ifdef SH4 6625196f3eSuwe void sh4_mmu_start(void); 67bf93dc9bSuch void sh4_tlb_invalidate_addr(int, vaddr_t); 68bf93dc9bSuch void sh4_tlb_invalidate_asid(int); 69bf93dc9bSuch void sh4_tlb_invalidate_all(void); 70970e24eeSuwe void sh4_tlb_update(int, vaddr_t, uint32_t); 7125196f3eSuwe #endif 7225196f3eSuwe 73bf93dc9bSuch 74780de330Such #if defined(SH3) && defined(SH4) 75970e24eeSuwe extern uint32_t __sh_PTEH; 766b850c43Suwe 7725196f3eSuwe extern void (*__sh_mmu_start)(void); 7825196f3eSuwe extern void (*__sh_tlb_invalidate_addr)(int, vaddr_t); 7925196f3eSuwe extern void (*__sh_tlb_invalidate_asid)(int); 8025196f3eSuwe extern void (*__sh_tlb_invalidate_all)(void); 81970e24eeSuwe extern void (*__sh_tlb_update)(int, vaddr_t, uint32_t); 8225196f3eSuwe 8325196f3eSuwe #define sh_mmu_start() (*__sh_mmu_start)() 84780de330Such #define sh_tlb_invalidate_addr(a, va) (*__sh_tlb_invalidate_addr)(a, va) 85780de330Such #define sh_tlb_invalidate_asid(a) (*__sh_tlb_invalidate_asid)(a) 86780de330Such #define sh_tlb_invalidate_all() (*__sh_tlb_invalidate_all)() 878025d17cSuwe #define sh_tlb_update(a, va, pte) (*__sh_tlb_update)(a, va, pte) 8825196f3eSuwe 89780de330Such #elif defined(SH3) 9025196f3eSuwe 9125196f3eSuwe #define sh_mmu_start() sh3_mmu_start() 92780de330Such #define sh_tlb_invalidate_addr(a, va) sh3_tlb_invalidate_addr(a, va) 93780de330Such #define sh_tlb_invalidate_asid(a) sh3_tlb_invalidate_asid(a) 94780de330Such #define sh_tlb_invalidate_all() sh3_tlb_invalidate_all() 95bf93dc9bSuch #define sh_tlb_update(a, va, pte) sh3_tlb_update(a, va, pte) 9625196f3eSuwe 97780de330Such #elif defined(SH4) 9825196f3eSuwe 9925196f3eSuwe #define sh_mmu_start() sh4_mmu_start() 100780de330Such #define sh_tlb_invalidate_addr(a, va) sh4_tlb_invalidate_addr(a, va) 101780de330Such #define sh_tlb_invalidate_asid(a) sh4_tlb_invalidate_asid(a) 102780de330Such #define sh_tlb_invalidate_all() sh4_tlb_invalidate_all() 103bf93dc9bSuch #define sh_tlb_update(a, va, pte) sh4_tlb_update(a, va, pte) 10425196f3eSuwe 105780de330Such #endif 106780de330Such 107780de330Such #endif /* !_SH3_MMU_H_ */ 108