1*86d3d1e4Suwe /* $NetBSD: dmacreg.h,v 1.3 2007/03/29 23:09:41 uwe Exp $ */ 2c22f7712Suwe 3c22f7712Suwe /* 4c22f7712Suwe * Copyright (c) 2004 Valeriy E. Ushakov 5c22f7712Suwe * All rights reserved. 6c22f7712Suwe * 7c22f7712Suwe * Redistribution and use in source and binary forms, with or without 8c22f7712Suwe * modification, are permitted provided that the following conditions 9c22f7712Suwe * are met: 10c22f7712Suwe * 1. Redistributions of source code must retain the above copyright 11c22f7712Suwe * notice, this list of conditions and the following disclaimer. 12c22f7712Suwe * 2. Redistributions in binary form must reproduce the above copyright 13c22f7712Suwe * notice, this list of conditions and the following disclaimer in the 14c22f7712Suwe * documentation and/or other materials provided with the distribution. 15c22f7712Suwe * 3. The name of the author may not be used to endorse or promote products 16c22f7712Suwe * derived from this software without specific prior written permission 17c22f7712Suwe * 18c22f7712Suwe * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19c22f7712Suwe * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20c22f7712Suwe * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21c22f7712Suwe * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22c22f7712Suwe * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23c22f7712Suwe * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24c22f7712Suwe * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25c22f7712Suwe * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26c22f7712Suwe * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27c22f7712Suwe * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28c22f7712Suwe */ 29c22f7712Suwe 30c22f7712Suwe #ifndef _SH3_DMACREG_H_ 31c22f7712Suwe #define _SH3_DMACREG_H_ 32c22f7712Suwe 33*86d3d1e4Suwe #include <sh3/devreg.h> 34*86d3d1e4Suwe 35*86d3d1e4Suwe 36c22f7712Suwe #define SH3_DMAC_SAR0 0xa4000020 /* Source Address */ 37c22f7712Suwe #define SH3_DMAC_DAR0 0xa4000024 /* Destination Address */ 38c22f7712Suwe #define SH3_DMAC_DMATCR0 0xa4000028 /* Transfer Counter */ 39c22f7712Suwe #define SH3_DMAC_CHCR0 0xa400002c /* Channel Control */ 40c22f7712Suwe 41c22f7712Suwe #define SH3_DMAC_SAR1 0xa4000030 /* ditto for channel 1 */ 42c22f7712Suwe #define SH3_DMAC_DAR1 0xa4000034 43c22f7712Suwe #define SH3_DMAC_DMATCR1 0xa4000038 44c22f7712Suwe #define SH3_DMAC_CHCR1 0xa400003c 45c22f7712Suwe 46c22f7712Suwe #define SH3_DMAC_SAR2 0xa4000040 /* ditto for channel 2 */ 47c22f7712Suwe #define SH3_DMAC_DAR2 0xa4000044 48c22f7712Suwe #define SH3_DMAC_DMATCR2 0xa4000048 49c22f7712Suwe #define SH3_DMAC_CHCR2 0xa400004c 50c22f7712Suwe 51c22f7712Suwe #define SH3_DMAC_SAR3 0xa4000050 /* ditto for channel 3 */ 52c22f7712Suwe #define SH3_DMAC_DAR3 0xa4000054 53c22f7712Suwe #define SH3_DMAC_DMATCR3 0xa4000058 54c22f7712Suwe #define SH3_DMAC_CHCR3 0xa400005c 55c22f7712Suwe 56c22f7712Suwe #define SH3_DMAC_DMAOR 0xa4000060 /* DMA Operation Register */ 57c22f7712Suwe 58c22f7712Suwe #define SH3_DMAC_CMT_CMSTR 0xa4000070 /* CMT Start */ 59c22f7712Suwe #define SH3_DMAC_CMT_CMCSR 0xa4000072 /* CMT Control/Status */ 60c22f7712Suwe #define SH3_DMAC_CMT_CMCNT 0xa4000074 /* CMT Counter */ 61c22f7712Suwe #define SH3_DMAC_CMT_CMCOR 0xa4000076 /* CMT Constant */ 62c22f7712Suwe 63c22f7712Suwe 64c22f7712Suwe /** 65c22f7712Suwe * Only bits 0..23 of DMATCR registers are valid. 66c22f7712Suwe * Writing 0 to these registers means count of SH3_DMAC_DMATCR_MAX. 67c22f7712Suwe */ 68c22f7712Suwe #define SH3_DMAC_DMATCR_MAX 0x01000000 69c22f7712Suwe 70c22f7712Suwe 71c22f7712Suwe /** 72c22f7712Suwe * Channel Control Register bits. 73c22f7712Suwe */ 74c22f7712Suwe 75c22f7712Suwe /* Direct (0) or Indirect (1) mode. */ 76c22f7712Suwe #define SH3_DMAC_CHCR_DI 0x00100000 77c22f7712Suwe 78c22f7712Suwe /* Source address reload. 79c22f7712Suwe Only valid for channel 2. */ 80c22f7712Suwe #define SH3_DMAC_CHCR_RO 0x00080000 81c22f7712Suwe 82c22f7712Suwe /* Request check level (0 - low, 1 - high). 83c22f7712Suwe Only valid for channels 0 and 1. */ 84c22f7712Suwe #define SH3_DMAC_CHCR_RL 0x00040000 85c22f7712Suwe 86c22f7712Suwe /* Acknowledge mode (0 - read, 1 - write). 87c22f7712Suwe Only valid for channels 0 and 1. */ 88c22f7712Suwe #define SH3_DMAC_CHCR_AM 0x00020000 89c22f7712Suwe 90c22f7712Suwe /* Acknowledge level (0 - low, 1 - high). 91c22f7712Suwe Only valid for channels 0 and 1. */ 92c22f7712Suwe #define SH3_DMAC_CHCR_AL 0x00010000 93c22f7712Suwe 94c22f7712Suwe /* Destination address mode. */ 95c22f7712Suwe #define SH3_DMAC_CHCR_DM_MASK 0x0000c000 96c22f7712Suwe #define SH3_DMAC_CHCR_DM_FIXED 0x00000000 97c22f7712Suwe #define SH3_DMAC_CHCR_DM_INC 0x00004000 98c22f7712Suwe #define SH3_DMAC_CHCR_DM_DEC 0x00008000 99c22f7712Suwe 100c22f7712Suwe /* Source address mode. */ 101c22f7712Suwe #define SH3_DMAC_CHCR_SM_MASK 0x00003000 102c22f7712Suwe #define SH3_DMAC_CHCR_SM_FIXED 0x00000000 103c22f7712Suwe #define SH3_DMAC_CHCR_SM_INC 0x00001000 104c22f7712Suwe #define SH3_DMAC_CHCR_SM_DEC 0x00002000 105c22f7712Suwe 106c22f7712Suwe /* Resource select */ 107c22f7712Suwe #define SH3_DMAC_CHCR_RS_MASK 0x00000f00 108c22f7712Suwe #define SH3_DMAC_CHCR_RS_EXT_DUAL 0x00000000 109c22f7712Suwe #define SH3_DMAC_CHCR_RS_EXT_OUT 0x00000200 110c22f7712Suwe #define SH3_DMAC_CHCR_RS_EXT_IN 0x00000300 111c22f7712Suwe #define SH3_DMAC_CHCR_RS_AUTO 0x00000400 112c22f7712Suwe #define SH3_DMAC_CHCR_RS_IRDA_TX 0x00000a00 113c22f7712Suwe #define SH3_DMAC_CHCR_RS_IRDA_RX 0x00000b00 114c22f7712Suwe #define SH3_DMAC_CHCR_RS_SCIF_TX 0x00000c00 115c22f7712Suwe #define SH3_DMAC_CHCR_RS_SCIF_RX 0x00000d00 116c22f7712Suwe #define SH3_DMAC_CHCR_RS_ADC 0x00000e00 117c22f7712Suwe #define SH3_DMAC_CHCR_RS_CMT 0x00000f00 118c22f7712Suwe 119c22f7712Suwe /* ~DREQ select (0 - low, 1 - high). 120c22f7712Suwe Only valid for channels 0 and 1. */ 121c22f7712Suwe #define SH3_DMAC_CHCR_DS 0x00000040 122c22f7712Suwe 123c22f7712Suwe /* Transmit mode (0 - cycle steal, 1 - burst). */ 124c22f7712Suwe #define SH3_DMAC_CHCR_TM 0x00000020 125c22f7712Suwe 126c22f7712Suwe /* Transmit size */ 127c22f7712Suwe #define SH3_DMAC_CHCR_TS_MASK 0x00000018 128c22f7712Suwe #define SH3_DMAC_CHCR_TS_1 0x00000000 129c22f7712Suwe #define SH3_DMAC_CHCR_TS_2 0x00000008 130c22f7712Suwe #define SH3_DMAC_CHCR_TS_4 0x00000010 131c22f7712Suwe #define SH3_DMAC_CHCR_TS_16 0x00000018 132c22f7712Suwe 133c22f7712Suwe /* Interrupt enable. */ 134c22f7712Suwe #define SH3_DMAC_CHCR_IE 0x00000004 135c22f7712Suwe 136c22f7712Suwe /* Transfer end. */ 137c22f7712Suwe #define SH3_DMAC_CHCR_TE 0x00000002 138c22f7712Suwe 139c22f7712Suwe /* DMAC enable. */ 140c22f7712Suwe #define SH3_DMAC_CHCR_DE 0x00000001 141c22f7712Suwe 142c22f7712Suwe #define SH3_DMAC_CHCR_BITS "\177\20" \ 143c22f7712Suwe "b\24DI\0" "b\23RO\0" "b\22RL\0" "b\21AM\0" "b\20AL\0" \ 144c22f7712Suwe "f\16\2DM\0" ":\0(FIXED)\0" ":\1(INC)\0" ":\2(DEC)\0" \ 145c22f7712Suwe "f\14\2SM\0" ":\0(FIXED)\0" ":\1(INC)\0" ":\2(DEC)\0" \ 146c22f7712Suwe "f\10\4RS\0" ":\0(EXT_DUAL)\0" ":\2(EXT_OUT)\0" ":\3(EXT_IN)\0" \ 147c22f7712Suwe ":\4(AUTO)\0" \ 148c22f7712Suwe ":\12(IRTX)\0" ":\13(IRRX)\0" ":\14(SCTX)\0" \ 149c22f7712Suwe ":\15(SCRX)\0" ":\16(ADC)\0" ":\17(CMT)\0" \ 150c22f7712Suwe "b\6DS\0" "b\5TM\0" \ 151c22f7712Suwe "f\3\2TS\0" ":\0(1)\0" ":\1(2)\0" ":\2(4)\0" ":\3(16)\0" \ 152c22f7712Suwe "b\2IE\0" "b\1TE\0" "b\0DE\0" 153c22f7712Suwe 154c22f7712Suwe 155c22f7712Suwe /** 156c22f7712Suwe * DMA Operation Register bits 157c22f7712Suwe */ 158c22f7712Suwe 159c22f7712Suwe /* Priority mode. */ 160c22f7712Suwe #define SH3_DMAC_DMAOR_PR_MASK 0x0300 161c22f7712Suwe #define SH3_DMAC_DMAOR_PR_0123 0x0000 /* 0 > 1 > 2 > 3 */ 162c22f7712Suwe #define SH3_DMAC_DMAOR_PR_0231 0x0100 /* 0 > 2 > 3 > 1 */ 163c22f7712Suwe #define SH3_DMAC_DMAOR_PR_2013 0x0200 /* 2 > 0 > 1 > 3 */ 164c22f7712Suwe #define SH3_DMAC_DMAOR_PR_RR 0x0300 /* round robbin */ 165c22f7712Suwe 166c22f7712Suwe /* Address error flag. */ 167c22f7712Suwe #define SH3_DMAC_DMAOR_AE 0x0004 168c22f7712Suwe 169c22f7712Suwe /* NMI flag. */ 170c22f7712Suwe #define SH3_DMAC_DMAOR_NMIF 0x0002 171c22f7712Suwe 172c22f7712Suwe /* DMA master enable. */ 173c22f7712Suwe #define SH3_DMAC_DMAOR_DME 0x0001 174c22f7712Suwe 175c22f7712Suwe #define SH3_DMAC_DMAOR_BITS "\177\20" \ 176c22f7712Suwe "f\10\2PR\0" ":\0(0123)\0" ":\1(0231)\0" ":\2(2013)\0" ":\3(RR)\0" \ 177c22f7712Suwe "b\2AE\0" "b\1NMIF\0" "b\0DME\0" 178c22f7712Suwe 179c22f7712Suwe 180c22f7712Suwe /** 181c22f7712Suwe * Compare Match Timer. 182c22f7712Suwe */ 183c22f7712Suwe 184c22f7712Suwe /* Start the CMT. */ 185c22f7712Suwe #define SH3_DMAC_CMT_CMSTR_STR 0x0001 186c22f7712Suwe 187c22f7712Suwe /* Compare Match Flag. */ 188c22f7712Suwe #define SH3_DMAC_CMT_CMCSR_CMF 0x0080 189c22f7712Suwe 190c22f7712Suwe /* Clock select (PCLOCK/x). */ 191c22f7712Suwe #define SH3_DMAC_CMT_CMCSR_CKS_MASK 0x0003 192c22f7712Suwe #define SH3_DMAC_CMT_CMCSR_CKS_4 0x0000 193c22f7712Suwe #define SH3_DMAC_CMT_CMCSR_CKS_8 0x0001 194c22f7712Suwe #define SH3_DMAC_CMT_CMCSR_CKS_16 0x0002 195c22f7712Suwe #define SH3_DMAC_CMT_CMCSR_CKS_64 0x0003 196c22f7712Suwe 197c22f7712Suwe #define SH3_DMAC_CMT_CMCSR_BITS "\177\20" \ 198c22f7712Suwe "b\7CMF\0" \ 199c22f7712Suwe "f\0\2CKS\0" ":\0(1/4)\0" ":\1(1/8)\0" ":\2(1/16)\0" ":\3(1/64)\0" 200c22f7712Suwe 201c22f7712Suwe #endif /* _SH3_DMACREG_H_ */ 202