1*95e1ffb1Schristos /* $NetBSD: dacreg.h,v 1.2 2005/12/11 12:18:58 christos Exp $ */ 281468eceSuwe 381468eceSuwe /* 481468eceSuwe * Copyright (c) 2003 Valeriy E. Ushakov 581468eceSuwe * All rights reserved. 681468eceSuwe * 781468eceSuwe * Redistribution and use in source and binary forms, with or without 881468eceSuwe * modification, are permitted provided that the following conditions 981468eceSuwe * are met: 1081468eceSuwe * 1. Redistributions of source code must retain the above copyright 1181468eceSuwe * notice, this list of conditions and the following disclaimer. 1281468eceSuwe * 2. Redistributions in binary form must reproduce the above copyright 1381468eceSuwe * notice, this list of conditions and the following disclaimer in the 1481468eceSuwe * documentation and/or other materials provided with the distribution. 1581468eceSuwe * 3. The name of the author may not be used to endorse or promote products 1681468eceSuwe * derived from this software without specific prior written permission 1781468eceSuwe * 1881468eceSuwe * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1981468eceSuwe * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2081468eceSuwe * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2181468eceSuwe * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2281468eceSuwe * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2381468eceSuwe * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2481468eceSuwe * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2581468eceSuwe * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2681468eceSuwe * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2781468eceSuwe * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2881468eceSuwe */ 2981468eceSuwe 3081468eceSuwe #ifndef _SH3_DACREG_H_ 3181468eceSuwe #define _SH3_DACREG_H_ 3281468eceSuwe 3381468eceSuwe /* D/A data registers for channels 0 and 1 */ 3481468eceSuwe #define SH7709_DADR0 0xa40000a0 3581468eceSuwe #define SH7709_DADR1 0xa40000a2 3681468eceSuwe 3781468eceSuwe /* D/A control register */ 3881468eceSuwe #define SH7709_DACR 0xa40000a4 3981468eceSuwe 4081468eceSuwe #define SH7709_DACR_DAOE1 0x80 /* output enable for channel 1 */ 4181468eceSuwe #define SH7709_DACR_DAOE0 0x40 /* output enable for channel 0 */ 4281468eceSuwe #define SH7709_DACR_DAE 0x20 /* D/A enable */ 4381468eceSuwe 4481468eceSuwe #define SH7709_DACR_BITS \ 4581468eceSuwe "\177\020" "b\07DAOE1\0" "b\06DAOE0\0" "b\05DAE\0" 4681468eceSuwe 4781468eceSuwe #endif /* _SH3_DACREG_H_ */ 48