1*b610ccb0Srumble /* $NetBSD: oiocreg.h,v 1.1 2009/02/10 06:04:56 rumble Exp $ */ 2*b610ccb0Srumble 3*b610ccb0Srumble /* 4*b610ccb0Srumble * Copyright (c) 2009 Stephen M. Rumble 5*b610ccb0Srumble * All rights reserved. 6*b610ccb0Srumble * 7*b610ccb0Srumble * Redistribution and use in source and binary forms, with or without 8*b610ccb0Srumble * modification, are permitted provided that the following conditions 9*b610ccb0Srumble * are met: 10*b610ccb0Srumble * 1. Redistributions of source code must retain the above copyright 11*b610ccb0Srumble * notice, this list of conditions and the following disclaimer. 12*b610ccb0Srumble * 2. The name of the author may not be used to endorse or promote products 13*b610ccb0Srumble * derived from this software without specific prior written permission. 14*b610ccb0Srumble * 15*b610ccb0Srumble * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16*b610ccb0Srumble * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17*b610ccb0Srumble * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18*b610ccb0Srumble * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19*b610ccb0Srumble * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20*b610ccb0Srumble * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21*b610ccb0Srumble * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22*b610ccb0Srumble * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23*b610ccb0Srumble * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24*b610ccb0Srumble * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25*b610ccb0Srumble */ 26*b610ccb0Srumble 27*b610ccb0Srumble #ifndef _ARCH_SGIMIPS_DEV_OIOCREG_H_ 28*b610ccb0Srumble #define _ARCH_SGIMIPS_DEV_OIOCREG_H_ 29*b610ccb0Srumble 30*b610ccb0Srumble /* Registers below are relative to: */ 31*b610ccb0Srumble #define OIOC_BASE_ADDRESS 0x1f900000 32*b610ccb0Srumble 33*b610ccb0Srumble /* 34*b610ccb0Srumble * The IOC SCSI DMA engine consists of 257 16-bit address registers, which can 35*b610ccb0Srumble * point to 256 4096-byte buffers. 36*b610ccb0Srumble * 37*b610ccb0Srumble * IOC_SCSI_DMA_LOW contains the first 12 bits of a starting offset within 38*b610ccb0Srumble * the first page of a virtually contiguous buffer. The MSB indicates DMA 39*b610ccb0Srumble * transfer direction. 40*b610ccb0Srumble * 41*b610ccb0Srumble * There are 256 high address registers starting at IOC_SCSI_DMA_HIGH_BASE 42*b610ccb0Srumble * and occurring every 4 bytes. This provides 28 address bits - more than 43*b610ccb0Srumble * sufficient for these old machines. 44*b610ccb0Srumble */ 45*b610ccb0Srumble #define OIOC_SCSI_REGS 0x00000000 /* SCSI registers offset */ 46*b610ccb0Srumble #define OIOC_SCSI_REGS_SIZE 0x00200102 /* SCSI length */ 47*b610ccb0Srumble 48*b610ccb0Srumble #define OIOC_SCSI_DMA_LOW 0x00000002 /* 16-bit */ 49*b610ccb0Srumble #define OIOC_SCSI_DMA_HIGH_BASE 0x00020002 /* 16-bit */ 50*b610ccb0Srumble #define OIOC_SCSI_DMA_FLUSH 0x00040000 /* 32-bit; write 0 to flush */ 51*b610ccb0Srumble 52*b610ccb0Srumble #define OIOC_SCSI_DMA_NSEGS 256 53*b610ccb0Srumble #define OIOC_SCSI_DMA_HIGH(_x) (OIOC_SCSI_DMA_HIGH_BASE + ((_x) << 2)) 54*b610ccb0Srumble #define OIOC_SCSI_DMA_HIGH_SHFT 12 55*b610ccb0Srumble #define OIOC_SCSI_DMA_LOW_ADDR_MASK 0x0fff 56*b610ccb0Srumble #define OIOC_SCSI_DMA_LOW_ADDR_DMADIR 0x8000 /* if set: SCSI->MEM */ 57*b610ccb0Srumble 58*b610ccb0Srumble #define OIOC_SCSI_RESET_OFF 0x00180000 /* 32-bit; read to set _RESET */ 59*b610ccb0Srumble #define OIOC_SCSI_RESET_ON 0x00180004 /* 32-bit; read to clr _RESET */ 60*b610ccb0Srumble 61*b610ccb0Srumble #define OIOC_WD33C93_ASR 0x00200001 /* 8-bit; scsi asr register */ 62*b610ccb0Srumble #define OIOC_WD33C93_ASR_SIZE 1 63*b610ccb0Srumble #define OIOC_WD33C93_DATA 0x00200101 /* 8-bit; scsi data register */ 64*b610ccb0Srumble #define OIOC_WD33C93_DATA_SIZE 1 65*b610ccb0Srumble 66*b610ccb0Srumble /* 67*b610ccb0Srumble * IOC has 64 (I think) 16-bit page remap registers occurring every 4 bytes 68*b610ccb0Srumble * starting at 0xbf920802. Each register takes a physical page number, N, which 69*b610ccb0Srumble * maps physical memory page N into LANCE's 24-bit address space at offset 70*b610ccb0Srumble * (N * 4096). 71*b610ccb0Srumble */ 72*b610ccb0Srumble #define OIOC_ENET_PGMAP_BASE 0x00020802 /* 16-bit */ 73*b610ccb0Srumble #define OIOC_ENET_NPGMAPS 64 /* 64 pages */ 74*b610ccb0Srumble #define OIOC_ENET_PGMAP_SIZE (OIOC_ENET_NPGMAPS * 4) 75*b610ccb0Srumble #define OIOC_ENET_PGMAP_OFF(n) ((n) << 2) /* every 4 bytes */ 76*b610ccb0Srumble 77*b610ccb0Srumble #define OIOC_ENET_RESET_OFF 0x00060000 /* 8-bit; read to set _RESET */ 78*b610ccb0Srumble #define OIOC_ENET_RESET_ON 0x00060004 /* 8-bit; read to clr _RESET */ 79*b610ccb0Srumble #define OIOC_LANCE_RDP 0x00050000 /* 16-bit; le reg. data port */ 80*b610ccb0Srumble #define OIOC_LANCE_RDP_SIZE 2 81*b610ccb0Srumble #define OIOC_LANCE_RAP 0x00050100 /* 16-bit; le reg. access port*/ 82*b610ccb0Srumble #define OIOC_LANCE_RAP_SIZE 2 83*b610ccb0Srumble 84*b610ccb0Srumble #define OIOC2_CONFIG 0x00180008 /* 32-bit; IOC2 (IP6/10) only */ 85*b610ccb0Srumble 86*b610ccb0Srumble /* OIOC2_CONFIG bits; only BURST, NOSYNC and HIWAT are writable. */ 87*b610ccb0Srumble #define OIOC2_CONFIG_HIWAT_MASK 0x0000000f 88*b610ccb0Srumble #define OIOC2_CONFIG_HIWAT_SHFT 0x00000000 89*b610ccb0Srumble #define OIOC2_CONFIG_ID_MASK 0x00000030 90*b610ccb0Srumble #define OIOC2_CONFIG_ID_SHFT 0x00000004 91*b610ccb0Srumble #define OIOC2_CONFIG_NOSYNC_MASK 0x00000040 92*b610ccb0Srumble #define OIOC2_CONFIG_NOSYNC_SHFT 0x00000006 93*b610ccb0Srumble #define OIOC2_CONFIG_BURST_MASK 0x00000080 94*b610ccb0Srumble #define OIOC2_CONFIG_BURST_SHFT 0x00000007 95*b610ccb0Srumble #define OIOC2_CONFIG_COUNT_MASK 0x00007f00 96*b610ccb0Srumble #define OIOC2_CONFIG_COUNT_SHFT 0x00000008 97*b610ccb0Srumble #define OIOC2_CONFIG_RSRVD_MASK 0x00008000 98*b610ccb0Srumble #define OIOC2_CONFIG_RSRVD_SHFT 0x0000000f 99*b610ccb0Srumble #define OIOC2_CONFIG_SCP_MASK 0x003f0000 100*b610ccb0Srumble #define OIOC2_CONFIG_SCP_SHFT 0x00000010 101*b610ccb0Srumble #define OIOC2_CONFIG_RSRVD2_MASK 0x0fc00000 102*b610ccb0Srumble #define OIOC2_CONFIG_RSRVD2_SHFT 0x00000016 103*b610ccb0Srumble #define OIOC2_CONFIG_IOP_MASK 0xf0000000 104*b610ccb0Srumble #define OIOC2_CONFIG_IOP_SHFT 0x0000001c 105*b610ccb0Srumble 106*b610ccb0Srumble #endif /* _ARCH_SGIMIPS_DEV_OIOCREG_H_ */ 107