xref: /netbsd-src/sys/arch/rs6000/include/iocc.h (revision ce099b40997c43048fb78bd578195f81d2456523)
1*ce099b40Smartin /*	$NetBSD: iocc.h,v 1.2 2008/04/28 20:23:34 martin Exp $	*/
268fe5b6fSgarbled 
368fe5b6fSgarbled /*-
468fe5b6fSgarbled  * Copyright (c) 2007 The NetBSD Foundation, Inc.
568fe5b6fSgarbled  * All rights reserved.
668fe5b6fSgarbled  *
768fe5b6fSgarbled  * This code is derived from software contributed to The NetBSD Foundation
868fe5b6fSgarbled  * by Tim Rightnour
968fe5b6fSgarbled  *
1068fe5b6fSgarbled  * Redistribution and use in source and binary forms, with or without
1168fe5b6fSgarbled  * modification, are permitted provided that the following conditions
1268fe5b6fSgarbled  * are met:
1368fe5b6fSgarbled  * 1. Redistributions of source code must retain the above copyright
1468fe5b6fSgarbled  *    notice, this list of conditions and the following disclaimer.
1568fe5b6fSgarbled  * 2. Redistributions in binary form must reproduce the above copyright
1668fe5b6fSgarbled  *    notice, this list of conditions and the following disclaimer in the
1768fe5b6fSgarbled  *    documentation and/or other materials provided with the distribution.
1868fe5b6fSgarbled  *
1968fe5b6fSgarbled  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
2068fe5b6fSgarbled  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
2168fe5b6fSgarbled  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
2268fe5b6fSgarbled  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
2368fe5b6fSgarbled  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2468fe5b6fSgarbled  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2568fe5b6fSgarbled  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2668fe5b6fSgarbled  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2768fe5b6fSgarbled  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2868fe5b6fSgarbled  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2968fe5b6fSgarbled  * POSSIBILITY OF SUCH DAMAGE.
3068fe5b6fSgarbled  */
3168fe5b6fSgarbled 
3268fe5b6fSgarbled #ifndef _RS6000_IOCC_H_
3368fe5b6fSgarbled #define _RS6000_IOCC_H_
3468fe5b6fSgarbled 
3568fe5b6fSgarbled /*
3668fe5b6fSgarbled  * Ports and defines used for control of the IOCC
3768fe5b6fSgarbled  */
3868fe5b6fSgarbled 
3968fe5b6fSgarbled /* MCA register addresses for PPC */
4068fe5b6fSgarbled 
4168fe5b6fSgarbled #define	IOCC_BASE_PPC		0x10000
4268fe5b6fSgarbled #define IOCC_POSBASE_PPC	0x400000
4368fe5b6fSgarbled 
4468fe5b6fSgarbled #define IOCC_BASE		IOCC_BASE_PPC
4568fe5b6fSgarbled #define IOCC_POSBASE		IOCC_POSBASE_PPC
4668fe5b6fSgarbled 
4768fe5b6fSgarbled #define IOCC_CFG_REG		(IOCC_BASE + 0x80)	/* config reg */
4868fe5b6fSgarbled #define IOCC_PERS		(IOCC_BASE + 0x88)	/* personalization */
4968fe5b6fSgarbled #define IOCC_TCE_ADDR_HIGH	(IOCC_BASE + 0x98)	/* MSW of tceaddr */
5068fe5b6fSgarbled #define IOCC_TCE_ADDR_LOW	(IOCC_BASE + 0x9C)	/* LSW of tceaddr */
5168fe5b6fSgarbled #define IOCC_CRESET		(IOCC_BASE + 0xA0)	/* comp reset reg */
5268fe5b6fSgarbled #define IOCC_BUS_MAP		(IOCC_BASE + 0xA8)	/* bus mapping reg */
5368fe5b6fSgarbled #define IOCC_IEE		(IOCC_BASE + 0x180) /* intr enable */
5468fe5b6fSgarbled #define IOCC_IRR		(IOCC_BASE + 0x188) /* intr request reg */
5568fe5b6fSgarbled #define IOCC_MIR		(IOCC_BASE + 0x190) /* misc intr reg */
5668fe5b6fSgarbled #define IOCC_CPU_AVAIL(proc) \
5768fe5b6fSgarbled 	(IOCC_BASE + 0x1C0 + (proc * 4))		/* available procs */
5868fe5b6fSgarbled #define IOCC_XIVR(intr) \
5968fe5b6fSgarbled 	(IOCC_BASE + 0x200 + (intr * 4))		/* extr intr vector */
6068fe5b6fSgarbled #define IOCC_DMA_SLAVE_CTRL(slave) \
6168fe5b6fSgarbled 	(IOCC_BASE + 0x380 + (slave * 4))		/* slave control regs */
6268fe5b6fSgarbled #define IOCC_CHAN_STAT(chan) \
6368fe5b6fSgarbled 	(IOCC_BASE + 0x400 + (chan * 4))		/* channel stat regs */
6468fe5b6fSgarbled #define IOCC_EOI(intr) \
6568fe5b6fSgarbled 	(IOCC_BASE + 0x480 + (intr * 4))		/* ext intr vec */
6668fe5b6fSgarbled #define IOCC_ARBLEVEL(chan) \
6768fe5b6fSgarbled 	(IOCC_BASE + 0x500 + (chan * 4))	/* chan arb level en/disable */
6868fe5b6fSgarbled 
6968fe5b6fSgarbled #define MAX_IOCC		2
7068fe5b6fSgarbled 
7168fe5b6fSgarbled #endif /* _RS6000_IOCC_H_ */
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