xref: /netbsd-src/sys/arch/riscv/include/pci_machdep.h (revision 05276bf3c24743a2bb3b218fc21708914b5da491)
1*05276bf3Sskrll /*	$NetBSD: pci_machdep.h,v 1.1 2025/01/01 17:53:08 skrll Exp $	*/
2*05276bf3Sskrll 
3*05276bf3Sskrll /*-
4*05276bf3Sskrll  * Copyright (c) 2023 The NetBSD Foundation, Inc.
5*05276bf3Sskrll  * All rights reserved.
6*05276bf3Sskrll  *
7*05276bf3Sskrll  * This code is derived from software contributed to The NetBSD Foundation
8*05276bf3Sskrll  * by Nick Hudson
9*05276bf3Sskrll  *
10*05276bf3Sskrll  * Redistribution and use in source and binary forms, with or without
11*05276bf3Sskrll  * modification, are permitted provided that the following conditions
12*05276bf3Sskrll  * are met:
13*05276bf3Sskrll  * 1. Redistributions of source code must retain the above copyright
14*05276bf3Sskrll  *    notice, this list of conditions and the following disclaimer.
15*05276bf3Sskrll  * 2. Redistributions in binary form must reproduce the above copyright
16*05276bf3Sskrll  *    notice, this list of conditions and the following disclaimer in the
17*05276bf3Sskrll  *    documentation and/or other materials provided with the distribution.
18*05276bf3Sskrll  *
19*05276bf3Sskrll  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20*05276bf3Sskrll  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21*05276bf3Sskrll  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22*05276bf3Sskrll  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23*05276bf3Sskrll  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*05276bf3Sskrll  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*05276bf3Sskrll  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*05276bf3Sskrll  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*05276bf3Sskrll  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*05276bf3Sskrll  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*05276bf3Sskrll  * POSSIBILITY OF SUCH DAMAGE.
30*05276bf3Sskrll  */
31*05276bf3Sskrll 
32*05276bf3Sskrll /*
33*05276bf3Sskrll  * Copyright (c) 1996 Carnegie-Mellon University.
34*05276bf3Sskrll  * All rights reserved.
35*05276bf3Sskrll  *
36*05276bf3Sskrll  * Author: Chris G. Demetriou
37*05276bf3Sskrll  *
38*05276bf3Sskrll  * Permission to use, copy, modify and distribute this software and
39*05276bf3Sskrll  * its documentation is hereby granted, provided that both the copyright
40*05276bf3Sskrll  * notice and this permission notice appear in all copies of the
41*05276bf3Sskrll  * software, derivative works or modified versions, and any portions
42*05276bf3Sskrll  * thereof, and that both notices appear in supporting documentation.
43*05276bf3Sskrll  *
44*05276bf3Sskrll  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
45*05276bf3Sskrll  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
46*05276bf3Sskrll  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
47*05276bf3Sskrll  *
48*05276bf3Sskrll  * Carnegie Mellon requests users of this software to return to
49*05276bf3Sskrll  *
50*05276bf3Sskrll  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
51*05276bf3Sskrll  *  School of Computer Science
52*05276bf3Sskrll  *  Carnegie Mellon University
53*05276bf3Sskrll  *  Pittsburgh PA 15213-3890
54*05276bf3Sskrll  *
55*05276bf3Sskrll  * any improvements or extensions that they make and grant Carnegie the
56*05276bf3Sskrll  * rights to redistribute these changes.
57*05276bf3Sskrll  */
58*05276bf3Sskrll 
59*05276bf3Sskrll #ifndef _RISCV_PCI_MACHDEP_H_
60*05276bf3Sskrll #define _RISCV_PCI_MACHDEP_H_
61*05276bf3Sskrll 
62*05276bf3Sskrll /*
63*05276bf3Sskrll  * Machine-specific definitions for PCI autoconfiguration.
64*05276bf3Sskrll  */
65*05276bf3Sskrll 
66*05276bf3Sskrll #define __HAVE_PCI_GET_SEGMENT
67*05276bf3Sskrll 
68*05276bf3Sskrll #ifdef _LP64
69*05276bf3Sskrll #define _PCI_HAVE_DMA64
70*05276bf3Sskrll #endif
71*05276bf3Sskrll 
72*05276bf3Sskrll #include <sys/errno.h>
73*05276bf3Sskrll 
74*05276bf3Sskrll /*
75*05276bf3Sskrll  * Types provided to machine-independent PCI code
76*05276bf3Sskrll  */
77*05276bf3Sskrll typedef struct riscv_pci_chipset *pci_chipset_tag_t;
78*05276bf3Sskrll typedef u_long pcitag_t;
79*05276bf3Sskrll typedef uint64_t pci_intr_handle_t;
80*05276bf3Sskrll 
81*05276bf3Sskrll /*
82*05276bf3Sskrll  * pci_intr_handle_t fields
83*05276bf3Sskrll  */
84*05276bf3Sskrll #define	RISCV_PCI_INTR_MSI_VEC	__BITS(42, 32)
85*05276bf3Sskrll #define	RISCV_PCI_INTR_MPSAFE	__BIT(31)
86*05276bf3Sskrll #define	RISCV_PCI_INTR_MSIX	__BIT(30)
87*05276bf3Sskrll #define	RISCV_PCI_INTR_MSI	__BIT(29)
88*05276bf3Sskrll #define	RISCV_PCI_INTR_FRAME	__BITS(23, 16)
89*05276bf3Sskrll #define	RISCV_PCI_INTR_IRQ	__BITS(15,  0)
90*05276bf3Sskrll 
91*05276bf3Sskrll #ifdef __HAVE_PCI_MSI_MSIX
92*05276bf3Sskrll /*
93*05276bf3Sskrll  * PCI MSI/MSI-X support
94*05276bf3Sskrll  */
95*05276bf3Sskrll typedef enum {
96*05276bf3Sskrll 	PCI_INTR_TYPE_INTX = 0,
97*05276bf3Sskrll 	PCI_INTR_TYPE_MSI,
98*05276bf3Sskrll 	PCI_INTR_TYPE_MSIX,
99*05276bf3Sskrll 	PCI_INTR_TYPE_SIZE,
100*05276bf3Sskrll } pci_intr_type_t;
101*05276bf3Sskrll #endif /* __HAVE_PCI_MSI_MSIX */
102*05276bf3Sskrll 
103*05276bf3Sskrll /*
104*05276bf3Sskrll  * Forward declarations.
105*05276bf3Sskrll  */
106*05276bf3Sskrll struct pci_attach_args;
107*05276bf3Sskrll 
108*05276bf3Sskrll /*
109*05276bf3Sskrll  * riscv-specific PCI structure and type definitions.
110*05276bf3Sskrll  * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
111*05276bf3Sskrll  */
112*05276bf3Sskrll struct riscv_pci_chipset {
113*05276bf3Sskrll 	void		*pc_conf_v;
114*05276bf3Sskrll 	void		(*pc_attach_hook)(device_t, device_t,
115*05276bf3Sskrll 			    struct pcibus_attach_args *);
116*05276bf3Sskrll 	int		(*pc_bus_maxdevs)(void *, int);
117*05276bf3Sskrll 	pcitag_t	(*pc_make_tag)(void *, int, int, int);
118*05276bf3Sskrll 	void		(*pc_decompose_tag)(void *, pcitag_t, int *,
119*05276bf3Sskrll 			    int *, int *);
120*05276bf3Sskrll 	u_int		(*pc_get_segment)(void *);
121*05276bf3Sskrll #if 0
122*05276bf3Sskrll 	// XXXNH devid?
123*05276bf3Sskrll 	uint32_t	(*pc_get_devid)(void *, uint32_t);
124*05276bf3Sskrll #endif
125*05276bf3Sskrll 	uint32_t	(*pc_get_frameid)(void *, uint32_t);
126*05276bf3Sskrll 	pcireg_t	(*pc_conf_read)(void *, pcitag_t, int);
127*05276bf3Sskrll 	void		(*pc_conf_write)(void *, pcitag_t, int, pcireg_t);
128*05276bf3Sskrll 
129*05276bf3Sskrll 	void		*pc_intr_v;
130*05276bf3Sskrll 	int		(*pc_intr_map)(const struct pci_attach_args *,
131*05276bf3Sskrll 			    pci_intr_handle_t *);
132*05276bf3Sskrll 	const char	*(*pc_intr_string)(void *, pci_intr_handle_t,
133*05276bf3Sskrll 			    char *, size_t);
134*05276bf3Sskrll 	const struct evcnt *(*pc_intr_evcnt)(void *, pci_intr_handle_t);
135*05276bf3Sskrll 	int		(*pc_intr_setattr)(void *, pci_intr_handle_t *,
136*05276bf3Sskrll 			    int, uint64_t);
137*05276bf3Sskrll 	void		*(*pc_intr_establish)(void *, pci_intr_handle_t,
138*05276bf3Sskrll 			    int, int (*)(void *), void *, const char *);
139*05276bf3Sskrll 	void		(*pc_intr_disestablish)(void *, void *);
140*05276bf3Sskrll 
141*05276bf3Sskrll #ifdef __HAVE_PCI_CONF_HOOK
142*05276bf3Sskrll 	int		(*pc_conf_hook)(void *, int, int, int, pcireg_t);
143*05276bf3Sskrll #endif
144*05276bf3Sskrll 	void		(*pc_conf_interrupt)(void *, int, int, int, int, int *);
145*05276bf3Sskrll 
146*05276bf3Sskrll #ifdef __HAVE_PCI_MSI_MSIX
147*05276bf3Sskrll 	void		*pc_msi_v;
148*05276bf3Sskrll 	pci_intr_type_t	(*pc_intr_type)(void *, pci_intr_handle_t);
149*05276bf3Sskrll 	int		(*pc_intr_alloc)(const struct pci_attach_args *,
150*05276bf3Sskrll 			    pci_intr_handle_t **, int *, pci_intr_type_t);
151*05276bf3Sskrll 	void		(*pc_intr_release)(void *, pci_intr_handle_t *, int);
152*05276bf3Sskrll 	int		(*pc_intx_alloc)(const struct pci_attach_args *,
153*05276bf3Sskrll 			    pci_intr_handle_t **);
154*05276bf3Sskrll 	int		(*pc_msi_alloc)(const struct pci_attach_args *,
155*05276bf3Sskrll 			    pci_intr_handle_t **, int *);
156*05276bf3Sskrll 	int		(*pc_msi_alloc_exact)(const struct pci_attach_args *,
157*05276bf3Sskrll 			    pci_intr_handle_t **, int);
158*05276bf3Sskrll 	int		(*pc_msix_alloc)(const struct pci_attach_args *,
159*05276bf3Sskrll 			    pci_intr_handle_t **, int *);
160*05276bf3Sskrll 	int		(*pc_msix_alloc_exact)(const struct pci_attach_args *,
161*05276bf3Sskrll 			    pci_intr_handle_t **, int);
162*05276bf3Sskrll 	int		(*pc_msix_alloc_map)(const struct pci_attach_args *,
163*05276bf3Sskrll 			    pci_intr_handle_t **, u_int *, int);
164*05276bf3Sskrll #endif
165*05276bf3Sskrll 
166*05276bf3Sskrll 	uint32_t	pc_cfg_cmd;
167*05276bf3Sskrll };
168*05276bf3Sskrll 
169*05276bf3Sskrll /*
170*05276bf3Sskrll  * Functions provided to machine-independent PCI code.
171*05276bf3Sskrll  */
172*05276bf3Sskrll //XXXNH static inlines..
173*05276bf3Sskrll #define	pci_attach_hook(p, s, pba)					\
174*05276bf3Sskrll     (*(pba)->pba_pc->pc_attach_hook)((p), (s), (pba))
175*05276bf3Sskrll #define	pci_bus_maxdevs(c, b)						\
176*05276bf3Sskrll     (*(c)->pc_bus_maxdevs)((c)->pc_conf_v, (b))
177*05276bf3Sskrll #define	pci_make_tag(c, b, d, f)					\
178*05276bf3Sskrll     (*(c)->pc_make_tag)((c)->pc_conf_v, (b), (d), (f))
179*05276bf3Sskrll #define	pci_decompose_tag(c, t, bp, dp, fp)				\
180*05276bf3Sskrll     (*(c)->pc_decompose_tag)((c)->pc_conf_v, (t), (bp), (dp), (fp))
181*05276bf3Sskrll #define pci_get_segment(c)						\
182*05276bf3Sskrll     ((c)->pc_get_segment ? (*(c)->pc_get_segment)((c)->pc_conf_v) : 0)
183*05276bf3Sskrll #define pci_get_devid(c, d)						\
184*05276bf3Sskrll     ((c)->pc_get_devid ? (*(c)->pc_get_devid)((c)->pc_conf_v, (d)) : (d))
185*05276bf3Sskrll #define pci_get_frameid(c, d)						\
186*05276bf3Sskrll     ((c)->pc_get_frameid ? (*(c)->pc_get_frameid)((c)->pc_conf_v, (d)) : 0)
187*05276bf3Sskrll #define	pci_conf_read(c, t, r)						\
188*05276bf3Sskrll     (*(c)->pc_conf_read)((c)->pc_conf_v, (t), (r))
189*05276bf3Sskrll #define	pci_conf_write(c, t, r, v)					\
190*05276bf3Sskrll     (*(c)->pc_conf_write)((c)->pc_conf_v, (t), (r), (v))
191*05276bf3Sskrll #define	pci_intr_map(pa, ihp)						\
192*05276bf3Sskrll     (*(pa)->pa_pc->pc_intr_map)((pa), (ihp))
193*05276bf3Sskrll #define	pci_intr_string(c, ih, buf, len)				\
194*05276bf3Sskrll     (*(c)->pc_intr_string)((c)->pc_intr_v, (ih), (buf), (len))
195*05276bf3Sskrll #define	pci_intr_evcnt(c, ih)						\
196*05276bf3Sskrll     (*(c)->pc_intr_evcnt)((c)->pc_intr_v, (ih))
197*05276bf3Sskrll #define	pci_intr_establish(c, ih, l, h, a)				\
198*05276bf3Sskrll     (*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), (h), (a), NULL)
199*05276bf3Sskrll #define	pci_intr_disestablish(c, iv)					\
200*05276bf3Sskrll     (*(c)->pc_intr_disestablish)((c)->pc_intr_v, (iv))
201*05276bf3Sskrll #ifdef __HAVE_PCI_CONF_HOOK
202*05276bf3Sskrll #define	pci_conf_hook(c, b, d, f, id)					\
203*05276bf3Sskrll     (*(c)->pc_conf_hook)((c)->pc_conf_v, (b), (d), (f), (id))
204*05276bf3Sskrll #endif
205*05276bf3Sskrll #define	pci_conf_interrupt(c, b, d, i, s, p)				\
206*05276bf3Sskrll     (*(c)->pc_conf_interrupt)((c)->pc_conf_v, (b), (d), (i), (s), (p))
207*05276bf3Sskrll 
208*05276bf3Sskrll static inline int
209*05276bf3Sskrll pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ihp,
210*05276bf3Sskrll     int attr, uint64_t data)
211*05276bf3Sskrll {
212*05276bf3Sskrll 	if (!pc->pc_intr_setattr)
213*05276bf3Sskrll 		return ENODEV;
214*05276bf3Sskrll 	return pc->pc_intr_setattr(pc, ihp, attr, data);
215*05276bf3Sskrll }
216*05276bf3Sskrll 
217*05276bf3Sskrll static inline void *
218*05276bf3Sskrll pci_intr_establish_xname(pci_chipset_tag_t pc, pci_intr_handle_t ih,
219*05276bf3Sskrll     int level, int (*fn)(void *), void *arg, const char *xname)
220*05276bf3Sskrll {
221*05276bf3Sskrll 	return pc->pc_intr_establish(pc->pc_intr_v, ih, level, fn, arg, xname);
222*05276bf3Sskrll }
223*05276bf3Sskrll 
224*05276bf3Sskrll #ifdef __HAVE_PCI_MSI_MSIX
225*05276bf3Sskrll pci_intr_type_t
226*05276bf3Sskrll 	pci_intr_type(pci_chipset_tag_t, pci_intr_handle_t);
227*05276bf3Sskrll int	pci_intr_alloc(const struct pci_attach_args *, pci_intr_handle_t **,
228*05276bf3Sskrll 	    int *, pci_intr_type_t);
229*05276bf3Sskrll void	pci_intr_release(pci_chipset_tag_t, pci_intr_handle_t *, int);
230*05276bf3Sskrll int	pci_intx_alloc(const struct pci_attach_args *, pci_intr_handle_t **);
231*05276bf3Sskrll int	pci_msi_alloc(const struct pci_attach_args *, pci_intr_handle_t **,
232*05276bf3Sskrll 	    int *);
233*05276bf3Sskrll int	pci_msi_alloc_exact(const struct pci_attach_args *,
234*05276bf3Sskrll 	    pci_intr_handle_t **, int);
235*05276bf3Sskrll int	pci_msix_alloc(const struct pci_attach_args *, pci_intr_handle_t **,
236*05276bf3Sskrll 	    int *);
237*05276bf3Sskrll int	pci_msix_alloc_exact(const struct pci_attach_args *,
238*05276bf3Sskrll 	    pci_intr_handle_t **, int);
239*05276bf3Sskrll int	pci_msix_alloc_map(const struct pci_attach_args *, pci_intr_handle_t **,
240*05276bf3Sskrll 	    u_int *, int);
241*05276bf3Sskrll #endif	/* __HAVE_PCI_MSI_MSIX */
242*05276bf3Sskrll 
243*05276bf3Sskrll #endif	/* _RISCV_PCI_MACHDEP_H_ */
244