1*05276bf3Sskrll /* $NetBSD: pcihost_fdtvar.h,v 1.1 2025/01/01 17:53:07 skrll Exp $ */ 2*05276bf3Sskrll 3*05276bf3Sskrll /*- 4*05276bf3Sskrll * Copyright (c) 2018 Jared D. McNeill <jmcneill@invisible.ca> 5*05276bf3Sskrll * All rights reserved. 6*05276bf3Sskrll * 7*05276bf3Sskrll * Redistribution and use in source and binary forms, with or without 8*05276bf3Sskrll * modification, are permitted provided that the following conditions 9*05276bf3Sskrll * are met: 10*05276bf3Sskrll * 1. Redistributions of source code must retain the above copyright 11*05276bf3Sskrll * notice, this list of conditions and the following disclaimer. 12*05276bf3Sskrll * 2. Redistributions in binary form must reproduce the above copyright 13*05276bf3Sskrll * notice, this list of conditions and the following disclaimer in the 14*05276bf3Sskrll * documentation and/or other materials provided with the distribution. 15*05276bf3Sskrll * 16*05276bf3Sskrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17*05276bf3Sskrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18*05276bf3Sskrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19*05276bf3Sskrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20*05276bf3Sskrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21*05276bf3Sskrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22*05276bf3Sskrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23*05276bf3Sskrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24*05276bf3Sskrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25*05276bf3Sskrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26*05276bf3Sskrll * SUCH DAMAGE. 27*05276bf3Sskrll */ 28*05276bf3Sskrll 29*05276bf3Sskrll /* Physical address format bit definitions */ 30*05276bf3Sskrll #define PHYS_HI_RELO __BIT(31) 31*05276bf3Sskrll #define PHYS_HI_PREFETCH __BIT(30) 32*05276bf3Sskrll #define PHYS_HI_ALIASED __BIT(29) 33*05276bf3Sskrll #define PHYS_HI_SPACE __BITS(25,24) 34*05276bf3Sskrll #define PHYS_HI_SPACE_CFG 0 35*05276bf3Sskrll #define PHYS_HI_SPACE_IO 1 36*05276bf3Sskrll #define PHYS_HI_SPACE_MEM32 2 37*05276bf3Sskrll #define PHYS_HI_SPACE_MEM64 3 38*05276bf3Sskrll #define PHYS_HI_BUS __BITS(23,16) 39*05276bf3Sskrll #define PHYS_HI_DEVICE __BITS(15,11) 40*05276bf3Sskrll #define PHYS_HI_FUNCTION __BITS(10,8) 41*05276bf3Sskrll #define PHYS_HI_REGISTER __BITS(7,0) 42*05276bf3Sskrll 43*05276bf3Sskrll extern int pcihost_segment; 44*05276bf3Sskrll 45*05276bf3Sskrll enum pcihost_type { 46*05276bf3Sskrll PCIHOST_CAM = 1, 47*05276bf3Sskrll PCIHOST_ECAM, 48*05276bf3Sskrll }; 49*05276bf3Sskrll 50*05276bf3Sskrll struct pcihost_msi_handlers; 51*05276bf3Sskrll 52*05276bf3Sskrll struct pcih_bus_space { 53*05276bf3Sskrll struct bus_space bst; 54*05276bf3Sskrll 55*05276bf3Sskrll int (*map)(void *, bus_addr_t, bus_size_t, 56*05276bf3Sskrll int, bus_space_handle_t *); 57*05276bf3Sskrll int flags; 58*05276bf3Sskrll 59*05276bf3Sskrll struct space_range { 60*05276bf3Sskrll bus_addr_t bpci; 61*05276bf3Sskrll bus_addr_t bbus; 62*05276bf3Sskrll bus_size_t size; 63*05276bf3Sskrll } ranges[4]; 64*05276bf3Sskrll size_t nranges; 65*05276bf3Sskrll }; 66*05276bf3Sskrll 67*05276bf3Sskrll struct pcihost_softc { 68*05276bf3Sskrll device_t sc_dev; 69*05276bf3Sskrll bus_dma_tag_t sc_dmat; 70*05276bf3Sskrll bus_space_tag_t sc_bst; 71*05276bf3Sskrll bus_space_handle_t sc_bsh; 72*05276bf3Sskrll bus_space_tag_t sc_pci_bst; 73*05276bf3Sskrll int sc_phandle; 74*05276bf3Sskrll 75*05276bf3Sskrll enum pcihost_type sc_type; 76*05276bf3Sskrll 77*05276bf3Sskrll u_int sc_seg; 78*05276bf3Sskrll u_int sc_bus_min; 79*05276bf3Sskrll u_int sc_bus_max; 80*05276bf3Sskrll 81*05276bf3Sskrll struct riscv_pci_chipset 82*05276bf3Sskrll sc_pc; 83*05276bf3Sskrll 84*05276bf3Sskrll struct pcih_bus_space sc_io; 85*05276bf3Sskrll struct pcih_bus_space sc_mem; 86*05276bf3Sskrll 87*05276bf3Sskrll int sc_pci_flags; 88*05276bf3Sskrll 89*05276bf3Sskrll const u_int *sc_pci_ranges; 90*05276bf3Sskrll u_int sc_pci_ranges_cells; 91*05276bf3Sskrll 92*05276bf3Sskrll #ifdef __HAVE_PCI_MSI_MSIX 93*05276bf3Sskrll kmutex_t sc_msi_handlers_mutex; 94*05276bf3Sskrll LIST_HEAD(, pcihost_msi_handler) 95*05276bf3Sskrll sc_msi_handlers; 96*05276bf3Sskrll #endif 97*05276bf3Sskrll }; 98*05276bf3Sskrll 99*05276bf3Sskrll void pcihost_init2(struct pcihost_softc *); 100*05276bf3Sskrll void pcihost_init(pci_chipset_tag_t, void *); 101