1*ce099b40Smartin /* $NetBSD: hid_601.h,v 1.2 2008/04/28 20:23:32 martin Exp $ */ 22b0e97a5Smatt 32b0e97a5Smatt /*- 42b0e97a5Smatt * Copyright (c) 1999 The NetBSD Foundation, Inc. 52b0e97a5Smatt * All rights reserved. 62b0e97a5Smatt * 72b0e97a5Smatt * This code is derived from software contributed to The NetBSD Foundation 82b0e97a5Smatt * by Jason R. Thorpe. 92b0e97a5Smatt * 102b0e97a5Smatt * Redistribution and use in source and binary forms, with or without 112b0e97a5Smatt * modification, are permitted provided that the following conditions 122b0e97a5Smatt * are met: 132b0e97a5Smatt * 1. Redistributions of source code must retain the above copyright 142b0e97a5Smatt * notice, this list of conditions and the following disclaimer. 152b0e97a5Smatt * 2. Redistributions in binary form must reproduce the above copyright 162b0e97a5Smatt * notice, this list of conditions and the following disclaimer in the 172b0e97a5Smatt * documentation and/or other materials provided with the distribution. 182b0e97a5Smatt * 192b0e97a5Smatt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 202b0e97a5Smatt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 212b0e97a5Smatt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 222b0e97a5Smatt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 232b0e97a5Smatt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 242b0e97a5Smatt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 252b0e97a5Smatt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 262b0e97a5Smatt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 272b0e97a5Smatt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 282b0e97a5Smatt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 292b0e97a5Smatt * POSSIBILITY OF SUCH DAMAGE. 302b0e97a5Smatt */ 312b0e97a5Smatt 322b0e97a5Smatt #ifndef _POWERPC_OEA_HID_601_H_ 332b0e97a5Smatt #define _POWERPC_OEA_HID_601_H_ 342b0e97a5Smatt /* 352b0e97a5Smatt * Hardware Implementation Dependent registers for the PowerPC 601. 362b0e97a5Smatt */ 372b0e97a5Smatt 382b0e97a5Smatt /* 392b0e97a5Smatt * HID0 (SPR 1008) -- Checkstop Enable/Disable and Status register 402b0e97a5Smatt */ 412b0e97a5Smatt /* v- feature bits -v */ 422b0e97a5Smatt #define HID0_601_EHP 0x00000001 /* enable HP_SNP_REQ# */ 432b0e97a5Smatt #define HID0_601_EMC 0x00000002 /* main cache error */ 442b0e97a5Smatt #define HID0_601_PAR 0x00000004 /* precharge of ARTRY#/SHD# disabled */ 452b0e97a5Smatt #define HID0_601_LM 0x00000008 /* little endian mode */ 462b0e97a5Smatt #define HID0_601_DRL 0x00000010 /* alt sec rld of load/store miss */ 472b0e97a5Smatt #define HID0_601_DRF 0x00000020 /* alt sec rld of insn fetch miss */ 482b0e97a5Smatt /* v- checkstop enable/disable bits -v */ 492b0e97a5Smatt #define HID0_601_EPP 0x00000040 /* i/o protocol checkstop */ 502b0e97a5Smatt #define HID0_601_EIU 0x00000080 /* invalid uCode checkstop */ 512b0e97a5Smatt #define HID0_601_ECP 0x00000100 /* cache parity checkstop */ 522b0e97a5Smatt #define HID0_601_EBD 0x00000200 /* data bus parity checkstop */ 532b0e97a5Smatt #define HID0_601_EBA 0x00000400 /* address bus parity checkstop */ 542b0e97a5Smatt #define HID0_601_EDT 0x00000800 /* dispatch timeout checkstop */ 552b0e97a5Smatt #define HID0_601_ESH 0x00001000 /* sequencer timeout checkstop */ 562b0e97a5Smatt #define HID0_601_ECD 0x00002000 /* cache checkstop */ 572b0e97a5Smatt #define HID0_601_ETD 0x00004000 /* TLB checkstop */ 582b0e97a5Smatt #define HID0_601_EM 0x00008000 /* machine checkstop */ 592b0e97a5Smatt #define HID0_601_ES 0x00010000 /* uCode checkstop */ 602b0e97a5Smatt /* 0x00020000 reserved */ 612b0e97a5Smatt /* 0x00040000 reserved */ 622b0e97a5Smatt /* 0x00080000 reserved */ 632b0e97a5Smatt /* v- status bits -- correspond to enable bits above -v */ 642b0e97a5Smatt #define HID0_601_PP 0x00100000 652b0e97a5Smatt #define HID0_601_IU 0x00200000 662b0e97a5Smatt #define HID0_601_CP 0x00400000 672b0e97a5Smatt #define HID0_601_BD 0x00800000 682b0e97a5Smatt #define HID0_601_BA 0x01000000 692b0e97a5Smatt #define HID0_601_DT 0x02000000 702b0e97a5Smatt #define HID0_601_SH 0x04000000 712b0e97a5Smatt #define HID0_601_CD 0x08000000 722b0e97a5Smatt #define HID0_601_TD 0x10000000 732b0e97a5Smatt #define HID0_601_M 0x20000000 742b0e97a5Smatt #define HID0_601_S 0x40000000 752b0e97a5Smatt 762b0e97a5Smatt #define HID0_601_CE 0x80000000 /* master checkstop enable */ 772b0e97a5Smatt 782b0e97a5Smatt #define HID0_601_BITMASK "\020" \ 792b0e97a5Smatt "\040CE\037S\036M\035TD\034CD\033SH\032DT\031BA" \ 802b0e97a5Smatt "\030BD\027CP\026IU\025PP\021ES" \ 812b0e97a5Smatt "\020EM\017ETC\016ECD\015ESH\014EDT\013EBA\012EBD\011ECP" \ 822b0e97a5Smatt "\010EIU\007EPP\006DRF\005DRL\004LM\003PAR\002EMC\001EHP" 832b0e97a5Smatt 842b0e97a5Smatt 852b0e97a5Smatt /* 862b0e97a5Smatt * HID1 (SPR 1009) -- Debug Modes register 872b0e97a5Smatt */ 882b0e97a5Smatt /* XXX */ 892b0e97a5Smatt 902b0e97a5Smatt 912b0e97a5Smatt /* 922b0e97a5Smatt * HID2 (SPR 1010) -- Instruction Address Breakpoint Register 932b0e97a5Smatt */ 942b0e97a5Smatt 952b0e97a5Smatt 962b0e97a5Smatt /* 972b0e97a5Smatt * HID5 (SPR 1013) -- Data Address Breakpoint Register 982b0e97a5Smatt */ 992b0e97a5Smatt 1002b0e97a5Smatt 1012b0e97a5Smatt /* 1022b0e97a5Smatt * HID15 (SPR 1023) -- Processor ID Register 1032b0e97a5Smatt */ 1042b0e97a5Smatt #define HID15_601_PID 0x0000000f /* processor ID mask */ 1052b0e97a5Smatt 1062b0e97a5Smatt #endif /* _POWERPC_OEA_HID_601_H_ */ 107