xref: /netbsd-src/sys/arch/powerpc/ibm4xx/dev/rgmiireg.h (revision 2692e2e238fd00b4477c93bd308bca5c3a5c1fce)
1*2692e2e2Skiyohara /*	$NetBSD: rgmiireg.h,v 1.1 2010/03/18 13:47:04 kiyohara Exp $	*/
2*2692e2e2Skiyohara /*
3*2692e2e2Skiyohara  * Copyright (c) 2010 KIYOHARA Takashi
4*2692e2e2Skiyohara  * All rights reserved.
5*2692e2e2Skiyohara  *
6*2692e2e2Skiyohara  * Redistribution and use in source and binary forms, with or without
7*2692e2e2Skiyohara  * modification, are permitted provided that the following conditions
8*2692e2e2Skiyohara  * are met:
9*2692e2e2Skiyohara  * 1. Redistributions of source code must retain the above copyright
10*2692e2e2Skiyohara  *    notice, this list of conditions and the following disclaimer.
11*2692e2e2Skiyohara  * 2. Redistributions in binary form must reproduce the above copyright
12*2692e2e2Skiyohara  *    notice, this list of conditions and the following disclaimer in the
13*2692e2e2Skiyohara  *    documentation and/or other materials provided with the distribution.
14*2692e2e2Skiyohara  *
15*2692e2e2Skiyohara  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16*2692e2e2Skiyohara  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17*2692e2e2Skiyohara  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18*2692e2e2Skiyohara  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19*2692e2e2Skiyohara  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20*2692e2e2Skiyohara  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21*2692e2e2Skiyohara  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22*2692e2e2Skiyohara  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23*2692e2e2Skiyohara  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24*2692e2e2Skiyohara  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25*2692e2e2Skiyohara  * POSSIBILITY OF SUCH DAMAGE.
26*2692e2e2Skiyohara  */
27*2692e2e2Skiyohara 
28*2692e2e2Skiyohara #ifndef _IBM4XX_RGMIIREG_H_
29*2692e2e2Skiyohara #define	_IBM4XX_RGMIIREG_H_
30*2692e2e2Skiyohara 
31*2692e2e2Skiyohara /* RGMII (reduced GMII) Bridge (405EX/440GX(EMAC 2, 3)) */
32*2692e2e2Skiyohara 
33*2692e2e2Skiyohara #define RGMII0_SIZE		0x8
34*2692e2e2Skiyohara 
35*2692e2e2Skiyohara #define RGMII0_FER		0x0	/* Function Enable Register */
36*2692e2e2Skiyohara #define   FER_MDIOEN_MASK	  0x000c0000	/* MDIO enable */
37*2692e2e2Skiyohara #define   FER_MDIOEN(emac)	  (1 << ((1 - ((emac) % 2)) + 18))
38*2692e2e2Skiyohara #define   FER_CHCFG_MASK	  0x7		/* EMAC n Mask */
39*2692e2e2Skiyohara #define   FER_CHCFG_RTBI	  0x4		/* RTBI enabled */
40*2692e2e2Skiyohara #define   FER_CHCFG_RGMII	  0x5		/* RGMII enabled */
41*2692e2e2Skiyohara #define   FER_CHCFG_TBI		  0x6		/* TBI enabled */
42*2692e2e2Skiyohara #define   FER_CHCFG_GMII	  0x7		/* GMII enabled */
43*2692e2e2Skiyohara #define   FER_CHCFG(rgmii, val)	  ((val) << ((rgmii) << 2))
44*2692e2e2Skiyohara #define RGMII0_SSR		0x4	/* Speed Select Register */
45*2692e2e2Skiyohara #define   SSR_SP_MASK		  0x7
46*2692e2e2Skiyohara #define   SSR_SP_10MBPS		  0x0
47*2692e2e2Skiyohara #define   SSR_SP_100MBPS	  0x2
48*2692e2e2Skiyohara #define   SSR_SP_1000MBPS	  0x4
49*2692e2e2Skiyohara #define   SSR_SP(emac, sp)	  ((sp) << (((emac) % 2) << 3))
50*2692e2e2Skiyohara 
51*2692e2e2Skiyohara #endif	/* _IBM4XX_RGMIIREG_H_ */
52