xref: /netbsd-src/sys/arch/powerpc/ibm4xx/dev/opbreg.h (revision 2692e2e238fd00b4477c93bd308bca5c3a5c1fce)
1*2692e2e2Skiyohara /*	$NetBSD: opbreg.h,v 1.2 2010/03/18 13:47:04 kiyohara Exp $	*/
2497d6762Ssimonb 
3497d6762Ssimonb /*
4497d6762Ssimonb  * Copyright 2001 Wasabi Systems, Inc.
5497d6762Ssimonb  * All rights reserved.
6497d6762Ssimonb  *
7497d6762Ssimonb  * Written by Simon Burge and Eduardo Horvath for Wasabi Systems, Inc.
8497d6762Ssimonb  *
9497d6762Ssimonb  * Redistribution and use in source and binary forms, with or without
10497d6762Ssimonb  * modification, are permitted provided that the following conditions
11497d6762Ssimonb  * are met:
12497d6762Ssimonb  * 1. Redistributions of source code must retain the above copyright
13497d6762Ssimonb  *    notice, this list of conditions and the following disclaimer.
14497d6762Ssimonb  * 2. Redistributions in binary form must reproduce the above copyright
15497d6762Ssimonb  *    notice, this list of conditions and the following disclaimer in the
16497d6762Ssimonb  *    documentation and/or other materials provided with the distribution.
17497d6762Ssimonb  * 3. All advertising materials mentioning features or use of this software
18497d6762Ssimonb  *    must display the following acknowledgement:
19497d6762Ssimonb  *      This product includes software developed for the NetBSD Project by
20497d6762Ssimonb  *      Wasabi Systems, Inc.
21497d6762Ssimonb  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22497d6762Ssimonb  *    or promote products derived from this software without specific prior
23497d6762Ssimonb  *    written permission.
24497d6762Ssimonb  *
25497d6762Ssimonb  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26497d6762Ssimonb  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27497d6762Ssimonb  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28497d6762Ssimonb  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29497d6762Ssimonb  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30497d6762Ssimonb  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31497d6762Ssimonb  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32497d6762Ssimonb  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33497d6762Ssimonb  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34497d6762Ssimonb  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35497d6762Ssimonb  * POSSIBILITY OF SUCH DAMAGE.
36497d6762Ssimonb  */
37497d6762Ssimonb 
38497d6762Ssimonb #ifndef _IBM4XX_OPBREG_H_
39497d6762Ssimonb #define	_IBM4XX_OPBREG_H_
40497d6762Ssimonb 
41*2692e2e2Skiyohara #define OPBREG_SIZE	0x1000
42*2692e2e2Skiyohara 
43497d6762Ssimonb /* OPB Arbiter Registers */
44497d6762Ssimonb #define	OPBA_PR			0x00	/* Priority Register */
45497d6762Ssimonb #define	OPBA_CR			0x01	/* Control Register */
46*2692e2e2Skiyohara 
47*2692e2e2Skiyohara 
48*2692e2e2Skiyohara /* ZMII Bridge (440EP/440GP/440GX) */
49*2692e2e2Skiyohara #define ZMII0_SIZE		0x10
50*2692e2e2Skiyohara #define ZMII0_FER		0x0	/* Function Enable Register */
51*2692e2e2Skiyohara #define   FER_MDI_MASK		  0x88880000	/* MDI enable */
52*2692e2e2Skiyohara #define   FER_MDI(emac)		  (1 << (31 - ((emac) << 2)))
53*2692e2e2Skiyohara #define   FER__MII_MASK		  0x7
54*2692e2e2Skiyohara #define   FER__MII_MII		  0x1		/* MII Enable */
55*2692e2e2Skiyohara #define   FER__MII_RMII		  0x2		/* ZMII (or RMII) Enable */
56*2692e2e2Skiyohara #define   FER__MII_SMII		  0x4		/* SMII Enable */
57*2692e2e2Skiyohara #define   FER__MII(emac, mii)	  ((mii) << (28 - ((emac) << 2)))
58*2692e2e2Skiyohara #define ZMII0_SSR		0x4	/* Speed Selection Register */
59*2692e2e2Skiyohara #define   SSR_SCI(emac)		  (0x4 << (28 - ((emac) << 2))) /* Suppress Collision Indication */
60*2692e2e2Skiyohara #define   SSR_FSS(emac)		  (0x2 << (28 - ((emac) << 2))) /* Force Speed Selection */
61*2692e2e2Skiyohara #define   SSR_SP_10MBPS		  0x0
62*2692e2e2Skiyohara #define   SSR_SP_100MBPS	  0x2
63*2692e2e2Skiyohara #define   SSR_ZSP(emac, sp)	  ((sp) << (27 - ((emac) << 2))) /* Speed Selection */
64*2692e2e2Skiyohara #define ZMII0_SMIISR		0x8	/* SMII Status Register */
65*2692e2e2Skiyohara #define   SMIISR_SHIFT(emac)	  (24 - ((emac) << 3))
66*2692e2e2Skiyohara #define   SMIISR_MASK		  0xff
67*2692e2e2Skiyohara #define   SMIISR_E1		  0x01		/* RxD Set to 1 */
68*2692e2e2Skiyohara #define   SMIISR_EC		  0x02		/* RxD False Carrier Detected */
69*2692e2e2Skiyohara #define   SMIISR_EN_INVALID	  0x00		/* RxD Nibble  Invalid */
70*2692e2e2Skiyohara #define   SMIISR_EN_VALID	  0x04		/* RxD Nibble  Valid */
71*2692e2e2Skiyohara #define   SMIISR_EJ_OK		  0x00		/* RxD Jabber  OK */
72*2692e2e2Skiyohara #define   SMIISR_EJ_ERROR	  0x08		/* RxD Jabber  Error */
73*2692e2e2Skiyohara #define   SMIISR_EL_DOWN	  0x00		/* RxD Link  Down */
74*2692e2e2Skiyohara #define   SMIISR_EL_UP		  0x10		/* RxD Link  Up */
75*2692e2e2Skiyohara #define   SMIISR_ED_HALF	  0x00		/* RxD Duplex  Half */
76*2692e2e2Skiyohara #define   SMIISR_ED_FULL	  0x20		/* RxD Duplex  Full */
77*2692e2e2Skiyohara #define   SMIISR_ES_10		  0x00		/* RxD Speed  10MBit */
78*2692e2e2Skiyohara #define   SMIISR_ES_100		  0x40		/* RxD Speed  100MBit */
79*2692e2e2Skiyohara #define   SMIISR_EF		  0x80		/* RxD from Previous Frame */
80*2692e2e2Skiyohara 
81497d6762Ssimonb #endif	/* _IBM4XX_OPBREG_H_ */
82