1 /* $NetBSD: intr.h,v 1.2 1998/11/10 22:45:44 dbj Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Scott Reynolds 5 * Copyright (C) 1998 Darrin Jewell 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _NEXT68K_INTR_H_ 32 #define _NEXT68K_INTR_H_ 33 34 #include <machine/psl.h> 35 36 /* Probably want to dealwith IPL's here @@@ */ 37 38 #ifdef _KERNEL 39 /* 40 * spl functions; all but spl0 are done in-line 41 */ 42 43 #define _spl(s) \ 44 ({ \ 45 register int _spl_r; \ 46 \ 47 __asm __volatile ("clrl %0; movew sr,%0; movew %1,sr" : \ 48 "&=d" (_spl_r) : "di" (s)); \ 49 _spl_r; \ 50 }) 51 52 #define _splraise(s) \ 53 ({ \ 54 int _spl_r; \ 55 \ 56 __asm __volatile (" \ 57 clrl d0 ; \ 58 movw sr,d0 ; \ 59 movl d0,%0 ; \ 60 andw #0x700,d0 ; \ 61 movw %1,d1 ; \ 62 andw #0x700,d1 ; \ 63 cmpw d0,d1 ; \ 64 jle 1f ; \ 65 movw %1,sr ; \ 66 1:" : \ 67 "&=d" (_spl_r) : \ 68 "di" (s) : \ 69 "d0", "d1"); \ 70 _spl_r; \ 71 }) 72 73 /* spl0 requires checking for software interrupts */ 74 #define spl1() _spl(PSL_S|PSL_IPL1) 75 #define spl2() _spl(PSL_S|PSL_IPL2) 76 #define spl3() _spl(PSL_S|PSL_IPL3) 77 #define spl4() _spl(PSL_S|PSL_IPL4) 78 #define spl5() _spl(PSL_S|PSL_IPL5) 79 #define spl6() _spl(PSL_S|PSL_IPL6) 80 #define spl7() _spl(PSL_S|PSL_IPL7) 81 82 /* watch out for side effects */ 83 #define splx(s) ((s) & PSL_IPL ? _spl(s) : spl0()) 84 85 /****************************************************************/ 86 87 #define spldma() spl6() 88 89 #define splscc() spl5() 90 91 #define splsched() spl3() 92 93 /* IPL used by soft interrupts: netintr(), softclock() */ 94 #define splsoftclock() spl1() 95 #define splsoftnet() spl2() 96 97 98 /* Highest block device (strategy) IPL. */ 99 #define splbio() spl3() 100 101 /* Highest tty device IPL. */ 102 #define spltty() spl1() 103 104 /* Highest network interface IPL. */ 105 #define splnet() spl2() 106 107 /* 108 * Requirement: imp >= (highest network, tty, or disk IPL) 109 * This is used mostly in the VM code. (Why not splvm?) 110 * Note that the VM code runs at spl7 during kernel 111 * initialization, and later at spl0, so we have to 112 * use splraise to avoid enabling interrupts early. 113 */ 114 #if 0 115 #define splimp() _splraise(PSL_S|PSL_IPL3) 116 #else 117 #define splimp() _splraise(PSL_S|PSL_IPL6) 118 #endif 119 120 #define splclock() spl6() 121 #define splstatclock() splclock() 122 123 /* Block out all interrupts (except NMI of course). */ 124 #define splhigh() spl7() 125 126 /****************************************************************/ 127 128 /* 129 * simulated software interrupt register 130 */ 131 extern volatile u_int8_t ssir; 132 133 #define SIR_NET 0x01 134 #define SIR_CLOCK 0x02 135 #define SIR_SERIAL 0x04 136 #define SIR_DTMGR 0x08 137 #define SIR_ADB 0x10 138 139 #define siron(mask) \ 140 __asm __volatile ( "orb %0,_ssir" : : "i" (mask)) 141 #define siroff(mask) \ 142 __asm __volatile ( "andb %0,_ssir" : : "ir" (~(mask))); 143 144 #define setsoftnet() siron(SIR_NET) 145 #define setsoftclock() siron(SIR_CLOCK) 146 #define setsoftserial() siron(SIR_SERIAL) 147 #define setsoftdtmgr() siron(SIR_DTMGR) 148 #define setsoftadb() siron(SIR_ADB) 149 150 extern u_long allocate_sir __P((void (*)(void),void *)); 151 extern void init_sir __P((void)); 152 153 /* locore.s */ 154 int spl0 __P((void)); 155 #endif /* _KERNEL */ 156 157 #define INTR_SETMASK(x) ((*(volatile u_long *)IIOV(NEXT_P_INTRMASK))=(x)) 158 #define INTR_ENABLE(x) ((*(volatile u_long *)IIOV(NEXT_P_INTRMASK))|=NEXT_I_BIT(x)) 159 #define INTR_DISABLE(x) ((*(volatile u_long *)IIOV(NEXT_P_INTRMASK))&=(~NEXT_I_BIT(x))) 160 #define INTR_OCCURRED(x) ((*(volatile u_long *)IIOV(NEXT_P_INTRSTAT))& NEXT_I_BIT(x)) 161 162 #endif /* _NEXT68K_INTR_H_ */ 163