xref: /netbsd-src/sys/arch/newsmips/include/intr.h (revision 18d4eede3402827d776030ff7cf3315cb9e1039e)
1*18d4eedeStsutsui /*	$NetBSD: intr.h,v 1.27 2018/10/14 00:10:11 tsutsui Exp $	*/
2c0e7a80fStsubai 
3c9058cdcStsutsui /*-
4c9058cdcStsutsui  * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
5c9058cdcStsutsui  * All rights reserved.
6c9058cdcStsutsui  *
7c9058cdcStsutsui  * This code is derived from software contributed to The NetBSD Foundation
8c9058cdcStsutsui  * by Jason R. Thorpe.
9c0e7a80fStsubai  *
10c0e7a80fStsubai  * Redistribution and use in source and binary forms, with or without
11c0e7a80fStsubai  * modification, are permitted provided that the following conditions
12c0e7a80fStsubai  * are met:
13c0e7a80fStsubai  * 1. Redistributions of source code must retain the above copyright
14c0e7a80fStsubai  *    notice, this list of conditions and the following disclaimer.
15c0e7a80fStsubai  * 2. Redistributions in binary form must reproduce the above copyright
16c0e7a80fStsubai  *    notice, this list of conditions and the following disclaimer in the
17c0e7a80fStsubai  *    documentation and/or other materials provided with the distribution.
18c0e7a80fStsubai  *
19c9058cdcStsutsui  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20c9058cdcStsutsui  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21c9058cdcStsutsui  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22c9058cdcStsutsui  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23c9058cdcStsutsui  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24c9058cdcStsutsui  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25c9058cdcStsutsui  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26c9058cdcStsutsui  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27c9058cdcStsutsui  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28c9058cdcStsutsui  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29c9058cdcStsutsui  * POSSIBILITY OF SUCH DAMAGE.
30c0e7a80fStsubai  */
31c0e7a80fStsubai 
32c0e7a80fStsubai #ifndef _MACHINE_INTR_H_
33c0e7a80fStsubai #define _MACHINE_INTR_H_
34c0e7a80fStsubai 
35996804a5Smatt #include <mips/intr.h>
36c9058cdcStsutsui 
37b9d51debStsubai #ifdef _KERNEL
38996804a5Smatt #ifdef __INTR_PRIVATE
39c9058cdcStsutsui 
40e54edb5bStsutsui #include <sys/evcnt.h>
41c9058cdcStsutsui 
42996804a5Smatt extern const struct ipl_sr_map newmips_ipl_sr_map;
438bf76628Syamt 
44764da5a4Stsutsui struct newsmips_intrhand {
45764da5a4Stsutsui 	LIST_ENTRY(newsmips_intrhand) ih_q;
46764da5a4Stsutsui 	struct evcnt intr_count;
47764da5a4Stsutsui 	int (*ih_func)(void *);
48764da5a4Stsutsui 	void *ih_arg;
49764da5a4Stsutsui 	u_int ih_level;
50764da5a4Stsutsui 	u_int ih_mask;
51764da5a4Stsutsui 	u_int ih_priority;
52764da5a4Stsutsui };
53764da5a4Stsutsui 
54764da5a4Stsutsui struct newsmips_intr {
55764da5a4Stsutsui 	LIST_HEAD(,newsmips_intrhand) intr_q;
56764da5a4Stsutsui };
57764da5a4Stsutsui 
58c0e7a80fStsubai /*
59c0e7a80fStsubai  * Index into intrcnt[], which is defined in locore
60c0e7a80fStsubai  */
61c9058cdcStsutsui #define SERIAL0_INTR	0
62c9058cdcStsutsui #define SERIAL1_INTR	1
63c9058cdcStsutsui #define SERIAL2_INTR	2
64c9058cdcStsutsui #define LANCE_INTR	3
65c9058cdcStsutsui #define SCSI_INTR	4
66c9058cdcStsutsui #define ERROR_INTR	5
67c9058cdcStsutsui #define HARDCLOCK_INTR	6
68c9058cdcStsutsui #define FPU_INTR	7
69c9058cdcStsutsui #define SLOT1_INTR	8
70c9058cdcStsutsui #define SLOT2_INTR	9
71c9058cdcStsutsui #define SLOT3_INTR	10
72c9058cdcStsutsui #define FLOPPY_INTR	11
73c9058cdcStsutsui #define STRAY_INTR	12
74c0e7a80fStsubai 
75c0e7a80fStsubai extern u_int intrcnt[];
76c0e7a80fStsubai 
77a890d2ddStsubai /* handle i/o device interrupts */
78996804a5Smatt void news3400_intr(int, vaddr_t, uint32_t);
79996804a5Smatt void news5000_intr(int, vaddr_t, uint32_t);
80*18d4eedeStsutsui void news4000_intr(int, vaddr_t, uint32_t);
81996804a5Smatt extern void (*hardware_intr)(int, vaddr_t, uint32_t);
82b9d51debStsubai 
83fd4afa03Stsutsui extern void (*enable_intr)(void);
84fd4afa03Stsutsui extern void (*disable_intr)(void);
85fd4afa03Stsutsui extern void (*enable_timer)(void);
8670289b0fStsubai 
87996804a5Smatt #endif /* __INTR_PRIVATE */
88b9d51debStsubai #endif /* _KERNEL */
89c0e7a80fStsubai #endif /* _MACHINE_INTR_H_ */
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