1*33a78575Sryo /* $NetBSD: intr.h,v 1.13 2021/11/02 11:26:04 ryo Exp $ */
2e8300f36Such
3e8300f36Such /*-
4e8300f36Such * Copyright (c) 2002 The NetBSD Foundation, Inc.
5e8300f36Such * All rights reserved.
6e8300f36Such *
7e8300f36Such * Redistribution and use in source and binary forms, with or without
8e8300f36Such * modification, are permitted provided that the following conditions
9e8300f36Such * are met:
10e8300f36Such * 1. Redistributions of source code must retain the above copyright
11e8300f36Such * notice, this list of conditions and the following disclaimer.
12e8300f36Such * 2. Redistributions in binary form must reproduce the above copyright
13e8300f36Such * notice, this list of conditions and the following disclaimer in the
14e8300f36Such * documentation and/or other materials provided with the distribution.
15e8300f36Such *
16e8300f36Such * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17e8300f36Such * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18e8300f36Such * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19e8300f36Such * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20e8300f36Such * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21e8300f36Such * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22e8300f36Such * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23e8300f36Such * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24e8300f36Such * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25e8300f36Such * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26e8300f36Such * POSSIBILITY OF SUCH DAMAGE.
27e8300f36Such */
287ae4a95cSmsaitoh
297ae4a95cSmsaitoh #ifndef _MMEYE_INTR_H_
307ae4a95cSmsaitoh #define _MMEYE_INTR_H_
3165363da2Sitojun
3265363da2Sitojun #include <sh3/intr.h>
3365363da2Sitojun
34e8300f36Such /*
35e8300f36Such * Number of interrupt source
36e8300f36Such * TMU0, TMU1, TMU2
37e8300f36Such * MMEYE(com * 2 + mmeyepcmcia(controller + card) * 2)
38c111cdafSkiyohara * SCIF * 4, SCI * 4
39e8300f36Such */
40c111cdafSkiyohara #define _INTR_N 17
4165363da2Sitojun
42e8300f36Such /* Interrupt priority levels */
434b293a84Sad #define IPL_VM 12
444b293a84Sad #define IPL_SCHED 14 /* clock */
45e8300f36Such #define IPL_HIGH 15 /* everything */
467ae4a95cSmsaitoh
47b07ec3fcSad typedef uint8_t ipl_t;
488bf76628Syamt typedef struct {
498bf76628Syamt ipl_t _ipl;
508bf76628Syamt } ipl_cookie_t;
518bf76628Syamt
52*33a78575Sryo static __inline __always_inline ipl_cookie_t
makeiplcookie(ipl_t ipl)538bf76628Syamt makeiplcookie(ipl_t ipl)
548bf76628Syamt {
558bf76628Syamt
568bf76628Syamt return (ipl_cookie_t){._ipl = ipl << 4};
578bf76628Syamt }
588bf76628Syamt
59*33a78575Sryo static __inline __always_inline int
splraiseipl(ipl_cookie_t icookie)608bf76628Syamt splraiseipl(ipl_cookie_t icookie)
618bf76628Syamt {
628bf76628Syamt
638bf76628Syamt return _cpu_intr_raise(icookie._ipl);
648bf76628Syamt }
658bf76628Syamt
668bf76628Syamt #include <sys/spl.h>
6765363da2Sitojun
68e8300f36Such #define spl0() _cpu_intr_resume(0)
69e8300f36Such #define splx(x) _cpu_intr_resume(x)
707ae4a95cSmsaitoh
71e8300f36Such #endif /* !_MMEYE_INTR_H_ */
72