1*ed6f7336Sskrll /* $NetBSD: ingenic_coreregs.h,v 1.1 2017/05/21 06:49:13 skrll Exp $ */ 2*ed6f7336Sskrll 3*ed6f7336Sskrll /*- 4*ed6f7336Sskrll * Copyright (c) 2014 Michael Lorenz 5*ed6f7336Sskrll * All rights reserved. 6*ed6f7336Sskrll * 7*ed6f7336Sskrll * Redistribution and use in source and binary forms, with or without 8*ed6f7336Sskrll * modification, are permitted provided that the following conditions 9*ed6f7336Sskrll * are met: 10*ed6f7336Sskrll * 1. Redistributions of source code must retain the above copyright 11*ed6f7336Sskrll * notice, this list of conditions and the following disclaimer. 12*ed6f7336Sskrll * 2. Redistributions in binary form must reproduce the above copyright 13*ed6f7336Sskrll * notice, this list of conditions and the following disclaimer in the 14*ed6f7336Sskrll * documentation and/or other materials provided with the distribution. 15*ed6f7336Sskrll * 16*ed6f7336Sskrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17*ed6f7336Sskrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18*ed6f7336Sskrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19*ed6f7336Sskrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20*ed6f7336Sskrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21*ed6f7336Sskrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22*ed6f7336Sskrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23*ed6f7336Sskrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24*ed6f7336Sskrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25*ed6f7336Sskrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26*ed6f7336Sskrll * POSSIBILITY OF SUCH DAMAGE. 27*ed6f7336Sskrll */ 28*ed6f7336Sskrll 29*ed6f7336Sskrll #ifndef INGENIC_COREREGS_H 30*ed6f7336Sskrll #define INGENIC_COREREGS_H 31*ed6f7336Sskrll 32*ed6f7336Sskrll #ifdef _LOCORE 33*ed6f7336Sskrll #define _(n) __CONCAT($,n) 34*ed6f7336Sskrll #else 35*ed6f7336Sskrll #define _(n) n 36*ed6f7336Sskrll #endif 37*ed6f7336Sskrll 38*ed6f7336Sskrll /* cores status, 12 select 3 */ 39*ed6f7336Sskrll #define CP0_CORE_CTRL _(12), 2 /* select 2 */ 40*ed6f7336Sskrll #define CC_SW_RST0 __BIT(0) /* reset core 0 */ 41*ed6f7336Sskrll #define CC_SW_RST1 __BIT(1) /* reset core 1 */ 42*ed6f7336Sskrll #define CC_RPC0 __BIT(8) /* dedicated reset entry core 0 */ 43*ed6f7336Sskrll #define CC_RPC1 __BIT(9) /* -- || -- core 1 */ 44*ed6f7336Sskrll #define CC_SLEEP0M __BIT(16) /* mask sleep core 0 */ 45*ed6f7336Sskrll #define CC_SLEEP1M __BIT(17) /* mask sleep core 1 */ 46*ed6f7336Sskrll 47*ed6f7336Sskrll /* cores status, 12 select 3 */ 48*ed6f7336Sskrll #define CP0_CORE_STATUS _(12), 3 49*ed6f7336Sskrll #define CS_MIRQ0_P __BIT(0) /* mailbox IRQ for 0 pending */ 50*ed6f7336Sskrll #define CS_MIRQ1_P __BIT(1) /* || core 1 */ 51*ed6f7336Sskrll #define CS_IRQ0_P __BIT(8) /* peripheral IRQ for core 0 */ 52*ed6f7336Sskrll #define CS_IRQ1_P __BIT(9) /* || core 1 */ 53*ed6f7336Sskrll #define CS_SLEEP0 __BIT(16) /* core 0 sleeping */ 54*ed6f7336Sskrll #define CS_SLEEP1 __BIT(17) /* core 1 sleeping */ 55*ed6f7336Sskrll 56*ed6f7336Sskrll /* cores reset entry & IRQ masks - 12 select 4 */ 57*ed6f7336Sskrll #define CP0_CORE_REIM _(12), 4 58*ed6f7336Sskrll #define REIM_MIRQ0_M __BIT(0) /* allow mailbox IRQ for core 0 */ 59*ed6f7336Sskrll #define REIM_MIRQ1_M __BIT(1) /* allow mailbox IRQ for core 1 */ 60*ed6f7336Sskrll #define REIM_IRQ0_M __BIT(8) /* allow peripheral IRQ for core 0 */ 61*ed6f7336Sskrll #define REIM_IRQ1_M __BIT(9) /* allow peripheral IRQ for core 1 */ 62*ed6f7336Sskrll #define REIM_ENTRY_M __BITS(31,16) /* reset exception entry if RPCn=1 */ 63*ed6f7336Sskrll 64*ed6f7336Sskrll #define CP0_SPINLOCK _(12), 5 65*ed6f7336Sskrll #define CP0_SPINATOMIC _(12), 6 66*ed6f7336Sskrll 67*ed6f7336Sskrll #define CP0_CORE0_MBOX _(20), 0 68*ed6f7336Sskrll #define CP0_CORE1_MBOX _(20), 1 69*ed6f7336Sskrll 70*ed6f7336Sskrll #endif /* INGENIC_COREREGS_H */ 71