1*a8f91533Sandvar# $NetBSD: files.rmixl,v 1.5 2024/10/07 15:04:32 andvar Exp $ 2290a34a0Smatt# 3290a34a0Smatt# Configuration info for RMI XLP, XLR, XLS 4290a34a0Smatt# 5290a34a0Smatt 6e544d504Smattfile arch/mips/rmi/rmixl_spl.S 7290a34a0Smattfile arch/mips/rmi/rmixl_intr.c 8290a34a0Smattfile arch/mips/rmi/rmixl_subr.S 9e544d504Smattfile arch/mips/rmi/rmixl_fmn.c 10e544d504Smatt 11e544d504Smatt 12e544d504Smatt# node is parent of one or more core 13e544d504Smattdevice cpunode { [ core = -1] } 14e544d504Smattattach cpunode at mainbus with cpunode_rmixl 15e544d504Smattfile arch/mips/rmi/rmixl_cpunode.c cpunode_rmixl 16e544d504Smatt 17e544d504Smatt# core is parent of one or more cpu 18e544d504Smattdevice cpucore { [ thread = -1] } 19e544d504Smattattach cpucore at cpunode with cpucore_rmixl 20e544d504Smattfile arch/mips/rmi/rmixl_cpucore.c cpucore_rmixl 21e544d504Smatt 22e544d504Smatt# each cpu is a RMI 'thread' or 'vCPU' 23e544d504Smattdevice cpu 24e544d504Smattattach cpu at cpucore with cpu_rmixl 25e544d504Smattfile arch/mips/rmi/rmixl_cpu.c cpu_rmixl 26290a34a0Smatt 27290a34a0Smatt# OBIO: offsets are from System Bridge Controller base 28e544d504Smattdefine obio { [addr=-1], [size=0], [intr=-1], [tmsk=-1], [mult=1] } 29290a34a0Smattdevice obio: obio 30e544d504Smattattach obio at cpunode with obio_rmixl 31e544d504Smattfile arch/mips/rmi/rmixl_obio.c obio_rmixl 32e544d504Smattfile arch/mips/rmi/rmixl_obio_eb_space.c obio_rmixl 33e544d504Smattfile arch/mips/rmi/rmixl_obio_el_space.c obio_rmixl 34e544d504Smattfile arch/mips/rmi/rmixl_pci_cfg_space.c rmixl_pcix | rmixl_pcie 35e544d504Smattfile arch/mips/rmi/rmixl_pci_ecfg_space.c rmixl_pcie 36e544d504Smattfile arch/mips/rmi/rmixl_pci_io_space.c rmixl_pcix | rmixl_pcie 37e544d504Smattfile arch/mips/rmi/rmixl_pci_mem_space.c rmixl_pcix | rmixl_pcie 38290a34a0Smatt 39290a34a0Smatt# NS16550 compatible serial ports 40e544d504Smattattach com at obio with com_rmixl 41e544d504Smattfile arch/mips/rmi/rmixl_com.c com_rmixl 42290a34a0Smattdefparam opt_com.h CONSADDR CONSFREQ CONSPEED CONMODE 43290a34a0Smatt 449628d95fScliff# GPIO 459628d95fScliffdevice rmixl_gpio: gpiobus 469628d95fScliffattach rmixl_gpio at obio 479628d95fSclifffile arch/mips/rmi/rmixl_gpio.c rmixl_gpio 489628d95fScliff 49e544d504Smatt# PCIe 50290a34a0Smattdevice rmixl_pcie: pcibus 51290a34a0Smattattach rmixl_pcie at obio 52e544d504Smattfile arch/mips/rmi/rmixl_pcie.c rmixl_pcie needs-flag 53e544d504Smatt 54e544d504Smatt# PCI-X 55e544d504Smattdevice rmixl_pcix: pcibus 56e544d504Smattattach rmixl_pcix at obio 57e544d504Smattfile arch/mips/rmi/rmixl_pcix.c rmixl_pcix needs-flag 58e544d504Smatt 59*a8f91533Sandvar# RMI Peripheral IO Bus to Flash, PCMCIA memory controllers 609628d95fScliffdefine rmixl_iobus { [cs=-1], [addr=-1], [size=-1], [intr=-1] } 619628d95fScliffdevice rmixl_iobus: rmixl_iobus 629628d95fScliffattach rmixl_iobus at obio 639628d95fSclifffile arch/mips/rmi/rmixl_iobus_space.c rmixl_iobus 649628d95fSclifffile arch/mips/rmi/rmixl_iobus.c rmixl_iobus 659628d95fScliff 669628d95fScliff# NAND flash controller 679628d95fScliffdevice rmixl_nand: nandbus 689628d95fScliffattach rmixl_nand at rmixl_iobus 699628d95fSclifffile arch/mips/rmi/rmixl_nand.c rmixl_nand 709628d95fScliff 719628d95fScliff# PCMCIA controller 729628d95fScliffdevice rmixl_pcic: pcmciabus 739628d95fScliffattach rmixl_pcic at rmixl_iobus 749628d95fSclifffile arch/mips/rmi/rmixl_pcic.c rmixl_pcic 759628d95fScliff 76e544d504Smatt# On-chip USB interface 77e544d504Smattdefine rmixl_usbi { [addr=-1], [size=-1], [intr=-1] } 78e544d504Smattdevice rmixl_usbi: rmixl_usbi 79e544d504Smattattach rmixl_usbi at obio 80e544d504Smattfile arch/mips/rmi/rmixl_usbi.c rmixl_usbi 81e544d504Smatt 82e544d504Smatt# On-chip OHCI USB controller 83e544d504Smattattach ohci at rmixl_usbi with rmixl_ohci 84e544d504Smattfile arch/mips/rmi/rmixl_ohci.c ohci 85e544d504Smatt 86e544d504Smatt# On-chip EHCI USB controller 87e544d504Smattattach ehci at rmixl_usbi with rmixl_ehci 88e544d504Smattfile arch/mips/rmi/rmixl_ehci.c ehci 89290a34a0Smatt 90