1*eb61b502Ssimonb /* $NetBSD: octeon_usbnreg.h,v 1.3 2020/06/23 05:14:18 simonb Exp $ */ 2f693c922Shikaru 3f693c922Shikaru /* 4f693c922Shikaru * Copyright (c) 2007 Internet Initiative Japan, Inc. 5f693c922Shikaru * All rights reserved. 6f693c922Shikaru * 7f693c922Shikaru * Redistribution and use in source and binary forms, with or without 8f693c922Shikaru * modification, are permitted provided that the following conditions 9f693c922Shikaru * are met: 10f693c922Shikaru * 1. Redistributions of source code must retain the above copyright 11f693c922Shikaru * notice, this list of conditions and the following disclaimer. 12f693c922Shikaru * 2. Redistributions in binary form must reproduce the above copyright 13f693c922Shikaru * notice, this list of conditions and the following disclaimer in the 14f693c922Shikaru * documentation and/or other materials provided with the distribution. 15f693c922Shikaru * 16f693c922Shikaru * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17f693c922Shikaru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18f693c922Shikaru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19f693c922Shikaru * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20f693c922Shikaru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21f693c922Shikaru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22f693c922Shikaru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23f693c922Shikaru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24f693c922Shikaru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25f693c922Shikaru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26f693c922Shikaru * SUCH DAMAGE. 27f693c922Shikaru */ 28f693c922Shikaru 29f693c922Shikaru /* 30f693c922Shikaru * USBN Registers 31f693c922Shikaru */ 32f693c922Shikaru 33f693c922Shikaru #ifndef _OCTEON_USBNREG_H_ 34f693c922Shikaru #define _OCTEON_USBNREG_H_ 35f693c922Shikaru 36f693c922Shikaru /* ---- register addresses */ 37f693c922Shikaru 38f693c922Shikaru #define USBN_INT_SUM 0x0001180068000000ULL 39f693c922Shikaru #define USBN_INT_ENB 0x0001180068000008ULL 40f693c922Shikaru #define USBN_CLK_CTL 0x0001180068000010ULL 41f693c922Shikaru #define USBN_USBP_CTL_STATUS 0x0001180068000018ULL 42f693c922Shikaru #define USBN_BIST_STATUS 0x00011800680007f8ULL 43f693c922Shikaru #define USBN_CTL_STATUS 0x00016F0000000800ULL 44f693c922Shikaru #define USBN_DMA_TEST 0x00016F0000000808ULL 45f693c922Shikaru #define USBN_DMA0_INB_CHN0 0x00016F0000000818ULL 46f693c922Shikaru #define USBN_DMA0_INB_CHN1 0x00016F0000000820ULL 47f693c922Shikaru #define USBN_DMA0_INB_CHN2 0x00016F0000000828ULL 48f693c922Shikaru #define USBN_DMA0_INB_CHN3 0x00016F0000000830ULL 49f693c922Shikaru #define USBN_DMA0_INB_CHN4 0x00016F0000000838ULL 50f693c922Shikaru #define USBN_DMA0_INB_CHN5 0x00016F0000000840ULL 51f693c922Shikaru #define USBN_DMA0_INB_CHN6 0x00016F0000000848ULL 52f693c922Shikaru #define USBN_DMA0_INB_CHN7 0x00016F0000000850ULL 53f693c922Shikaru #define USBN_DMA0_OUTB_CHN0 0x00016F0000000858ULL 54f693c922Shikaru #define USBN_DMA0_OUTB_CHN1 0x00016F0000000860ULL 55f693c922Shikaru #define USBN_DMA0_OUTB_CHN2 0x00016F0000000868ULL 56f693c922Shikaru #define USBN_DMA0_OUTB_CHN3 0x00016F0000000870ULL 57f693c922Shikaru #define USBN_DMA0_OUTB_CHN4 0x00016F0000000878ULL 58f693c922Shikaru #define USBN_DMA0_OUTB_CHN5 0x00016F0000000880ULL 59f693c922Shikaru #define USBN_DMA0_OUTB_CHN6 0x00016F0000000888ULL 60f693c922Shikaru #define USBN_DMA0_OUTB_CHN7 0x00016F0000000890ULL 61f693c922Shikaru 62f693c922Shikaru /* ---- register bits */ 63f693c922Shikaru 64f693c922Shikaru /* for USBN_INT_SUM and USBN_INT_ENB */ 65f693c922Shikaru #define USBN_INT_XXX_63_38 UINT64_C(0xffffffc000000000) 66f693c922Shikaru #define USBN_INT_ND4O_DPF UINT64_C(0x0000002000000000) 67f693c922Shikaru #define USBN_INT_ND4O_DPE UINT64_C(0x0000001000000000) 68f693c922Shikaru #define USBN_INT_ND4O_RPF UINT64_C(0x0000000800000000) 69f693c922Shikaru #define USBN_INT_ND4O_RPE UINT64_C(0x0000000400000000) 70f693c922Shikaru #define USBN_INT_LTL_F_PF UINT64_C(0x0000000200000000) 71f693c922Shikaru #define USBN_INT_LTL_F_PE UINT64_C(0x0000000100000000) 72f693c922Shikaru #define USBN_INT_U2N_C_PE UINT64_C(0x0000000080000000) 73f693c922Shikaru #define USBN_INT_U2N_C_PF UINT64_C(0x0000000040000000) 74f693c922Shikaru #define USBN_INT_U2N_D_PF UINT64_C(0x0000000020000000) 75f693c922Shikaru #define USBN_INT_U2N_D_PE UINT64_C(0x0000000010000000) 76f693c922Shikaru #define USBN_INT_N2U_PE UINT64_C(0x0000000008000000) 77f693c922Shikaru #define USBN_INT_N2U_PF UINT64_C(0x0000000004000000) 78f693c922Shikaru #define USBN_INT_UOD_PF UINT64_C(0x0000000002000000) 79f693c922Shikaru #define USBN_INT_UOD_PE UINT64_C(0x0000000001000000) 80f693c922Shikaru #define USBN_INT_RQ_Q3_E UINT64_C(0x0000000000800000) 81f693c922Shikaru #define USBN_INT_RQ_Q3_F UINT64_C(0x0000000000400000) 82f693c922Shikaru #define USBN_INT_RQ_Q2_E UINT64_C(0x0000000000200000) 83f693c922Shikaru #define USBN_INT_RQ_Q2_F UINT64_C(0x0000000000100000) 84f693c922Shikaru #define USBN_INT_RG_FI_F UINT64_C(0x0000000000080000) 85f693c922Shikaru #define USBN_INT_RG_FI_E UINT64_C(0x0000000000040000) 86f693c922Shikaru #define USBN_INT_LT_FI_F UINT64_C(0x0000000000020000) 87f693c922Shikaru #define USBN_INT_LT_FI_E UINT64_C(0x0000000000010000) 88f693c922Shikaru #define USBN_INT_L2C_A_F UINT64_C(0x0000000000008000) 89f693c922Shikaru #define USBN_INT_L2C_S_E UINT64_C(0x0000000000004000) 90f693c922Shikaru #define USBN_INT_DCRED_F UINT64_C(0x0000000000002000) 91f693c922Shikaru #define USBN_INT_DCRED_E UINT64_C(0x0000000000001000) 92f693c922Shikaru #define USBN_INT_LT_PU_F UINT64_C(0x0000000000000800) 93f693c922Shikaru #define USBN_INT_LT_PO_E UINT64_C(0x0000000000000400) 94f693c922Shikaru #define USBN_INT_NT_PU_F UINT64_C(0x0000000000000200) 95f693c922Shikaru #define USBN_INT_NT_PO_E UINT64_C(0x0000000000000100) 96f693c922Shikaru #define USBN_INT_PT_PU_F UINT64_C(0x0000000000000080) 97f693c922Shikaru #define USBN_INT_PT_PO_E UINT64_C(0x0000000000000040) 98f693c922Shikaru #define USBN_INT_LR_PU_F UINT64_C(0x0000000000000020) 99f693c922Shikaru #define USBN_INT_LR_PO_E UINT64_C(0x0000000000000010) 100f693c922Shikaru #define USBN_INT_NR_PU_F UINT64_C(0x0000000000000008) 101f693c922Shikaru #define USBN_INT_NR_PO_E UINT64_C(0x0000000000000004) 102f693c922Shikaru #define USBN_INT_PR_PU_F UINT64_C(0x0000000000000002) 103f693c922Shikaru #define USBN_INT_PR_PO_E UINT64_C(0x0000000000000001) 104f693c922Shikaru 105f693c922Shikaru #define USBN_CLK_CTL_XXX_63_18 UINT64_C(0xfffffffffffc0000) 106f693c922Shikaru #define USBN_CLK_CTL_HCLK_RST UINT64_C(0x0000000000020000) 107f693c922Shikaru #define USBN_CLK_CTL_P_X_ON UINT64_C(0x0000000000010000) 108f693c922Shikaru #define USBN_CLK_CTL_P_RCLK UINT64_C(0x0000000000008000) 109f693c922Shikaru #define USBN_CLK_CTL_P_XENBN UINT64_C(0x0000000000004000) 110f693c922Shikaru #define USBN_CLK_CTL_P_COM_ON UINT64_C(0x0000000000002000) 111f693c922Shikaru #define USBN_CLK_CTL_P_C_SEL UINT64_C(0x0000000000001800) 112*eb61b502Ssimonb #define USBN_CLK_CTL_P_C_SEL_12MHZ 0 113*eb61b502Ssimonb #define USBN_CLK_CTL_P_C_SEL_24MHZ 1 114*eb61b502Ssimonb #define USBN_CLK_CTL_P_C_SEL_48MHZ 2 115f693c922Shikaru #define USBN_CLK_CTL_CDIV_BYP UINT64_C(0x0000000000000400) 116f693c922Shikaru #define USBN_CLK_CTL_SD_MODE UINT64_C(0x0000000000000300) 117f693c922Shikaru #define USBN_CLK_CTL_S_BIST UINT64_C(0x0000000000000080) 118f693c922Shikaru #define USBN_CLK_CTL_POR UINT64_C(0x0000000000000040) 119f693c922Shikaru #define USBN_CLK_CTL_ENABLE UINT64_C(0x0000000000000020) 120f693c922Shikaru #define USBN_CLK_CTL_PRST UINT64_C(0x0000000000000010) 121f693c922Shikaru #define USBN_CLK_CTL_HRST UINT64_C(0x0000000000000008) 122f693c922Shikaru #define USBN_CLK_CTL_DIVIDE UINT64_C(0x0000000000000007) 123f693c922Shikaru /* CN50xx extension */ 124f693c922Shikaru #define USBN_CLK_CTL_DIVIDE2 UINT64_C(0x00000000000c0000) 125f693c922Shikaru #define USBN_CLK_CTL_P_RTYPE UINT64_C(0x000000000000c000) 126f693c922Shikaru 127f693c922Shikaru #define USBN_USBP_CTL_STATUS_XXX_63_38 UINT64_C(0xffffffc000000000) 128f693c922Shikaru #define USBN_USBP_CTL_STATUS_BIST_DONE UINT64_C(0x0000002000000000) 129f693c922Shikaru #define USBN_USBP_CTL_STATUS_BIST_ERR UINT64_C(0x0000001000000000) 130f693c922Shikaru #define USBN_USBP_CTL_STATUS_TDATA_OUT UINT64_C(0x0000000f00000000) 131f693c922Shikaru #define USBN_USBP_CTL_STATUS_SPARES UINT64_C(0x00000000e0000000) 132f693c922Shikaru #define USBN_USBP_CTL_STATUS_USBC_END UINT64_C(0x0000000010000000) 133f693c922Shikaru #define USBN_USBP_CTL_STATUS_USBP_BIST UINT64_C(0x0000000008000000) 134f693c922Shikaru #define USBN_USBP_CTL_STATUS_TCLK UINT64_C(0x0000000004000000) 135f693c922Shikaru #define USBN_USBP_CTL_STATUS_DP_PULLD UINT64_C(0x0000000002000000) 136f693c922Shikaru #define USBN_USBP_CTL_STATUS_DM_PULLD UINT64_C(0x0000000001000000) 137f693c922Shikaru #define USBN_USBP_CTL_STATUS_HST_MODE UINT64_C(0x0000000000800000) 138f693c922Shikaru #define USBN_USBP_CTL_STATUS_TUNING UINT64_C(0x0000000000780000) 139f693c922Shikaru #define USBN_USBP_CTL_STATUS_TX_BS_ENH UINT64_C(0x0000000000040000) 140f693c922Shikaru #define USBN_USBP_CTL_STATUS_TX_BS_EN UINT64_C(0x0000000000020000) 141f693c922Shikaru #define USBN_USBP_CTL_STATUS_LOOP_ENB UINT64_C(0x0000000000010000) 142f693c922Shikaru #define USBN_USBP_CTL_STATUS_VTEST_ENB UINT64_C(0x0000000000008000) 143f693c922Shikaru #define USBN_USBP_CTL_STATUS_BIST_ENB UINT64_C(0x0000000000004000) 144f693c922Shikaru #define USBN_USBP_CTL_STATUS_TDATA_SEL UINT64_C(0x0000000000002000) 145f693c922Shikaru #define USBN_USBP_CTL_STATUS_TADDR_IN UINT64_C(0x0000000000001e00) 146f693c922Shikaru #define USBN_USBP_CTL_STATUS_TDATA_IN UINT64_C(0x00000000000001fe) 147f693c922Shikaru #define USBN_USBP_CTL_STATUS_ATE_RESET UINT64_C(0x0000000000000001) 148f693c922Shikaru /* CN50xx extension */ 149f693c922Shikaru #define USBN_USBP_CTL_STATUS_TXRISETUNE UINT64_C(0x8000000000000000) 150f693c922Shikaru #define USBN_USBP_CTL_STATUS_TXVREFTUNE UINT64_C(0x7800000000000000) 151f693c922Shikaru #define USBN_USBP_CTL_STATUS_TXFSLSTUNE UINT64_C(0x0780000000000000) 152f693c922Shikaru #define USBN_USBP_CTL_STATUS_TXHSXVTUNE UINT64_C(0x0060000000000000) 153f693c922Shikaru #define USBN_USBP_CTL_STATUS_SQRXTUNE UINT64_C(0x001c000000000000) 154f693c922Shikaru #define USBN_USBP_CTL_STATUS_COMPDISTUNE UINT64_C(0x0003800000000000) 155f693c922Shikaru #define USBN_USBP_CTL_STATUS_OTGTUNE UINT64_C(0x0000700000000000) 156f693c922Shikaru #define USBN_USBP_CTL_STATUS_OTGDISABLE UINT64_C(0x0000080000000000) 157f693c922Shikaru #define USBN_USBP_CTL_STATUS_PORTRESET UINT64_C(0x0000040000000000) 158f693c922Shikaru #define USBN_USBP_CTL_STATUS_DRVVBUS UINT64_C(0x0000020000000000) 159f693c922Shikaru #define USBN_USBP_CTL_STATUS_LSBIST UINT64_C(0x0000010000000000) 160f693c922Shikaru #define USBN_USBP_CTL_STATUS_FSBIST UINT64_C(0x0000008000000000) 161f693c922Shikaru #define USBN_USBP_CTL_STATUS_HSBIST UINT64_C(0x0000004000000000) 162f693c922Shikaru 163f693c922Shikaru #define USBN_BIST_STATUS_XXX_63_3 UINT64_C(0xfffffffffffffff8) 164f693c922Shikaru #define USBN_BIST_STATUS_USBC_BIS UINT64_C(0x0000000000000004) 165f693c922Shikaru #define USBN_BIST_STATUS_NIF_BIS UINT64_C(0x0000000000000002) 166f693c922Shikaru #define USBN_BIST_STATUS_NOF_BIS UINT64_C(0x0000000000000001) 167f693c922Shikaru /* CN50xx extension */ 168f693c922Shikaru #define USBN_BIST_STATUS_U2NC_BIS UINT64_C(0x0000000000000040) 169f693c922Shikaru #define USBN_BIST_STATUS_U2NF_BIS UINT64_C(0x0000000000000020) 170f693c922Shikaru #define USBN_BIST_STATUS_E2HC_BIS UINT64_C(0x0000000000000010) 171f693c922Shikaru #define USBN_BIST_STATUS_N2UF_BIS UINT64_C(0x0000000000000008) 172f693c922Shikaru 173f693c922Shikaru #define USBN_CTL_STATUS_XXX_63_6 UINT64_C(0xffffffffffffffc0) 174f693c922Shikaru #define USBN_CTL_STATUS_DMA_0PAG UINT64_C(0x0000000000000020) 175f693c922Shikaru #define USBN_CTL_STATUS_DMA_STT UINT64_C(0x0000000000000010) 176f693c922Shikaru #define USBN_CTL_STATUS_DMA_TEST UINT64_C(0x0000000000000008) 177f693c922Shikaru #define USBN_CTL_STATUS_INV_A2 UINT64_C(0x0000000000000004) 178f693c922Shikaru #define USBN_CTL_STATUS_L2C_EMOD UINT64_C(0x0000000000000003) 179f693c922Shikaru 180f693c922Shikaru #define USBN_DMA_TEST_XXX_63_40 UINT64_C(0xffffff0000000000) 181f693c922Shikaru #define USBN_DMA_TEST_DONE UINT64_C(0x0000008000000000) 182f693c922Shikaru #define USBN_DMA_TEST_REQ UINT64_C(0x0000004000000000) 183f693c922Shikaru #define USBN_DMA_TEST_F_ADDR UINT64_C(0x0000003ffff00000) 184f693c922Shikaru #define USBN_DMA_TEST_COUNT UINT64_C(0x00000000000ffe00) 185f693c922Shikaru #define USBN_DMA_TEST_CHANNEL UINT64_C(0x00000000000001f0) 186f693c922Shikaru #define USBN_DMA_TEST_BURST UINT64_C(0x000000000000000f) 187f693c922Shikaru 188f693c922Shikaru /* for USBN_DMA0_INB_CHN(0..7) */ 189f693c922Shikaru #define USBN_DMA0_INB_CHNX_XXX_63_36 UINT64_C(0xfffffff000000000) 190f693c922Shikaru #define USBN_DMA0_INB_CHNX_ADDR UINT64_C(0x0000000fffffffff) 191f693c922Shikaru 192f693c922Shikaru /* for USBN_DMA0_OUTB_CHN(0..7) */ 193f693c922Shikaru #define USBN_DMA0_OUTB_CHNX_XXX_63_36 UINT64_C(0xfffffff000000000) 194f693c922Shikaru #define USBN_DMA0_OUTB_CHNX_ADDR UINT64_C(0x0000000fffffffff) 195f693c922Shikaru 196f693c922Shikaru /* ---- bus_space */ 197f693c922Shikaru 198f693c922Shikaru #define USBN_NUNITS 1 199f693c922Shikaru #define USBN_BASE 0x0001180068000000ULL 200f693c922Shikaru #define USBN_SIZE 0x800 201f693c922Shikaru 202f693c922Shikaru #define USBN_INT_SUM_OFFSET 0x00000000 203f693c922Shikaru #define USBN_INT_ENB_OFFSET 0x00000008 204f693c922Shikaru #define USBN_CLK_CTL_OFFSET 0x00000010 205f693c922Shikaru #define USBN_USBP_CTL_STATUS_OFFSET 0x00000018 206f693c922Shikaru #define USBN_BIST_STATUS_OFFSET 0x000007f8 207f693c922Shikaru 208f693c922Shikaru 209f693c922Shikaru /* ---- bus_space 2 */ 210f693c922Shikaru 211f693c922Shikaru #define USBN_2_NUNITS 1 212f693c922Shikaru #define USBN_2_BASE 0x00016F0000000800ULL 213f693c922Shikaru #define USBN_2_SIZE 0x098 214f693c922Shikaru 215f693c922Shikaru #define USBN_CTL_STATUS_OFFSET 0x00000000 216f693c922Shikaru #define USBN_DMA_TEST_OFFSET 0x00000008 217f693c922Shikaru #define USBN_DMA0_INB_CHN0_OFFSET 0x00000018 218f693c922Shikaru #define USBN_DMA0_INB_CHN1_OFFSET 0x00000020 219f693c922Shikaru #define USBN_DMA0_INB_CHN2_OFFSET 0x00000028 220f693c922Shikaru #define USBN_DMA0_INB_CHN3_OFFSET 0x00000030 221f693c922Shikaru #define USBN_DMA0_INB_CHN4_OFFSET 0x00000038 222f693c922Shikaru #define USBN_DMA0_INB_CHN5_OFFSET 0x00000040 223f693c922Shikaru #define USBN_DMA0_INB_CHN6_OFFSET 0x00000048 224f693c922Shikaru #define USBN_DMA0_INB_CHN7_OFFSET 0x00000050 225f693c922Shikaru #define USBN_DMA0_OUTB_CHN0_OFFSET 0x00000058 226f693c922Shikaru #define USBN_DMA0_OUTB_CHN1_OFFSET 0x00000060 227f693c922Shikaru #define USBN_DMA0_OUTB_CHN2_OFFSET 0x00000068 228f693c922Shikaru #define USBN_DMA0_OUTB_CHN3_OFFSET 0x00000070 229f693c922Shikaru #define USBN_DMA0_OUTB_CHN4_OFFSET 0x00000078 230f693c922Shikaru #define USBN_DMA0_OUTB_CHN5_OFFSET 0x00000080 231f693c922Shikaru #define USBN_DMA0_OUTB_CHN6_OFFSET 0x00000088 232f693c922Shikaru #define USBN_DMA0_OUTB_CHN7_OFFSET 0x00000090 233f693c922Shikaru 234f693c922Shikaru #endif /* _OCTEON_USBNREG_H_ */ 235