1*894a4342Skamil /* $NetBSD: octeon_uartreg.h,v 1.2 2019/04/11 11:40:58 kamil Exp $ */ 2f693c922Shikaru 3f693c922Shikaru /* 4f693c922Shikaru * Copyright (c) 2007 Internet Initiative Japan, Inc. 5f693c922Shikaru * All rights reserved. 6f693c922Shikaru * 7f693c922Shikaru * Redistribution and use in source and binary forms, with or without 8f693c922Shikaru * modification, are permitted provided that the following conditions 9f693c922Shikaru * are met: 10f693c922Shikaru * 1. Redistributions of source code must retain the above copyright 11f693c922Shikaru * notice, this list of conditions and the following disclaimer. 12f693c922Shikaru * 2. Redistributions in binary form must reproduce the above copyright 13f693c922Shikaru * notice, this list of conditions and the following disclaimer in the 14f693c922Shikaru * documentation and/or other materials provided with the distribution. 15f693c922Shikaru * 16f693c922Shikaru * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17f693c922Shikaru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18f693c922Shikaru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19f693c922Shikaru * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20f693c922Shikaru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21f693c922Shikaru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22f693c922Shikaru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23f693c922Shikaru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24f693c922Shikaru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25f693c922Shikaru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26f693c922Shikaru * SUCH DAMAGE. 27f693c922Shikaru */ 28f693c922Shikaru 29f693c922Shikaru /* 30f693c922Shikaru * UART Registers 31f693c922Shikaru */ 32f693c922Shikaru 33f693c922Shikaru #ifndef _OCTEON_UARTREG_H_ 34f693c922Shikaru #define _OCTEON_UARTREG_H_ 35f693c922Shikaru 36f693c922Shikaru /* ---- register addresses */ 37f693c922Shikaru 38f693c922Shikaru #define MIO_UART0_RBR 0x0001180000000800ULL 39f693c922Shikaru #define MIO_UART0_IER 0x0001180000000808ULL 40f693c922Shikaru #define MIO_UART0_IIR 0x0001180000000810ULL 41f693c922Shikaru #define MIO_UART0_LCR 0x0001180000000818ULL 42f693c922Shikaru #define MIO_UART0_MCR 0x0001180000000820ULL 43f693c922Shikaru #define MIO_UART0_LSR 0x0001180000000828ULL 44f693c922Shikaru #define MIO_UART0_MSR 0x0001180000000830ULL 45f693c922Shikaru #define MIO_UART0_SCR 0x0001180000000838ULL 46f693c922Shikaru #define MIO_UART0_THR 0x0001180000000840ULL 47f693c922Shikaru #define MIO_UART0_FCR 0x0001180000000850ULL 48f693c922Shikaru #define MIO_UART0_DLL 0x0001180000000880ULL 49f693c922Shikaru #define MIO_UART0_DLH 0x0001180000000888ULL 50f693c922Shikaru #define MIO_UART0_FAR 0x0001180000000920ULL 51f693c922Shikaru #define MIO_UART0_TFR 0x0001180000000928ULL 52f693c922Shikaru #define MIO_UART0_RFW 0x0001180000000930ULL 53f693c922Shikaru #define MIO_UART0_USR 0x0001180000000938ULL 54f693c922Shikaru #define MIO_UART0_TFL 0x0001180000000a00ULL 55f693c922Shikaru #define MIO_UART0_RFL 0x0001180000000a08ULL 56f693c922Shikaru #define MIO_UART0_SRR 0x0001180000000a10ULL 57f693c922Shikaru #define MIO_UART0_SRTS 0x0001180000000a18ULL 58f693c922Shikaru #define MIO_UART0_SBCR 0x0001180000000a20ULL 59f693c922Shikaru #define MIO_UART0_SFE 0x0001180000000a30ULL 60f693c922Shikaru #define MIO_UART0_SRT 0x0001180000000a38ULL 61f693c922Shikaru #define MIO_UART0_STT 0x0001180000000b00ULL 62f693c922Shikaru #define MIO_UART0_HTX 0x0001180000000b08ULL 63f693c922Shikaru #define MIO_UART1_RBR 0x0001180000000c00ULL 64f693c922Shikaru #define MIO_UART1_IER 0x0001180000000c08ULL 65f693c922Shikaru #define MIO_UART1_IIR 0x0001180000000c10ULL 66f693c922Shikaru #define MIO_UART1_LCR 0x0001180000000c18ULL 67f693c922Shikaru #define MIO_UART1_MCR 0x0001180000000c20ULL 68f693c922Shikaru #define MIO_UART1_LSR 0x0001180000000c28ULL 69f693c922Shikaru #define MIO_UART1_MSR 0x0001180000000c30ULL 70f693c922Shikaru #define MIO_UART1_SCR 0x0001180000000c38ULL 71f693c922Shikaru #define MIO_UART1_THR 0x0001180000000c40ULL 72f693c922Shikaru #define MIO_UART1_FCR 0x0001180000000c50ULL 73f693c922Shikaru #define MIO_UART1_DLL 0x0001180000000c80ULL 74f693c922Shikaru #define MIO_UART1_DLH 0x0001180000000c88ULL 75f693c922Shikaru #define MIO_UART1_FAR 0x0001180000000d20ULL 76f693c922Shikaru #define MIO_UART1_TFR 0x0001180000000d28ULL 77f693c922Shikaru #define MIO_UART1_RFW 0x0001180000000d30ULL 78f693c922Shikaru #define MIO_UART1_USR 0x0001180000000d38ULL 79f693c922Shikaru #define MIO_UART1_TFL 0x0001180000000e00ULL 80f693c922Shikaru #define MIO_UART1_RFL 0x0001180000000e08ULL 81f693c922Shikaru #define MIO_UART1_SRR 0x0001180000000e10ULL 82f693c922Shikaru #define MIO_UART1_SRTS 0x0001180000000e18ULL 83f693c922Shikaru #define MIO_UART1_SBCR 0x0001180000000e20ULL 84f693c922Shikaru #define MIO_UART1_SFE 0x0001180000000e30ULL 85f693c922Shikaru #define MIO_UART1_SRT 0x0001180000000e38ULL 86f693c922Shikaru #define MIO_UART1_STT 0x0001180000000f00ULL 87f693c922Shikaru #define MIO_UART1_HTX 0x0001180000000f08ULL 88f693c922Shikaru 89f693c922Shikaru /* ---- snprintb */ 90f693c922Shikaru 91f693c922Shikaru /* XXX */ 92f693c922Shikaru 93f693c922Shikaru /* ---- bus_space */ 94f693c922Shikaru 95f693c922Shikaru #define MIO_UART0_BASE 0x0001180000000800ULL 96f693c922Shikaru #define MIO_UART1_BASE 0x0001180000000c00ULL 97f693c922Shikaru 98f693c922Shikaru #define MIO_UART_RBR_OFFSET 0x0000 99f693c922Shikaru #define MIO_UART_IER_OFFSET 0x0008 100f693c922Shikaru #define MIO_UART_IIR_OFFSET 0x0010 101f693c922Shikaru #define MIO_UART_LCR_OFFSET 0x0018 102f693c922Shikaru #define MIO_UART_MCR_OFFSET 0x0020 103f693c922Shikaru #define MIO_UART_LSR_OFFSET 0x0028 104f693c922Shikaru #define MIO_UART_MSR_OFFSET 0x0030 105f693c922Shikaru #define MIO_UART_SCR_OFFSET 0x0038 106f693c922Shikaru #define MIO_UART_THR_OFFSET 0x0040 107f693c922Shikaru #define MIO_UART_FCR_OFFSET 0x0050 108f693c922Shikaru #define MIO_UART_DLL_OFFSET 0x0080 109f693c922Shikaru #define MIO_UART_DLH_OFFSET 0x0088 110f693c922Shikaru #define MIO_UART_FAR_OFFSET 0x0120 111f693c922Shikaru #define MIO_UART_TFR_OFFSET 0x0128 112f693c922Shikaru #define MIO_UART_RFW_OFFSET 0x0130 113f693c922Shikaru #define MIO_UART_USR_OFFSET 0x0138 114f693c922Shikaru #define MIO_UART_TFL_OFFSET 0x0200 115f693c922Shikaru #define MIO_UART_RFL_OFFSET 0x0208 116f693c922Shikaru #define MIO_UART_SRR_OFFSET 0x0210 117f693c922Shikaru #define MIO_UART_SRTS_OFFSET 0x0218 118f693c922Shikaru #define MIO_UART_SBCR_OFFSET 0x0220 119f693c922Shikaru #define MIO_UART_SFE_OFFSET 0x0230 120f693c922Shikaru #define MIO_UART_SRT_OFFSET 0x0238 121f693c922Shikaru #define MIO_UART_STT_OFFSET 0x0300 122f693c922Shikaru #define MIO_UART_HTX_OFFSET 0x0308 123f693c922Shikaru 124f693c922Shikaru #endif /* _OCTEON_UARTREG_H_ */ 125