xref: /netbsd-src/sys/arch/mips/cavium/dev/octeon_smivar.h (revision 092c6bf70adb0beda38e5014d15f5338efd7e22e)
1*092c6bf7Ssimonb /*	$NetBSD: octeon_smivar.h,v 1.6 2020/06/23 05:18:02 simonb Exp $	*/
2f693c922Shikaru 
3f693c922Shikaru /*
4f693c922Shikaru  * Copyright (c) 2007 Internet Initiative Japan, Inc.
5f693c922Shikaru  * All rights reserved.
6f693c922Shikaru  *
7f693c922Shikaru  * Redistribution and use in source and binary forms, with or without
8f693c922Shikaru  * modification, are permitted provided that the following conditions
9f693c922Shikaru  * are met:
10f693c922Shikaru  * 1. Redistributions of source code must retain the above copyright
11f693c922Shikaru  *    notice, this list of conditions and the following disclaimer.
12f693c922Shikaru  * 2. Redistributions in binary form must reproduce the above copyright
13f693c922Shikaru  *    notice, this list of conditions and the following disclaimer in the
14f693c922Shikaru  *    documentation and/or other materials provided with the distribution.
15f693c922Shikaru  *
16f693c922Shikaru  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17f693c922Shikaru  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18f693c922Shikaru  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19f693c922Shikaru  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20f693c922Shikaru  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21f693c922Shikaru  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22f693c922Shikaru  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23f693c922Shikaru  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24f693c922Shikaru  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25f693c922Shikaru  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26f693c922Shikaru  * SUCH DAMAGE.
27f693c922Shikaru  */
28f693c922Shikaru 
29f693c922Shikaru #ifndef _OCTEON_SMIVAR_H_
30f693c922Shikaru #define _OCTEON_SMIVAR_H_
31f693c922Shikaru 
32f693c922Shikaru /* XXX */
333f508e4dSsimonb struct octsmi_softc {
34*092c6bf7Ssimonb 	device_t		sc_dev;
35f693c922Shikaru 	int			sc_port;
36f693c922Shikaru 	bus_space_tag_t		sc_regt;
37f693c922Shikaru 	bus_space_handle_t	sc_regh;
38f693c922Shikaru };
39f693c922Shikaru 
403f508e4dSsimonb int	octsmi_read(struct octsmi_softc *, int, int, uint16_t *);
413f508e4dSsimonb int	octsmi_write(struct octsmi_softc *, int, int, uint16_t);
42*092c6bf7Ssimonb struct octsmi_softc
43*092c6bf7Ssimonb 	*octsmi_lookup(int, int);
44f693c922Shikaru 
45b9fcd28bSsimonb #endif /* _OCTEON_SMIVAR_H_ */
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