xref: /netbsd-src/sys/arch/mips/cavium/dev/octeon_pci.c (revision 09773f5b6cac6063a8c1c99a8f5e689bb0478168)
1*09773f5bSsimonb /*	$NetBSD: octeon_pci.c,v 1.5 2020/06/22 02:26:20 simonb Exp $	*/
2f693c922Shikaru 
3f693c922Shikaru /*
4f693c922Shikaru  * Copyright (c) 2007, 2008 Internet Initiative Japan, Inc.
5f693c922Shikaru  * All rights reserved.
6f693c922Shikaru  *
7f693c922Shikaru  * Redistribution and use in source and binary forms, with or without
8f693c922Shikaru  * modification, are permitted provided that the following conditions
9f693c922Shikaru  * are met:
10f693c922Shikaru  * 1. Redistributions of source code must retain the above copyright
11f693c922Shikaru  *    notice, this list of conditions and the following disclaimer.
12f693c922Shikaru  * 2. Redistributions in binary form must reproduce the above copyright
13f693c922Shikaru  *    notice, this list of conditions and the following disclaimer in the
14f693c922Shikaru  *    documentation and/or other materials provided with the distribution.
15f693c922Shikaru  *
16f693c922Shikaru  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17f693c922Shikaru  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18f693c922Shikaru  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19f693c922Shikaru  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20f693c922Shikaru  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21f693c922Shikaru  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22f693c922Shikaru  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23f693c922Shikaru  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24f693c922Shikaru  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25f693c922Shikaru  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26f693c922Shikaru  * SUCH DAMAGE.
27f693c922Shikaru  */
28f693c922Shikaru 
29f693c922Shikaru #include <sys/cdefs.h>
30*09773f5bSsimonb __KERNEL_RCSID(0, "$NetBSD: octeon_pci.c,v 1.5 2020/06/22 02:26:20 simonb Exp $");
31f693c922Shikaru 
32f693c922Shikaru #include "opt_octeon.h"
33f693c922Shikaru 
34f693c922Shikaru #include <sys/param.h>
35f693c922Shikaru #include <sys/systm.h>
36f693c922Shikaru #include <sys/types.h>
37f693c922Shikaru #include <sys/device.h>
38f693c922Shikaru 
39f693c922Shikaru #include <sys/bus.h>
40f693c922Shikaru 
41f693c922Shikaru #include <mips/cavium/octeonvar.h>
42f693c922Shikaru #include <mips/cavium/dev/octeon_ciureg.h>
43f693c922Shikaru #include <mips/cavium/dev/octeon_npireg.h>
44f693c922Shikaru 
45f693c922Shikaru /*
46f693c922Shikaru  * In OCTEON, some infrequent, error interrupts (RML) are handled with PCI
47f693c922Shikaru  * interrupt.  Hence, here.
48f693c922Shikaru  */
49f693c922Shikaru 
503f508e4dSsimonb void			octpci_bootstrap(struct octeon_config *);
513f508e4dSsimonb static void		octpci_init(void);
52f693c922Shikaru 
53f693c922Shikaru void
octpci_bootstrap(struct octeon_config * mcp)543f508e4dSsimonb octpci_bootstrap(struct octeon_config *mcp)
55f693c922Shikaru {
563f508e4dSsimonb 	octpci_init();
57f693c922Shikaru }
58f693c922Shikaru 
59f693c922Shikaru static void
octpci_init(void)603f508e4dSsimonb octpci_init(void)
61f693c922Shikaru {
62*09773f5bSsimonb 
63*09773f5bSsimonb 	/* XXX remove this? */
64f693c922Shikaru }
65