xref: /netbsd-src/sys/arch/mips/cavium/dev/octeon_faureg.h (revision b9fcd28bf45d108da8842b5f53af8caefd5eb745)
1*b9fcd28bSsimonb /*	$NetBSD: octeon_faureg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $	*/
2f693c922Shikaru 
3f693c922Shikaru /*
4f693c922Shikaru  * Copyright (c) 2007 Internet Initiative Japan, Inc.
5f693c922Shikaru  * All rights reserved.
6f693c922Shikaru  *
7f693c922Shikaru  * Redistribution and use in source and binary forms, with or without
8f693c922Shikaru  * modification, are permitted provided that the following conditions
9f693c922Shikaru  * are met:
10f693c922Shikaru  * 1. Redistributions of source code must retain the above copyright
11f693c922Shikaru  *    notice, this list of conditions and the following disclaimer.
12f693c922Shikaru  * 2. Redistributions in binary form must reproduce the above copyright
13f693c922Shikaru  *    notice, this list of conditions and the following disclaimer in the
14f693c922Shikaru  *    documentation and/or other materials provided with the distribution.
15f693c922Shikaru  *
16f693c922Shikaru  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17f693c922Shikaru  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18f693c922Shikaru  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19f693c922Shikaru  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20f693c922Shikaru  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21f693c922Shikaru  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22f693c922Shikaru  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23f693c922Shikaru  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24f693c922Shikaru  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25f693c922Shikaru  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26f693c922Shikaru  * SUCH DAMAGE.
27f693c922Shikaru  */
28f693c922Shikaru 
29f693c922Shikaru /*
30f693c922Shikaru  * Fetch-and-Add Operations
31f693c922Shikaru  */
32f693c922Shikaru 
33f693c922Shikaru #ifndef _OCTEON_FAUREG_H_
34f693c922Shikaru #define _OCTEON_FAUREG_H_
35f693c922Shikaru 
36*b9fcd28bSsimonb 
37*b9fcd28bSsimonb #define	FAU_MAJOR_DID			0x1e
38*b9fcd28bSsimonb #define	FAU_SUB_DID			0
39*b9fcd28bSsimonb 
40f693c922Shikaru /* ---- operations */
41f693c922Shikaru 
42*b9fcd28bSsimonb /* -- load operations */
43*b9fcd28bSsimonb #define	POW_LOAD_INCVAL			__BITS(35,14)
44*b9fcd28bSsimonb #define	POW_LOAD_TAGWAIT		__BIT(13)
45*b9fcd28bSsimonb /*      reserved			__BiTS(12,11) */
46*b9fcd28bSsimonb #define	POW_LOAD_REG			__BITS(10,0)
47*b9fcd28bSsimonb 
48*b9fcd28bSsimonb /* -- iobdma store operations */
49*b9fcd28bSsimonb 
50*b9fcd28bSsimonb #define	POW_IOBDMA_LEN			1	/* always 1 for POW */
51*b9fcd28bSsimonb #define	POW_IOBDMA_INCVAL		POW_LOAD_INCVAL
52*b9fcd28bSsimonb #define	POW_IOBDMA_TAGWAIT		POW_LOAD_TAGWAIT
53*b9fcd28bSsimonb #define	POW_IOBDMA_SIZE			__BITS(12,11)
54*b9fcd28bSsimonb #define	POW_IOBDMA_REG			POW_LOAD_REG
55*b9fcd28bSsimonb 
56*b9fcd28bSsimonb /* -- store operations */
57*b9fcd28bSsimonb /*      reserved			__BiTS(35,14) */
58*b9fcd28bSsimonb #define	POW_STORE_NOADD			__BIT(13)
59*b9fcd28bSsimonb /*      reserved			__BiTS(12,11) */
60*b9fcd28bSsimonb #define	POW_STORE_REG			__BITS(10,0)
61f693c922Shikaru 
62f693c922Shikaru #endif /* _OCTEON_FAUREG_H_ */
63