xref: /netbsd-src/sys/arch/mips/alchemy/dev/usbdreg.h (revision 0129c2494ba9f2499e44f208950876723a9d8790)
1*0129c249Sgdamore /* $NetBSD: usbdreg.h,v 1.1 2006/02/09 03:14:31 gdamore Exp $ */
2*0129c249Sgdamore 
3*0129c249Sgdamore /*
4*0129c249Sgdamore  * Copyright 2002 Wasabi Systems, Inc.
5*0129c249Sgdamore  * All rights reserved.
6*0129c249Sgdamore  *
7*0129c249Sgdamore  * Written by Simon Burge for Wasabi Systems, Inc.
8*0129c249Sgdamore  *
9*0129c249Sgdamore  * Redistribution and use in source and binary forms, with or without
10*0129c249Sgdamore  * modification, are permitted provided that the following conditions
11*0129c249Sgdamore  * are met:
12*0129c249Sgdamore  * 1. Redistributions of source code must retain the above copyright
13*0129c249Sgdamore  *    notice, this list of conditions and the following disclaimer.
14*0129c249Sgdamore  * 2. Redistributions in binary form must reproduce the above copyright
15*0129c249Sgdamore  *    notice, this list of conditions and the following disclaimer in the
16*0129c249Sgdamore  *    documentation and/or other materials provided with the distribution.
17*0129c249Sgdamore  * 3. All advertising materials mentioning features or use of this software
18*0129c249Sgdamore  *    must display the following acknowledgement:
19*0129c249Sgdamore  *      This product includes software developed for the NetBSD Project by
20*0129c249Sgdamore  *      Wasabi Systems, Inc.
21*0129c249Sgdamore  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22*0129c249Sgdamore  *    or promote products derived from this software without specific prior
23*0129c249Sgdamore  *    written permission.
24*0129c249Sgdamore  *
25*0129c249Sgdamore  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26*0129c249Sgdamore  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27*0129c249Sgdamore  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28*0129c249Sgdamore  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29*0129c249Sgdamore  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30*0129c249Sgdamore  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31*0129c249Sgdamore  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32*0129c249Sgdamore  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33*0129c249Sgdamore  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34*0129c249Sgdamore  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35*0129c249Sgdamore  * POSSIBILITY OF SUCH DAMAGE.
36*0129c249Sgdamore  */
37*0129c249Sgdamore 
38*0129c249Sgdamore #ifndef	_MIPS_ALCHEMY_DEV_USBDREG_H
39*0129c249Sgdamore #define	_MIPS_ALCHEMY_DEV_USBDREG_H
40*0129c249Sgdamore 
41*0129c249Sgdamore #define USBD_EP0RD		0x00		/* Read from endpoint 0 */
42*0129c249Sgdamore #define USBD_EP0WR		0x04		/* Write to endpoint 0 */
43*0129c249Sgdamore #define USBD_EP1WR		0x08		/* Write to endpoint 1 */
44*0129c249Sgdamore #define USBD_EP2WR		0x0c		/* Write to endpoint 2 */
45*0129c249Sgdamore #define USBD_EP3RD		0x10		/* Read from endpoint 3 */
46*0129c249Sgdamore #define USBD_EP4RD		0x14		/* Read from endpoint 4 */
47*0129c249Sgdamore #define USBD_INTEN		0x18		/* Interrupt Enable Register */
48*0129c249Sgdamore #define USBD_INTSTAT		0x1c		/* Interrupt Status Register */
49*0129c249Sgdamore #define USBD_CONFIG		0x20		/* Write Configuration Register */
50*0129c249Sgdamore #define USBD_EP0CS		0x24		/* Endpoint 0 control and status */
51*0129c249Sgdamore #define USBD_EP1CS		0x28		/* Endpoint 1 control and status */
52*0129c249Sgdamore #define USBD_EP2CS		0x2c		/* Endpoint 2 control and status */
53*0129c249Sgdamore #define USBD_EP3CS		0x30		/* Endpoint 3 control and status */
54*0129c249Sgdamore #define USBD_EP4CS		0x34		/* Endpoint 4 control and status */
55*0129c249Sgdamore #define USBD_FRAMENUM		0x38		/* Current frame number */
56*0129c249Sgdamore #define USBD_EP0RDSTAT		0x40		/* EP0 Read FIFO Status */
57*0129c249Sgdamore #define USBD_EP0WRSTAT		0x44		/* EP0 Write FIFO Status */
58*0129c249Sgdamore #define USBD_EP1WRSTAT		0x48		/* EP1 Write FIFO Status */
59*0129c249Sgdamore #define USBD_EP2WRSTAT		0x4c		/* EP2 Write FIFO Status */
60*0129c249Sgdamore #define USBD_EP3RDSTAT		0x50		/* EP3 Read FIFO Status */
61*0129c249Sgdamore #define USBD_EP4RDSTAT		0x54		/* EP4 Read FIFO Status */
62*0129c249Sgdamore #define USBD_ENABLE		0x58		/* USB Device Controller Enable */
63*0129c249Sgdamore 
64*0129c249Sgdamore #endif	/* _MIPS_ALCHEMY_DEV_USBDREG_H */
65